target/linux/mvebu/patches-4.4/049-net-mvneta-replace-MVNETA_CPU_D_CACHE_LINE_SIZE-with.patch

   1 From: Jisheng Zhang <jszhang@marvell.com>
   2 Date: Wed, 30 Mar 2016 19:55:21 +0800
   3 Subject: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with
   4  L1_CACHE_BYTES
   5
   6 The mvneta is also used in some Marvell berlin family SoCs which may
   7 have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
   8 usage with L1_CACHE_BYTES.
   9
  10 And since dma_alloc_coherent() is always cacheline size aligned, so
  11 remove the align checks.
  12
  13 Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
  14 Signed-off-by: David S. Miller <davem@davemloft.net>
  15 ---
  16
  17 --- a/drivers/net/ethernet/marvell/mvneta.c
  18 +++ b/drivers/net/ethernet/marvell/mvneta.c
  19 @@ -260,7 +260,6 @@
  20
  21  #define MVNETA_VLAN_TAG_LEN             4
  22
  23 -#define MVNETA_CPU_D_CACHE_LINE_SIZE    32
  24  #define MVNETA_TX_CSUM_DEF_SIZE                1600
  25  #define MVNETA_TX_CSUM_MAX_SIZE                9800
  26  #define MVNETA_ACC_MODE_EXT1           1
  27 @@ -300,7 +299,7 @@
  28  #define MVNETA_RX_PKT_SIZE(mtu) \
  29         ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
  30               ETH_HLEN + ETH_FCS_LEN,                        \
  31 -             MVNETA_CPU_D_CACHE_LINE_SIZE)
  32 +             L1_CACHE_BYTES)
  33
  34  #define IS_TSO_HEADER(txq, addr) \
  35         ((addr >= txq->tso_hdrs_phys) && \
  36 @@ -2762,9 +2761,6 @@ static int mvneta_rxq_init(struct mvneta
  37         if (rxq->descs == NULL)
  38                 return -ENOMEM;
  39
  40 -       BUG_ON(rxq->descs !=
  41 -              PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
  42 -
  43         rxq->last_desc = rxq->size - 1;
  44
  45         /* Set Rx descriptors queue starting address */
  46 @@ -2835,10 +2831,6 @@ static int mvneta_txq_init(struct mvneta
  47         if (txq->descs == NULL)
  48                 return -ENOMEM;
  49
  50 -       /* Make sure descriptor address is cache line size aligned  */
  51 -       BUG_ON(txq->descs !=
  52 -              PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
  53 -
  54         txq->last_desc = txq->size - 1;
  55
  56         /* Set maximum bandwidth for enabled TXQs */