tools: mkimage: provide dtc path during build
[openwrt/openwrt.git] / target / linux / mvebu / patches-4.4 / 053-ARM-dts-Add-SolidRun-Armada-388-Clearfog-A1-DT-file.patch
1 From 4c945e8556ec7ea5b19d4f8721b212f468656e0d Mon Sep 17 00:00:00 2001
2 From: Russell King <rmk+kernel@arm.linux.org.uk>
3 Date: Sun, 6 Dec 2015 21:52:06 +0000
4 Subject: [PATCH] ARM: dts: Add SolidRun Armada 388 Clearfog A1 DT file
5
6 Add support for the SolidRun Armada 388 Clearfog A1 board. This board
7 has an Armada 388 microsom, dedicated gigabit ethernet, six switched
8 gigabit ethernet ports, SFP cage, two Mini-PCIe/mSATA slots, a m.2 SATA
9 slot, and a MikroBUS connector to allow MikroBUS modules to be added.
10
11 This DT file adds support for all board facilities with the exception
12 of full SFP support.
13
14 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
15 Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
16 Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
17 ---
18 arch/arm/boot/dts/Makefile | 1 +
19 arch/arm/boot/dts/armada-388-clearfog.dts | 456 +++++++++++++++++++++
20 .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 115 ++++++
21 3 files changed, 572 insertions(+)
22 create mode 100644 arch/arm/boot/dts/armada-388-clearfog.dts
23 create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
24
25 --- a/arch/arm/boot/dts/Makefile
26 +++ b/arch/arm/boot/dts/Makefile
27 @@ -750,6 +750,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
28 armada-385-linksys-cobra.dtb \
29 armada-385-linksys-rango.dtb \
30 armada-385-linksys-shelby.dtb \
31 + armada-388-clearfog.dtb \
32 armada-388-db.dtb \
33 armada-388-gp.dtb \
34 armada-388-rd.dtb
35 --- /dev/null
36 +++ b/arch/arm/boot/dts/armada-388-clearfog.dts
37 @@ -0,0 +1,456 @@
38 +/*
39 + * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
40 + *
41 + * Copyright (C) 2015 Russell King
42 + *
43 + * This board is in development; the contents of this file work with
44 + * the A1 rev 2.0 of the board, which does not represent final
45 + * production board. Things will change, don't expect this file to
46 + * remain compatible info the future.
47 + *
48 + * This file is dual-licensed: you can use it either under the terms
49 + * of the GPL or the X11 license, at your option. Note that this dual
50 + * licensing only applies to this file, and not this project as a
51 + * whole.
52 + *
53 + * a) This file is free software; you can redistribute it and/or
54 + * modify it under the terms of the GNU General Public License
55 + * version 2 as published by the Free Software Foundation.
56 + *
57 + * This file is distributed in the hope that it will be useful
58 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
59 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
60 + * GNU General Public License for more details.
61 + *
62 + * Or, alternatively
63 + *
64 + * b) Permission is hereby granted, free of charge, to any person
65 + * obtaining a copy of this software and associated documentation
66 + * files (the "Software"), to deal in the Software without
67 + * restriction, including without limitation the rights to use
68 + * copy, modify, merge, publish, distribute, sublicense, and/or
69 + * sell copies of the Software, and to permit persons to whom the
70 + * Software is furnished to do so, subject to the following
71 + * conditions:
72 + *
73 + * The above copyright notice and this permission notice shall be
74 + * included in all copies or substantial portions of the Software.
75 + *
76 + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
77 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
78 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
79 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
80 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
81 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
82 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
83 + * OTHER DEALINGS IN THE SOFTWARE.
84 + */
85 +
86 +/dts-v1/;
87 +#include "armada-388.dtsi"
88 +#include "armada-38x-solidrun-microsom.dtsi"
89 +
90 +/ {
91 + model = "SolidRun Clearfog A1";
92 + compatible = "solidrun,clearfog-a1", "marvell,armada388",
93 + "marvell,armada385", "marvell,armada380";
94 +
95 + aliases {
96 + /* So that mvebu u-boot can update the MAC addresses */
97 + ethernet1 = &eth0;
98 + ethernet2 = &eth1;
99 + ethernet3 = &eth2;
100 + };
101 +
102 + chosen {
103 + stdout-path = "serial0:115200n8";
104 + };
105 +
106 + reg_3p3v: regulator-3p3v {
107 + compatible = "regulator-fixed";
108 + regulator-name = "3P3V";
109 + regulator-min-microvolt = <3300000>;
110 + regulator-max-microvolt = <3300000>;
111 + regulator-always-on;
112 + };
113 +
114 + soc {
115 + internal-regs {
116 + ethernet@30000 {
117 + phy-mode = "sgmii";
118 + status = "okay";
119 +
120 + fixed-link {
121 + speed = <1000>;
122 + full-duplex;
123 + };
124 + };
125 +
126 + ethernet@34000 {
127 + phy-mode = "sgmii";
128 + status = "okay";
129 +
130 + fixed-link {
131 + speed = <1000>;
132 + full-duplex;
133 + };
134 + };
135 +
136 + i2c@11000 {
137 + /* Is there anything on this? */
138 + clock-frequency = <100000>;
139 + pinctrl-0 = <&i2c0_pins>;
140 + pinctrl-names = "default";
141 + status = "okay";
142 +
143 + /*
144 + * PCA9655 GPIO expander, up to 1MHz clock.
145 + * 0-CON3 CLKREQ#
146 + * 1-CON3 PERST#
147 + * 2-CON2 PERST#
148 + * 3-CON3 W_DISABLE
149 + * 4-CON2 CLKREQ#
150 + * 5-USB3 overcurrent
151 + * 6-USB3 power
152 + * 7-CON2 W_DISABLE
153 + * 8-JP4 P1
154 + * 9-JP4 P4
155 + * 10-JP4 P5
156 + * 11-m.2 DEVSLP
157 + * 12-SFP_LOS
158 + * 13-SFP_TX_FAULT
159 + * 14-SFP_TX_DISABLE
160 + * 15-SFP_MOD_DEF0
161 + */
162 + expander0: gpio-expander@20 {
163 + /*
164 + * This is how it should be:
165 + * compatible = "onnn,pca9655",
166 + * "nxp,pca9555";
167 + * but you can't do this because of
168 + * the way I2C works.
169 + */
170 + compatible = "nxp,pca9555";
171 + gpio-controller;
172 + #gpio-cells = <2>;
173 + reg = <0x20>;
174 +
175 + pcie1_0_clkreq {
176 + gpio-hog;
177 + gpios = <0 GPIO_ACTIVE_LOW>;
178 + input;
179 + line-name = "pcie1.0-clkreq";
180 + };
181 + pcie1_0_w_disable {
182 + gpio-hog;
183 + gpios = <3 GPIO_ACTIVE_LOW>;
184 + output-low;
185 + line-name = "pcie1.0-w-disable";
186 + };
187 + pcie2_0_clkreq {
188 + gpio-hog;
189 + gpios = <4 GPIO_ACTIVE_LOW>;
190 + input;
191 + line-name = "pcie2.0-clkreq";
192 + };
193 + pcie2_0_w_disable {
194 + gpio-hog;
195 + gpios = <7 GPIO_ACTIVE_LOW>;
196 + output-low;
197 + line-name = "pcie2.0-w-disable";
198 + };
199 + usb3_ilimit {
200 + gpio-hog;
201 + gpios = <5 GPIO_ACTIVE_LOW>;
202 + input;
203 + line-name = "usb3-current-limit";
204 + };
205 + usb3_power {
206 + gpio-hog;
207 + gpios = <6 GPIO_ACTIVE_HIGH>;
208 + output-high;
209 + line-name = "usb3-power";
210 + };
211 + m2_devslp {
212 + gpio-hog;
213 + gpios = <11 GPIO_ACTIVE_HIGH>;
214 + output-low;
215 + line-name = "m.2 devslp";
216 + };
217 + sfp_los {
218 + /* SFP loss of signal */
219 + gpio-hog;
220 + gpios = <12 GPIO_ACTIVE_HIGH>;
221 + input;
222 + line-name = "sfp-los";
223 + };
224 + sfp_tx_fault {
225 + /* SFP laser fault */
226 + gpio-hog;
227 + gpios = <13 GPIO_ACTIVE_HIGH>;
228 + input;
229 + line-name = "sfp-tx-fault";
230 + };
231 + sfp_tx_disable {
232 + /* SFP transmit disable */
233 + gpio-hog;
234 + gpios = <14 GPIO_ACTIVE_HIGH>;
235 + output-low;
236 + line-name = "sfp-tx-disable";
237 + };
238 + sfp_mod_def0 {
239 + /* SFP module present */
240 + gpio-hog;
241 + gpios = <15 GPIO_ACTIVE_LOW>;
242 + input;
243 + line-name = "sfp-mod-def0";
244 + };
245 + };
246 +
247 + /* The MCP3021 is 100kHz clock only */
248 + mikrobus_adc: mcp3021@4c {
249 + compatible = "microchip,mcp3021";
250 + reg = <0x4c>;
251 + };
252 +
253 + /* Also something at 0x64 */
254 + };
255 +
256 + i2c@11100 {
257 + /*
258 + * Routed to SFP, mikrobus, and PCIe.
259 + * SFP limits this to 100kHz, and requires
260 + * an AT24C01A/02/04 with address pins tied
261 + * low, which takes addresses 0x50 and 0x51.
262 + * Mikrobus doesn't specify beyond an I2C
263 + * bus being present.
264 + * PCIe uses ARP to assign addresses, or
265 + * 0x63-0x64.
266 + */
267 + clock-frequency = <100000>;
268 + pinctrl-0 = <&clearfog_i2c1_pins>;
269 + pinctrl-names = "default";
270 + status = "okay";
271 + };
272 +
273 + mdio@72004 {
274 + pinctrl-0 = <&mdio_pins>;
275 + pinctrl-names = "default";
276 +
277 + phy_dedicated: ethernet-phy@0 {
278 + /*
279 + * Annoyingly, the marvell phy driver
280 + * configures the LED register, rather
281 + * than preserving reset-loaded setting.
282 + * We undo that rubbish here.
283 + */
284 + marvell,reg-init = <3 16 0 0x101e>;
285 + reg = <0>;
286 + };
287 + };
288 +
289 + pinctrl@18000 {
290 + clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
291 + marvell,pins = "mpp46";
292 + marvell,function = "ref";
293 + };
294 + clearfog_dsa0_pins: clearfog-dsa0-pins {
295 + marvell,pins = "mpp23", "mpp41";
296 + marvell,function = "gpio";
297 + };
298 + clearfog_i2c1_pins: i2c1-pins {
299 + /* SFP, PCIe, mSATA, mikrobus */
300 + marvell,pins = "mpp26", "mpp27";
301 + marvell,function = "i2c1";
302 + };
303 + clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
304 + marvell,pins = "mpp20";
305 + marvell,function = "gpio";
306 + };
307 + clearfog_sdhci_pins: clearfog-sdhci-pins {
308 + marvell,pins = "mpp21", "mpp28",
309 + "mpp37", "mpp38",
310 + "mpp39", "mpp40";
311 + marvell,function = "sd0";
312 + };
313 + clearfog_spi1_cs_pins: spi1-cs-pins {
314 + marvell,pins = "mpp55";
315 + marvell,function = "spi1";
316 + };
317 + mikro_pins: mikro-pins {
318 + /* int: mpp22 rst: mpp29 */
319 + marvell,pins = "mpp22", "mpp29";
320 + marvell,function = "gpio";
321 + };
322 + mikro_spi_pins: mikro-spi-pins {
323 + marvell,pins = "mpp43";
324 + marvell,function = "spi1";
325 + };
326 + mikro_uart_pins: mikro-uart-pins {
327 + marvell,pins = "mpp24", "mpp25";
328 + marvell,function = "ua1";
329 + };
330 + rear_button_pins: rear-button-pins {
331 + marvell,pins = "mpp34";
332 + marvell,function = "gpio";
333 + };
334 + };
335 +
336 + sata@a8000 {
337 + /* pinctrl? */
338 + status = "okay";
339 + };
340 +
341 + sata@e0000 {
342 + /* pinctrl? */
343 + status = "okay";
344 + };
345 +
346 + sdhci@d8000 {
347 + bus-width = <4>;
348 + cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
349 + no-1-8-v;
350 + pinctrl-0 = <&clearfog_sdhci_pins
351 + &clearfog_sdhci_cd_pins>;
352 + pinctrl-names = "default";
353 + status = "okay";
354 + vmmc = <&reg_3p3v>;
355 + wp-inverted;
356 + };
357 +
358 + serial@12100 {
359 + /* mikrobus uart */
360 + pinctrl-0 = <&mikro_uart_pins>;
361 + pinctrl-names = "default";
362 + status = "okay";
363 + };
364 +
365 + spi@10680 {
366 + /*
367 + * We don't seem to have the W25Q32 on the
368 + * A1 Rev 2.0 boards, so disable SPI.
369 + * CS0: W25Q32 (doesn't appear to be present)
370 + * CS1:
371 + * CS2: mikrobus
372 + */
373 + pinctrl-0 = <&spi1_pins
374 + &clearfog_spi1_cs_pins
375 + &mikro_spi_pins>;
376 + pinctrl-names = "default";
377 + status = "okay";
378 +
379 + spi-flash@0 {
380 + #address-cells = <1>;
381 + #size-cells = <0>;
382 + compatible = "w25q32", "jedec,spi-nor";
383 + reg = <0>; /* Chip select 0 */
384 + spi-max-frequency = <3000000>;
385 + status = "disabled";
386 + };
387 + };
388 +
389 + usb@58000 {
390 + /* CON3, nearest power. */
391 + status = "okay";
392 + };
393 +
394 + usb3@f0000 {
395 + /* CON2, nearest CPU, USB2 only. */
396 + status = "okay";
397 + };
398 +
399 + usb3@f8000 {
400 + /* CON7 */
401 + status = "okay";
402 + };
403 + };
404 +
405 + pcie-controller {
406 + status = "okay";
407 + /*
408 + * The two PCIe units are accessible through
409 + * the mini-PCIe connectors on the board.
410 + */
411 + pcie@2,0 {
412 + /* Port 1, Lane 0. CON3, nearest power. */
413 + reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
414 + status = "okay";
415 + };
416 + pcie@3,0 {
417 + /* Port 2, Lane 0. CON2, nearest CPU. */
418 + reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
419 + status = "okay";
420 + };
421 + };
422 + };
423 +
424 + dsa@0 {
425 + compatible = "marvell,dsa";
426 + dsa,ethernet = <&eth1>;
427 + dsa,mii-bus = <&mdio>;
428 + pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
429 + pinctrl-names = "default";
430 + #address-cells = <2>;
431 + #size-cells = <0>;
432 +
433 + switch@0 {
434 + #address-cells = <1>;
435 + #size-cells = <0>;
436 + reg = <4 0>;
437 +
438 + port@0 {
439 + reg = <0>;
440 + label = "lan1";
441 + };
442 +
443 + port@1 {
444 + reg = <1>;
445 + label = "lan2";
446 + };
447 +
448 + port@2 {
449 + reg = <2>;
450 + label = "lan3";
451 + };
452 +
453 + port@3 {
454 + reg = <3>;
455 + label = "lan4";
456 + };
457 +
458 + port@4 {
459 + reg = <4>;
460 + label = "lan5";
461 + };
462 +
463 + port@5 {
464 + reg = <5>;
465 + label = "cpu";
466 + };
467 +
468 + port@6 {
469 + /* 88E1512 external phy */
470 + reg = <6>;
471 + label = "lan6";
472 + fixed-link {
473 + speed = <1000>;
474 + full-duplex;
475 + };
476 + };
477 + };
478 + };
479 +
480 + gpio-keys {
481 + compatible = "gpio-keys";
482 + pinctrl-0 = <&rear_button_pins>;
483 + pinctrl-names = "default";
484 +
485 + button_0 {
486 + /* The rear SW3 button */
487 + label = "Rear Button";
488 + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
489 + linux,can-disable;
490 + linux,code = <BTN_0>;
491 + };
492 + };
493 +};
494 --- /dev/null
495 +++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
496 @@ -0,0 +1,115 @@
497 +/*
498 + * Device Tree file for SolidRun Armada 38x Microsom
499 + *
500 + * Copyright (C) 2015 Russell King
501 + *
502 + * This board is in development; the contents of this file work with
503 + * the A1 rev 2.0 of the board, which does not represent final
504 + * production board. Things will change, don't expect this file to
505 + * remain compatible info the future.
506 + *
507 + * This file is dual-licensed: you can use it either under the terms
508 + * of the GPL or the X11 license, at your option. Note that this dual
509 + * licensing only applies to this file, and not this project as a
510 + * whole.
511 + *
512 + * a) This file is free software; you can redistribute it and/or
513 + * modify it under the terms of the GNU General Public License
514 + * version 2 as published by the Free Software Foundation.
515 + *
516 + * This file is distributed in the hope that it will be useful
517 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
518 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
519 + * GNU General Public License for more details.
520 + *
521 + * Or, alternatively
522 + *
523 + * b) Permission is hereby granted, free of charge, to any person
524 + * obtaining a copy of this software and associated documentation
525 + * files (the "Software"), to deal in the Software without
526 + * restriction, including without limitation the rights to use
527 + * copy, modify, merge, publish, distribute, sublicense, and/or
528 + * sell copies of the Software, and to permit persons to whom the
529 + * Software is furnished to do so, subject to the following
530 + * conditions:
531 + *
532 + * The above copyright notice and this permission notice shall be
533 + * included in all copies or substantial portions of the Software.
534 + *
535 + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
536 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
537 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
538 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
539 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
540 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
541 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
542 + * OTHER DEALINGS IN THE SOFTWARE.
543 + */
544 +#include <dt-bindings/input/input.h>
545 +#include <dt-bindings/gpio/gpio.h>
546 +
547 +/ {
548 + memory {
549 + device_type = "memory";
550 + reg = <0x00000000 0x10000000>; /* 256 MB */
551 + };
552 +
553 + soc {
554 + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
555 + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
556 + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
557 + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
558 +
559 + internal-regs {
560 + ethernet@70000 {
561 + pinctrl-0 = <&ge0_rgmii_pins>;
562 + pinctrl-names = "default";
563 + phy = <&phy_dedicated>;
564 + phy-mode = "rgmii-id";
565 + status = "okay";
566 + };
567 +
568 + mdio@72004 {
569 + /*
570 + * Add the phy clock here, so the phy can be
571 + * accessed to read its IDs prior to binding
572 + * with the driver.
573 + */
574 + pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
575 + pinctrl-names = "default";
576 +
577 + phy_dedicated: ethernet-phy@0 {
578 + /*
579 + * Annoyingly, the marvell phy driver
580 + * configures the LED register, rather
581 + * than preserving reset-loaded setting.
582 + * We undo that rubbish here.
583 + */
584 + marvell,reg-init = <3 16 0 0x101e>;
585 + reg = <0>;
586 + };
587 + };
588 +
589 + pinctrl@18000 {
590 + microsom_phy_clk_pins: microsom-phy-clk-pins {
591 + marvell,pins = "mpp45";
592 + marvell,function = "ref";
593 + };
594 + };
595 +
596 + rtc@a3800 {
597 + /*
598 + * If the rtc doesn't work, run "date reset"
599 + * twice in u-boot.
600 + */
601 + status = "okay";
602 + };
603 +
604 + serial@12000 {
605 + pinctrl-0 = <&uart0_pins>;
606 + pinctrl-names = "default";
607 + status = "okay";
608 + };
609 + };
610 + };
611 +};