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[openwrt/openwrt.git] / target / linux / mvebu / patches-4.4 / 134-net-mvneta-convert-to-phylink.patch
1 From e268be0ddc666f4a98db462cbed2a97637e82b5c Mon Sep 17 00:00:00 2001
2 From: Russell King <rmk+kernel@arm.linux.org.uk>
3 Date: Wed, 16 Sep 2015 21:27:10 +0100
4 Subject: [PATCH 722/744] net: mvneta: convert to phylink
5
6 Convert mvneta to use phylink, which models the MAC to PHY link in
7 a generic, reusable form.
8
9 Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
10 ---
11 drivers/net/ethernet/marvell/Kconfig | 2 +-
12 drivers/net/ethernet/marvell/mvneta.c | 451 +++++++++++++++++-----------------
13 2 files changed, 227 insertions(+), 226 deletions(-)
14
15 --- a/drivers/net/ethernet/marvell/Kconfig
16 +++ b/drivers/net/ethernet/marvell/Kconfig
17 @@ -58,7 +58,7 @@ config MVNETA
18 tristate "Marvell Armada 370/38x/XP network interface support"
19 depends on PLAT_ORION
20 select MVMDIO
21 - select FIXED_PHY
22 + select PHYLINK
23 ---help---
24 This driver supports the network interface units in the
25 Marvell ARMADA XP, ARMADA 370 and ARMADA 38x SoC family.
26 --- a/drivers/net/ethernet/marvell/mvneta.c
27 +++ b/drivers/net/ethernet/marvell/mvneta.c
28 @@ -28,6 +28,7 @@
29 #include <linux/of_mdio.h>
30 #include <linux/of_net.h>
31 #include <linux/phy.h>
32 +#include <linux/phylink.h>
33 #include <linux/platform_device.h>
34 #include <linux/skbuff.h>
35 #include <net/hwbm.h>
36 @@ -188,6 +189,7 @@
37 #define MVNETA_GMAC_CTRL_0 0x2c00
38 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
39 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
40 +#define MVNETA_GMAC0_PORT_1000BASE_X BIT(1)
41 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
42 #define MVNETA_GMAC_CTRL_2 0x2c08
43 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
44 @@ -203,13 +205,19 @@
45 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
46 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
47 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
48 +#define MVNETA_GMAC_AN_COMPLETE BIT(11)
49 +#define MVNETA_GMAC_SYNC_OK BIT(14)
50 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
51 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
52 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
53 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
54 +#define MVNETA_GMAC_AN_BYPASS_ENABLE BIT(3)
55 +#define MVNETA_GMAC_INBAND_RESTART_AN BIT(4)
56 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
57 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
58 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
59 +#define MVNETA_GMAC_CONFIG_FLOW_CTRL BIT(8)
60 +#define MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL BIT(9)
61 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
62 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
63 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
64 @@ -396,15 +404,9 @@ struct mvneta_port {
65 u16 tx_ring_size;
66 u16 rx_ring_size;
67
68 - struct mii_bus *mii_bus;
69 - struct phy_device *phy_dev;
70 - phy_interface_t phy_interface;
71 - struct device_node *phy_node;
72 - unsigned int link;
73 - unsigned int duplex;
74 - unsigned int speed;
75 + struct device_node *dn;
76 unsigned int tx_csum_limit;
77 - unsigned int use_inband_status:1;
78 + struct phylink *phylink;
79
80 struct mvneta_bm *bm_priv;
81 struct mvneta_bm_pool *pool_long;
82 @@ -1177,10 +1179,6 @@ static void mvneta_port_disable(struct m
83 val &= ~MVNETA_GMAC0_PORT_ENABLE;
84 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
85
86 - pp->link = 0;
87 - pp->duplex = -1;
88 - pp->speed = 0;
89 -
90 udelay(200);
91 }
92
93 @@ -1240,44 +1238,6 @@ static void mvneta_set_other_mcast_table
94 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
95 }
96
97 -static void mvneta_set_autoneg(struct mvneta_port *pp, int enable)
98 -{
99 - u32 val;
100 -
101 - if (enable) {
102 - val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
103 - val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
104 - MVNETA_GMAC_FORCE_LINK_DOWN |
105 - MVNETA_GMAC_AN_FLOW_CTRL_EN);
106 - val |= MVNETA_GMAC_INBAND_AN_ENABLE |
107 - MVNETA_GMAC_AN_SPEED_EN |
108 - MVNETA_GMAC_AN_DUPLEX_EN;
109 - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
110 -
111 - val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
112 - val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
113 - mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
114 -
115 - val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
116 - val |= MVNETA_GMAC2_INBAND_AN_ENABLE;
117 - mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
118 - } else {
119 - val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
120 - val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE |
121 - MVNETA_GMAC_AN_SPEED_EN |
122 - MVNETA_GMAC_AN_DUPLEX_EN);
123 - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
124 -
125 - val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
126 - val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
127 - mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
128 -
129 - val = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
130 - val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE;
131 - mvreg_write(pp, MVNETA_GMAC_CTRL_2, val);
132 - }
133 -}
134 -
135 static void mvneta_percpu_unmask_interrupt(void *arg)
136 {
137 struct mvneta_port *pp = arg;
138 @@ -1425,7 +1385,6 @@ static void mvneta_defaults_set(struct m
139 val &= ~MVNETA_PHY_POLLING_ENABLE;
140 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
141
142 - mvneta_set_autoneg(pp, pp->use_inband_status);
143 mvneta_set_ucast_table(pp, -1);
144 mvneta_set_special_mcast_table(pp, -1);
145 mvneta_set_other_mcast_table(pp, -1);
146 @@ -2618,26 +2577,11 @@ static irqreturn_t mvneta_isr(int irq, v
147 return IRQ_HANDLED;
148 }
149
150 -static int mvneta_fixed_link_update(struct mvneta_port *pp,
151 - struct phy_device *phy)
152 +static void mvneta_link_change(struct mvneta_port *pp)
153 {
154 - struct fixed_phy_status status;
155 - struct fixed_phy_status changed = {};
156 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
157
158 - status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
159 - if (gmac_stat & MVNETA_GMAC_SPEED_1000)
160 - status.speed = SPEED_1000;
161 - else if (gmac_stat & MVNETA_GMAC_SPEED_100)
162 - status.speed = SPEED_100;
163 - else
164 - status.speed = SPEED_10;
165 - status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
166 - changed.link = 1;
167 - changed.speed = 1;
168 - changed.duplex = 1;
169 - fixed_phy_update_state(phy, &status, &changed);
170 - return 0;
171 + phylink_mac_change(pp->phylink, !!(gmac_stat & MVNETA_GMAC_LINK_UP));
172 }
173
174 /* NAPI handler
175 @@ -2666,12 +2610,11 @@ static int mvneta_poll(struct napi_struc
176 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
177
178 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
179 - if (pp->use_inband_status && (cause_misc &
180 - (MVNETA_CAUSE_PHY_STATUS_CHANGE |
181 - MVNETA_CAUSE_LINK_CHANGE |
182 - MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
183 - mvneta_fixed_link_update(pp, pp->phy_dev);
184 - }
185 +
186 + if (cause_misc & (MVNETA_CAUSE_PHY_STATUS_CHANGE |
187 + MVNETA_CAUSE_LINK_CHANGE |
188 + MVNETA_CAUSE_PSC_SYNC_CHANGE))
189 + mvneta_link_change(pp);
190 }
191
192 /* Release Tx descriptors */
193 @@ -2987,7 +2930,7 @@ static void mvneta_start_dev(struct mvne
194 MVNETA_CAUSE_LINK_CHANGE |
195 MVNETA_CAUSE_PSC_SYNC_CHANGE);
196
197 - phy_start(pp->phy_dev);
198 + phylink_start(pp->phylink);
199 netif_tx_start_all_queues(pp->dev);
200 }
201
202 @@ -2995,7 +2938,7 @@ static void mvneta_stop_dev(struct mvnet
203 {
204 unsigned int cpu;
205
206 - phy_stop(pp->phy_dev);
207 + phylink_stop(pp->phylink);
208
209 for_each_online_cpu(cpu) {
210 struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
211 @@ -3165,99 +3108,219 @@ static int mvneta_set_mac_addr(struct ne
212 return 0;
213 }
214
215 -static void mvneta_adjust_link(struct net_device *ndev)
216 +static int mvneta_mac_support(struct net_device *ndev, unsigned int mode,
217 + struct phylink_link_state *state)
218 +{
219 + switch (mode) {
220 + case MLO_AN_8023Z:
221 + state->supported = SUPPORTED_1000baseT_Full |
222 + SUPPORTED_Autoneg | SUPPORTED_Pause;
223 + state->advertising = ADVERTISED_1000baseT_Full |
224 + ADVERTISED_Autoneg | ADVERTISED_Pause;
225 + state->an_enabled = 1;
226 + break;
227 +
228 + case MLO_AN_FIXED:
229 + break;
230 +
231 + default:
232 + state->supported = PHY_10BT_FEATURES |
233 + PHY_100BT_FEATURES |
234 + SUPPORTED_1000baseT_Full |
235 + SUPPORTED_Autoneg;
236 + state->advertising = ADVERTISED_10baseT_Half |
237 + ADVERTISED_10baseT_Full |
238 + ADVERTISED_100baseT_Half |
239 + ADVERTISED_100baseT_Full |
240 + ADVERTISED_1000baseT_Full |
241 + ADVERTISED_Autoneg;
242 + state->an_enabled = 1;
243 + break;
244 + }
245 + return 0;
246 +}
247 +
248 +static int mvneta_mac_link_state(struct net_device *ndev,
249 + struct phylink_link_state *state)
250 {
251 struct mvneta_port *pp = netdev_priv(ndev);
252 - struct phy_device *phydev = pp->phy_dev;
253 - int status_change = 0;
254 + u32 gmac_stat;
255
256 - if (phydev->link) {
257 - if ((pp->speed != phydev->speed) ||
258 - (pp->duplex != phydev->duplex)) {
259 - u32 val;
260 -
261 - val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
262 - val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
263 - MVNETA_GMAC_CONFIG_GMII_SPEED |
264 - MVNETA_GMAC_CONFIG_FULL_DUPLEX);
265 -
266 - if (phydev->duplex)
267 - val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
268 -
269 - if (phydev->speed == SPEED_1000)
270 - val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
271 - else if (phydev->speed == SPEED_100)
272 - val |= MVNETA_GMAC_CONFIG_MII_SPEED;
273 + gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
274
275 - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
276 + if (gmac_stat & MVNETA_GMAC_SPEED_1000)
277 + state->speed = SPEED_1000;
278 + else if (gmac_stat & MVNETA_GMAC_SPEED_100)
279 + state->speed = SPEED_100;
280 + else
281 + state->speed = SPEED_10;
282
283 - pp->duplex = phydev->duplex;
284 - pp->speed = phydev->speed;
285 - }
286 + state->an_complete = !!(gmac_stat & MVNETA_GMAC_AN_COMPLETE);
287 + state->sync = !!(gmac_stat & MVNETA_GMAC_SYNC_OK);
288 + state->link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
289 + state->duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
290 +
291 + state->pause = 0;
292 + if (gmac_stat & MVNETA_GMAC_RX_FLOW_CTRL_ENABLE)
293 + state->pause |= MLO_PAUSE_RX;
294 + if (gmac_stat & MVNETA_GMAC_TX_FLOW_CTRL_ENABLE)
295 + state->pause |= MLO_PAUSE_TX;
296 +
297 + return 1;
298 +}
299 +
300 +static void mvneta_mac_an_restart(struct net_device *ndev, unsigned int mode)
301 +{
302 + struct mvneta_port *pp = netdev_priv(ndev);
303 +
304 + if (mode == MLO_AN_8023Z) {
305 + u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
306 +
307 + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
308 + gmac_an | MVNETA_GMAC_INBAND_RESTART_AN);
309 + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
310 + gmac_an & ~MVNETA_GMAC_INBAND_RESTART_AN);
311 }
312 +}
313
314 - if (phydev->link != pp->link) {
315 - if (!phydev->link) {
316 - pp->duplex = -1;
317 - pp->speed = 0;
318 - }
319 +static void mvneta_mac_config(struct net_device *ndev, unsigned int mode,
320 + const struct phylink_link_state *state)
321 +{
322 + struct mvneta_port *pp = netdev_priv(ndev);
323 + u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
324 + u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
325 + u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
326 + u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
327 +
328 + new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
329 + new_ctrl2 = gmac_ctrl2 & ~MVNETA_GMAC2_INBAND_AN_ENABLE;
330 + new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
331 + new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
332 + MVNETA_GMAC_INBAND_RESTART_AN |
333 + MVNETA_GMAC_CONFIG_MII_SPEED |
334 + MVNETA_GMAC_CONFIG_GMII_SPEED |
335 + MVNETA_GMAC_AN_SPEED_EN |
336 + MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL |
337 + MVNETA_GMAC_CONFIG_FLOW_CTRL |
338 + MVNETA_GMAC_AN_FLOW_CTRL_EN |
339 + MVNETA_GMAC_CONFIG_FULL_DUPLEX |
340 + MVNETA_GMAC_AN_DUPLEX_EN);
341 +
342 + if (state->advertising & ADVERTISED_Pause)
343 + new_an |= MVNETA_GMAC_ADVERT_SYM_FLOW_CTRL;
344 +
345 + switch (mode) {
346 + case MLO_AN_SGMII:
347 + /* SGMII mode receives the state from the PHY */
348 + new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
349 + new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
350 + new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
351 + MVNETA_GMAC_FORCE_LINK_PASS)) |
352 + MVNETA_GMAC_INBAND_AN_ENABLE |
353 + MVNETA_GMAC_AN_SPEED_EN |
354 + MVNETA_GMAC_AN_DUPLEX_EN;
355 + break;
356 +
357 + case MLO_AN_8023Z:
358 + /* 802.3z negotiation - only 1000base-X */
359 + new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
360 + new_clk |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
361 + new_an = (new_an & ~(MVNETA_GMAC_FORCE_LINK_DOWN |
362 + MVNETA_GMAC_FORCE_LINK_PASS)) |
363 + MVNETA_GMAC_INBAND_AN_ENABLE |
364 + MVNETA_GMAC_CONFIG_GMII_SPEED |
365 + /* The MAC only supports FD mode */
366 + MVNETA_GMAC_CONFIG_FULL_DUPLEX;
367 +
368 + if (state->an_enabled)
369 + new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
370 + break;
371
372 - pp->link = phydev->link;
373 - status_change = 1;
374 + default:
375 + /* Phy or fixed speed */
376 + if (state->duplex)
377 + new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
378 +
379 + if (state->speed == SPEED_1000)
380 + new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
381 + else if (state->speed == SPEED_100)
382 + new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
383 + break;
384 }
385
386 - if (status_change) {
387 - if (phydev->link) {
388 - if (!pp->use_inband_status) {
389 - u32 val = mvreg_read(pp,
390 - MVNETA_GMAC_AUTONEG_CONFIG);
391 - val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
392 - val |= MVNETA_GMAC_FORCE_LINK_PASS;
393 - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
394 - val);
395 - }
396 - mvneta_port_up(pp);
397 - } else {
398 - if (!pp->use_inband_status) {
399 - u32 val = mvreg_read(pp,
400 - MVNETA_GMAC_AUTONEG_CONFIG);
401 - val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
402 - val |= MVNETA_GMAC_FORCE_LINK_DOWN;
403 - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
404 - val);
405 - }
406 - mvneta_port_down(pp);
407 - }
408 - phy_print_status(phydev);
409 + /* Armada 370 documentation says we can only change the port mode
410 + * and in-band enable when the link is down, so force it down
411 + * while making these changes. We also do this for GMAC_CTRL2 */
412 + if ((new_ctrl0 ^ gmac_ctrl0) & MVNETA_GMAC0_PORT_1000BASE_X ||
413 + (new_ctrl2 ^ gmac_ctrl2) & MVNETA_GMAC2_INBAND_AN_ENABLE ||
414 + (new_an ^ gmac_an) & MVNETA_GMAC_INBAND_AN_ENABLE) {
415 + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
416 + (gmac_an & ~MVNETA_GMAC_FORCE_LINK_PASS) |
417 + MVNETA_GMAC_FORCE_LINK_DOWN);
418 + }
419 +
420 + if (new_ctrl0 != gmac_ctrl0)
421 + mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
422 + if (new_ctrl2 != gmac_ctrl2)
423 + mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
424 + if (new_clk != gmac_clk)
425 + mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
426 + if (new_an != gmac_an)
427 + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
428 +}
429 +
430 +static void mvneta_mac_link_down(struct net_device *ndev, unsigned int mode)
431 +{
432 + struct mvneta_port *pp = netdev_priv(ndev);
433 + u32 val;
434 +
435 + mvneta_port_down(pp);
436 +
437 + if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED) {
438 + val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
439 + val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
440 + val |= MVNETA_GMAC_FORCE_LINK_DOWN;
441 + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
442 }
443 }
444
445 -static int mvneta_mdio_probe(struct mvneta_port *pp)
446 +static void mvneta_mac_link_up(struct net_device *ndev, unsigned int mode,
447 + struct phy_device *phy)
448 {
449 - struct phy_device *phy_dev;
450 + struct mvneta_port *pp = netdev_priv(ndev);
451 + u32 val;
452
453 - phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
454 - pp->phy_interface);
455 - if (!phy_dev) {
456 - netdev_err(pp->dev, "could not find the PHY\n");
457 - return -ENODEV;
458 - }
459 -
460 - phy_dev->supported &= PHY_GBIT_FEATURES;
461 - phy_dev->advertising = phy_dev->supported;
462 -
463 - pp->phy_dev = phy_dev;
464 - pp->link = 0;
465 - pp->duplex = 0;
466 - pp->speed = 0;
467 + if (mode == MLO_AN_PHY || mode == MLO_AN_FIXED) {
468 + val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
469 + val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
470 + val |= MVNETA_GMAC_FORCE_LINK_PASS;
471 + mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
472 + }
473
474 - return 0;
475 + mvneta_port_up(pp);
476 +}
477 +
478 +static const struct phylink_mac_ops mvneta_phylink_ops = {
479 + .mac_get_support = mvneta_mac_support,
480 + .mac_link_state = mvneta_mac_link_state,
481 + .mac_an_restart = mvneta_mac_an_restart,
482 + .mac_config = mvneta_mac_config,
483 + .mac_link_down = mvneta_mac_link_down,
484 + .mac_link_up = mvneta_mac_link_up,
485 +};
486 +
487 +static int mvneta_mdio_probe(struct mvneta_port *pp)
488 +{
489 + int err = phylink_of_phy_connect(pp->phylink, pp->dn);
490 + if (err)
491 + netdev_err(pp->dev, "could not attach PHY\n");
492 +
493 + return err;
494 }
495
496 static void mvneta_mdio_remove(struct mvneta_port *pp)
497 {
498 - phy_disconnect(pp->phy_dev);
499 - pp->phy_dev = NULL;
500 + phylink_disconnect_phy(pp->phylink);
501 }
502
503 /* Electing a CPU must be done in an atomic way: it should be done
504 @@ -3505,10 +3568,7 @@ static int mvneta_ioctl(struct net_devic
505 {
506 struct mvneta_port *pp = netdev_priv(dev);
507
508 - if (!pp->phy_dev)
509 - return -ENOTSUPP;
510 -
511 - return phy_mii_ioctl(pp->phy_dev, ifr, cmd);
512 + return phylink_mii_ioctl(pp->phylink, ifr, cmd);
513 }
514
515 /* Ethtool methods */
516 @@ -3518,54 +3578,15 @@ int mvneta_ethtool_get_settings(struct n
517 {
518 struct mvneta_port *pp = netdev_priv(dev);
519
520 - if (!pp->phy_dev)
521 - return -ENODEV;
522 -
523 - return phy_ethtool_gset(pp->phy_dev, cmd);
524 + return phylink_ethtool_get_settings(pp->phylink, cmd);
525 }
526
527 /* Set settings (phy address, speed) for ethtools */
528 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
529 {
530 struct mvneta_port *pp = netdev_priv(dev);
531 - struct phy_device *phydev = pp->phy_dev;
532 -
533 - if (!phydev)
534 - return -ENODEV;
535
536 - if ((cmd->autoneg == AUTONEG_ENABLE) != pp->use_inband_status) {
537 - u32 val;
538 -
539 - mvneta_set_autoneg(pp, cmd->autoneg == AUTONEG_ENABLE);
540 -
541 - if (cmd->autoneg == AUTONEG_DISABLE) {
542 - val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
543 - val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
544 - MVNETA_GMAC_CONFIG_GMII_SPEED |
545 - MVNETA_GMAC_CONFIG_FULL_DUPLEX);
546 -
547 - if (phydev->duplex)
548 - val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
549 -
550 - if (phydev->speed == SPEED_1000)
551 - val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
552 - else if (phydev->speed == SPEED_100)
553 - val |= MVNETA_GMAC_CONFIG_MII_SPEED;
554 -
555 - mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
556 - }
557 -
558 - pp->use_inband_status = (cmd->autoneg == AUTONEG_ENABLE);
559 - netdev_info(pp->dev, "autoneg status set to %i\n",
560 - pp->use_inband_status);
561 -
562 - if (netif_running(dev)) {
563 - mvneta_port_down(pp);
564 - mvneta_port_up(pp);
565 - }
566 - }
567 -
568 - return phy_ethtool_sset(pp->phy_dev, cmd);
569 + return phylink_ethtool_set_settings(pp->phylink, cmd);
570 }
571
572 /* Set interrupt coalescing for ethtools */
573 @@ -3673,7 +3694,8 @@ static void mvneta_ethtool_update_stats(
574 {
575 const struct mvneta_statistic *s;
576 void __iomem *base = pp->base;
577 - u32 high, low, val;
578 + u32 high, low;
579 + u64 val;
580 u64 val64;
581 int i;
582
583 @@ -3968,14 +3990,13 @@ static int mvneta_probe(struct platform_
584 const struct mbus_dram_target_info *dram_target_info;
585 struct resource *res;
586 struct device_node *dn = pdev->dev.of_node;
587 - struct device_node *phy_node;
588 struct device_node *bm_node;
589 struct mvneta_port *pp;
590 struct net_device *dev;
591 + struct phylink *phylink;
592 const char *dt_mac_addr;
593 char hw_mac_addr[ETH_ALEN];
594 const char *mac_from;
595 - const char *managed;
596 int tx_csum_limit;
597 int phy_mode;
598 int err;
599 @@ -3991,31 +4012,11 @@ static int mvneta_probe(struct platform_
600 goto err_free_netdev;
601 }
602
603 - phy_node = of_parse_phandle(dn, "phy", 0);
604 - if (!phy_node) {
605 - if (!of_phy_is_fixed_link(dn)) {
606 - dev_err(&pdev->dev, "no PHY specified\n");
607 - err = -ENODEV;
608 - goto err_free_irq;
609 - }
610 -
611 - err = of_phy_register_fixed_link(dn);
612 - if (err < 0) {
613 - dev_err(&pdev->dev, "cannot register fixed PHY\n");
614 - goto err_free_irq;
615 - }
616 -
617 - /* In the case of a fixed PHY, the DT node associated
618 - * to the PHY is the Ethernet MAC DT node.
619 - */
620 - phy_node = of_node_get(dn);
621 - }
622 -
623 phy_mode = of_get_phy_mode(dn);
624 if (phy_mode < 0) {
625 dev_err(&pdev->dev, "incorrect phy-mode\n");
626 err = -EINVAL;
627 - goto err_put_phy_node;
628 + goto err_free_irq;
629 }
630
631 dev->tx_queue_len = MVNETA_MAX_TXD;
632 @@ -4026,12 +4027,7 @@ static int mvneta_probe(struct platform_
633
634 pp = netdev_priv(dev);
635 spin_lock_init(&pp->lock);
636 - pp->phy_node = phy_node;
637 - pp->phy_interface = phy_mode;
638 -
639 - err = of_property_read_string(dn, "managed", &managed);
640 - pp->use_inband_status = (err == 0 &&
641 - strcmp(managed, "in-band-status") == 0);
642 + pp->dn = dn;
643 pp->cpu_notifier.notifier_call = mvneta_percpu_notifier;
644
645 pp->rxq_def = rxq_def;
646 @@ -4041,7 +4037,7 @@ static int mvneta_probe(struct platform_
647 pp->clk = devm_clk_get(&pdev->dev, NULL);
648 if (IS_ERR(pp->clk)) {
649 err = PTR_ERR(pp->clk);
650 - goto err_put_phy_node;
651 + goto err_free_irq;
652 }
653
654 clk_prepare_enable(pp->clk);
655 @@ -4144,6 +4140,14 @@ static int mvneta_probe(struct platform_
656 dev->priv_flags |= IFF_UNICAST_FLT | IFF_LIVE_ADDR_CHANGE;
657 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
658
659 + phylink = phylink_create(dev, dn, phy_mode, &mvneta_phylink_ops);
660 + if (IS_ERR(phylink)) {
661 + err = PTR_ERR(phylink);
662 + goto err_free_stats;
663 + }
664 +
665 + pp->phylink = phylink;
666 +
667 err = register_netdev(dev);
668 if (err < 0) {
669 dev_err(&pdev->dev, "failed to register\n");
670 @@ -4155,13 +4159,6 @@ static int mvneta_probe(struct platform_
671
672 platform_set_drvdata(pdev, pp->dev);
673
674 - if (pp->use_inband_status) {
675 - struct phy_device *phy = of_phy_find_device(dn);
676 -
677 - mvneta_fixed_link_update(pp, phy);
678 -
679 - put_device(&phy->dev);
680 - }
681
682 return 0;
683
684 @@ -4173,13 +4170,13 @@ err_netdev:
685 1 << pp->id);
686 }
687 err_free_stats:
688 + if (pp->phylink)
689 + phylink_destroy(pp->phylink);
690 free_percpu(pp->stats);
691 err_free_ports:
692 free_percpu(pp->ports);
693 err_clk:
694 clk_disable_unprepare(pp->clk);
695 -err_put_phy_node:
696 - of_node_put(phy_node);
697 err_free_irq:
698 irq_dispose_mapping(dev->irq);
699 err_free_netdev:
700 @@ -4198,7 +4195,7 @@ static int mvneta_remove(struct platform
701 free_percpu(pp->ports);
702 free_percpu(pp->stats);
703 irq_dispose_mapping(dev->irq);
704 - of_node_put(pp->phy_node);
705 + phylink_destroy(pp->phylink);
706 free_netdev(dev);
707
708 if (pp->bm_priv) {