mvebu: add ClearFog Base device tree files
[openwrt/openwrt.git] / target / linux / mvebu / patches-4.9 / 472-armada-solidrun-microsom-backport-improvements.patch
1 From fc5783a00be9251196091be6b9cdd54fe196630b Mon Sep 17 00:00:00 2001
2 From: Marko Ratkaj <marko.ratkaj@sartura.hr>
3 Date: Fri, 7 Apr 2017 11:24:19 +0200
4 Subject: [PATCH] armada-38x-solidrun-microsom backport improvements from
5 upstream
6
7 Signed-off-by: Marko Ratkaj <marko.ratkaj@sartura.hr>
8 ---
9 .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 130 ++++++++++++---------
10 1 file changed, 74 insertions(+), 56 deletions(-)
11
12 --- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
13 +++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
14 @@ -17,17 +17,17 @@
15 * modify it under the terms of the GNU General Public License
16 * version 2 as published by the Free Software Foundation.
17 *
18 - * This file is distributed in the hope that it will be useful
19 + * This file is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 - * Or, alternatively
25 + * Or, alternatively,
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 - * restriction, including without limitation the rights to use
31 + * restriction, including without limitation the rights to use,
32 * copy, modify, merge, publish, distribute, sublicense, and/or
33 * sell copies of the Software, and to permit persons to whom the
34 * Software is furnished to do so, subject to the following
35 @@ -36,11 +36,11 @@
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
44 - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
45 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
47 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
48 * OTHER DEALINGS IN THE SOFTWARE.
49 @@ -62,45 +62,6 @@
50 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
51
52 internal-regs {
53 - ethernet@70000 {
54 - pinctrl-0 = <&ge0_rgmii_pins>;
55 - pinctrl-names = "default";
56 - phy = <&phy_dedicated>;
57 - phy-mode = "rgmii-id";
58 - buffer-manager = <&bm>;
59 - bm,pool-long = <0>;
60 - bm,pool-short = <1>;
61 - status = "okay";
62 - };
63 -
64 - mdio@72004 {
65 - /*
66 - * Add the phy clock here, so the phy can be
67 - * accessed to read its IDs prior to binding
68 - * with the driver.
69 - */
70 - pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
71 - pinctrl-names = "default";
72 -
73 - phy_dedicated: ethernet-phy@0 {
74 - /*
75 - * Annoyingly, the marvell phy driver
76 - * configures the LED register, rather
77 - * than preserving reset-loaded setting.
78 - * We undo that rubbish here.
79 - */
80 - marvell,reg-init = <3 16 0 0x101e>;
81 - reg = <0>;
82 - };
83 - };
84 -
85 - pinctrl@18000 {
86 - microsom_phy_clk_pins: microsom-phy-clk-pins {
87 - marvell,pins = "mpp45";
88 - marvell,function = "ref";
89 - };
90 - };
91 -
92 rtc@a3800 {
93 /*
94 * If the rtc doesn't work, run "date reset"
95 @@ -108,21 +69,78 @@
96 */
97 status = "okay";
98 };
99 + };
100 + };
101 +};
102
103 - serial@12000 {
104 - pinctrl-0 = <&uart0_pins>;
105 - pinctrl-names = "default";
106 - status = "okay";
107 - };
108 +&bm {
109 + status = "okay";
110 +};
111
112 - bm@c8000 {
113 - status = "okay";
114 - };
115 - };
116 +&bm_bppi {
117 + status = "okay";
118 +};
119
120 - bm-bppi {
121 - status = "okay";
122 - };
123 +&eth0 {
124 + /* ethernet@70000 */
125 + pinctrl-0 = <&ge0_rgmii_pins>;
126 + pinctrl-names = "default";
127 + phy = <&phy_dedicated>;
128 + phy-mode = "rgmii-id";
129 + buffer-manager = <&bm>;
130 + bm,pool-long = <0>;
131 + bm,pool-short = <1>;
132 + status = "okay";
133 +};
134
135 +&mdio {
136 + /*
137 + * Add the phy clock here, so the phy can be accessed to read its
138 + * IDs prior to binding with the driver.
139 + */
140 + pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
141 + pinctrl-names = "default";
142 +
143 + phy_dedicated: ethernet-phy@0 {
144 + /*
145 + * Annoyingly, the marvell phy driver configures the LED
146 + * register, rather than preserving reset-loaded setting.
147 + * We undo that rubbish here.
148 + */
149 + marvell,reg-init = <3 16 0 0x101e>;
150 + reg = <0>;
151 };
152 };
153 +
154 +&pinctrl {
155 + microsom_phy_clk_pins: microsom-phy-clk-pins {
156 + marvell,pins = "mpp45";
157 + marvell,function = "ref";
158 + };
159 + /* Optional eMMC */
160 + microsom_sdhci_pins: microsom-sdhci-pins {
161 + marvell,pins = "mpp21", "mpp28", "mpp37",
162 + "mpp38", "mpp39", "mpp40";
163 + marvell,function = "sd0";
164 + };
165 +};
166 +
167 +&spi1 {
168 + /* The microsom has an optional W25Q32 on board, connected to CS0 */
169 + pinctrl-0 = <&spi1_pins>;
170 +
171 + w25q32: spi-flash@0 {
172 + #address-cells = <1>;
173 + #size-cells = <1>;
174 + compatible = "w25q32", "jedec,spi-nor";
175 + reg = <0>; /* Chip select 0 */
176 + spi-max-frequency = <3000000>;
177 + status = "disabled";
178 + };
179 +};
180 +
181 +&uart0 {
182 + pinctrl-0 = <&uart0_pins>;
183 + pinctrl-names = "default";
184 + status = "okay";
185 +};