target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch

   1 From 715878016984b2617f6c1f177c50039e12e7bd5b Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
   3 Date: Thu, 30 Apr 2020 10:06:23 +0200
   4 Subject: [PATCH] arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio
   5  function
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   8 Content-Transfer-Encoding: 8bit
   9
  10 We found out that we are unable to control the PERST# signal via the
  11 default pin dedicated to be PERST# pin (GPIO2[3] pin) on A3700 SOC when
  12 this pin is in EP_PCIE1_Resetn mode. There is a register in the PCIe
  13 register space called PERSTN_GPIO_EN (D0088004[3]), but changing the
  14 value of this register does not change the pin output when measuring
  15 with voltmeter.
  16
  17 We do not know if this is a bug in the SOC, or if it works only when
  18 PCIe controller is in a certain state.
  19
  20 Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready
  21 before training link") says that when this pin changes pinctrl mode
  22 from EP_PCIE1_Resetn to GPIO, the PERST# signal is asserted for a brief
  23 moment.
  24
  25 So currently the situation is that on A3700 boards the PERST# signal is
  26 asserted in U-Boot (because the code in U-Boot issues reset via this pin
  27 via GPIO mode), and then in Linux by the obscure and undocumented
  28 mechanism described by the above mentioned commit.
  29
  30 We want to issue PERST# signal in a known way, therefore this patch
  31 changes the pcie_reset_pin function from "pcie" to "gpio" and adds the
  32 reset-gpios property to the PCIe node in device tree files of
  33 EspressoBin and Armada 3720 Dev Board (Turris Mox device tree already
  34 has this property and uDPU does not have a PCIe port).
  35
  36 Signed-off-by: Marek Behún <marek.behun@nic.cz>
  37 Cc: Remi Pommarel <repk@triplefau.lt>
  38 Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
  39 Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  40 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
  41 ---
  42  arch/arm64/boot/dts/marvell/armada-3720-db.dts           | 3 +++
  43  arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 1 +
  44  arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts   | 4 ----
  45  arch/arm64/boot/dts/marvell/armada-37xx.dtsi             | 2 +-
  46  4 files changed, 5 insertions(+), 5 deletions(-)
  47
  48 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
  49 +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
  50 @@ -128,6 +128,9 @@
  51
  52  /* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
  53  &pcie0 {
  54 +       pinctrl-names = "default";
  55 +       pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
  56 +       reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
  57         status = "okay";
  58  };
  59
  60 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
  61 +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
  62 @@ -59,6 +59,7 @@
  63         phys = <&comphy1 0>;
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
  66 +       reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
  67  };
  68
  69  /* J6 */
  70 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
  71 +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
  72 @@ -120,10 +120,6 @@
  73         };
  74  };
  75
  76 -&pcie_reset_pins {
  77 -       function = "gpio";
  78 -};
  79 -
  80  &pcie0 {
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
  83 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
  84 +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
  85 @@ -317,7 +317,7 @@
  86
  87                                 pcie_reset_pins: pcie-reset-pins {
  88                                         groups = "pcie1";
  89 -                                       function = "pcie";
  90 +                                       function = "gpio";
  91                                 };
  92
  93                                 pcie_clkreq_pins: pcie-clkreq-pins {