target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch

   1 From 1b5a2dd9e266d78d5fddd7e6b116e47ba9577b5e Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Thu, 30 Apr 2020 10:06:25 +0200
   4 Subject: [PATCH] arm64: dts: marvell: armada-37xx: Move PCIe max-link-speed
   5  property
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Move the max-link-speed property of the PCIe node from board specific
  11 device tree files to the generic armada-37xx.dtsi.
  12
  13 Armada 37xx supports only PCIe gen2 speed so max-link-speed property
  14 should be in the generic armada-37xx.dtsi file.
  15
  16 Signed-off-by: Pali Rohár <pali@kernel.org>
  17 Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
  18 Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  19 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
  20 ---
  21  arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 1 -
  22  arch/arm64/boot/dts/marvell/armada-37xx.dtsi           | 1 +
  23  2 files changed, 1 insertion(+), 1 deletion(-)
  24
  25 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
  26 +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
  27 @@ -124,7 +124,6 @@
  28         pinctrl-names = "default";
  29         pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
  30         status = "okay";
  31 -       max-link-speed = <2>;
  32         reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
  33
  34         /* enabled by U-Boot if PCIe module is present */
  35 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
  36 +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
  37 @@ -494,6 +494,7 @@
  38                                         <0 0 0 2 &pcie_intc 1>,
  39                                         <0 0 0 3 &pcie_intc 2>,
  40                                         <0 0 0 4 &pcie_intc 3>;
  41 +                       max-link-speed = <2>;
  42                         phys = <&comphy1 0>;
  43                         pcie_intc: interrupt-controller {
  44                                 interrupt-controller;