kernel: bump 4.14 to 4.14.20
[openwrt/openwrt.git] / target / linux / octeontx / patches-4.14 / 0001-net-thunderx-workaround-BGX-TX-Underflow-issue.patch
1 From b1e7791e688620c9bb8476ac2d0bc99abeb7f825 Mon Sep 17 00:00:00 2001
2 From: Tim Harvey <tharvey@gateworks.com>
3 Date: Fri, 29 Dec 2017 16:48:04 -0800
4 Subject: [PATCH] net: thunderx: workaround BGX TX Underflow issue
5
6 While it is not yet understood why a TX underflow can easily occur
7 for SGMII interfaces resulting in a TX wedge. It has been found that
8 disabling/re-enabling the LMAC resolves the issue.
9
10 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
11 ---
12 drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 54 +++++++++++++++++++++++
13 drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 9 ++++
14 2 files changed, 63 insertions(+)
15
16 --- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
17 +++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c
18 @@ -1344,6 +1344,54 @@ static int bgx_init_phy(struct bgx *bgx)
19 return bgx_init_of_phy(bgx);
20 }
21
22 +static irqreturn_t bgx_intr_handler(int irq, void *data)
23 +{
24 + struct bgx *bgx = (struct bgx *)data;
25 + struct device *dev = &bgx->pdev->dev;
26 + u64 status, val;
27 + int lmac;
28 +
29 + for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
30 + status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT);
31 + if (status & GMI_TXX_INT_UNDFLW) {
32 + dev_err(dev, "BGX%d lmac%d UNDFLW\n", bgx->bgx_id,
33 + lmac);
34 + val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG);
35 + val &= ~CMR_EN;
36 + bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
37 + val |= CMR_EN;
38 + bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val);
39 + }
40 + /* clear interrupts */
41 + bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status);
42 + }
43 +
44 + return IRQ_HANDLED;
45 +}
46 +
47 +static int bgx_register_intr(struct pci_dev *pdev)
48 +{
49 + struct bgx *bgx = pci_get_drvdata(pdev);
50 + struct device *dev = &pdev->dev;
51 + int num_vec, ret;
52 + char irq_name[32];
53 +
54 + /* Enable MSI-X */
55 + num_vec = pci_msix_vec_count(pdev);
56 + ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSIX);
57 + if (ret < 0) {
58 + dev_err(dev, "Req for #%d msix vectors failed\n", num_vec);
59 + return 1;
60 + }
61 + sprintf(irq_name, "BGX%d", bgx->bgx_id);
62 + ret = request_irq(pci_irq_vector(pdev, GMPX_GMI_TX_INT),
63 + bgx_intr_handler, 0, irq_name, bgx);
64 + if (ret)
65 + return 1;
66 +
67 + return 0;
68 +}
69 +
70 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
71 {
72 int err;
73 @@ -1414,6 +1462,8 @@ static int bgx_probe(struct pci_dev *pde
74 xcv_init_hw(bgx->phy_mode);
75 bgx_init_hw(bgx);
76
77 + bgx_register_intr(pdev);
78 +
79 /* Enable all LMACs */
80 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
81 err = bgx_lmac_enable(bgx, lmac);
82 @@ -1424,6 +1474,10 @@ static int bgx_probe(struct pci_dev *pde
83 bgx_lmac_disable(bgx, --lmac);
84 goto err_enable;
85 }
86 +
87 + /* enable TX FIFO Underflow interrupt */
88 + bgx_reg_modify(bgx, lmac, BGX_GMP_GMI_TXX_INT_ENA_W1S,
89 + GMI_TXX_INT_UNDFLW);
90 }
91
92 return 0;
93 --- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
94 +++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h
95 @@ -179,6 +179,15 @@
96 #define BGX_GMP_GMI_TXX_BURST 0x38228
97 #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240
98 #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300
99 +#define BGX_GMP_GMI_TXX_INT 0x38500
100 +#define BGX_GMP_GMI_TXX_INT_W1S 0x38508
101 +#define BGX_GMP_GMI_TXX_INT_ENA_W1C 0x38510
102 +#define BGX_GMP_GMI_TXX_INT_ENA_W1S 0x38518
103 +#define GMI_TXX_INT_PTP_LOST BIT_ULL(4)
104 +#define GMI_TXX_INT_LATE_COL BIT_ULL(3)
105 +#define GMI_TXX_INT_XSDEF BIT_ULL(2)
106 +#define GMI_TXX_INT_XSCOL BIT_ULL(1)
107 +#define GMI_TXX_INT_UNDFLW BIT_ULL(0)
108
109 #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */
110 #define BGX_MSIX_VEC_0_29_CTL 0x400008