3e1d9f38b42aa1f91048ffb86b7db9f23eef4351
[openwrt/openwrt.git] / target / linux / oxnas / files / arch / arm / boot / dts / ox820.dtsi
1 /*
2 * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 /include/ "skeleton.dtsi"
10
11 / {
12 compatible = "plxtech,nas7820", "plxtech,nas782x";
13 interrupt-parent = <&gic>;
14
15 aliases {
16 serial0 = &uart0;
17 /* alias to determine bank index */
18 gpio0 = &GPIOA;
19 gpio1 = &GPIOB;
20
21 ethernet0 = &gmac;
22 };
23
24 cpus {
25 cpu@0 {
26 compatible = "arm,arm11mpcore";
27 };
28 cpu@1 {
29 compatible = "arm,arm11mpcore";
30 };
31 };
32
33 gic: gic@47001000 {
34 compatible = "arm,arm11mp-gic";
35 interrupt-controller;
36 #interrupt-cells = <3>;
37 reg = <0x47001000 0x1000>,
38 <0x47000100 0x0100>;
39 };
40
41 rst: reset-controller@44E00034 {
42 compatible = "plxtech,nas782x-reset";
43 #reset-cells = <1>;
44 reg = <0x44E00034 0x8>; /* currently not used */
45 };
46
47 rps: rps@44400000 {
48 compatible = "plxtech,nas782x-rps";
49 interrupt-controller;
50 #interrupt-cells = <1>;
51 reg = <0x44400000 0x14>;
52 interrupts = <0 5 0x304>;
53 };
54
55 /* external oscillator */
56 osc: oscillator {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <25000000>;
60 };
61
62 sysclk: sysclk {
63 compatible = "fixed-factor-clock";
64 #clock-cells = <0>;
65 clock-div = <4>;
66 clock-mult = <1>;
67 clocks = <&osc>;
68 };
69
70 plla: plla@44e001f0 {
71 compatible = "plxtech,nas782x-plla";
72 #clock-cells = <0>;
73 clocks = <&osc>;
74 reg = <0x44e001f0 0x10>;
75 };
76
77 pllb: pllb@44f001f0 {
78 compatible = "plxtech,nas782x-pllb";
79 #clock-cells = <0>;
80 clocks = <&osc>;
81 reg = <0x44f001f0 0x10>;
82 resets = <&rst 31>;
83 };
84
85 stdclk: stdclk {
86 compatible = "plxtech,nas782x-stdclk";
87 #clock-cells = <1>;
88 clocks = <&osc>;
89 };
90
91 twdclk: twdclk {
92 compatible = "fixed-factor-clock";
93 #clock-cells = <0>;
94 clock-div = <2>;
95 clock-mult = <1>;
96 clocks = <&plla>;
97 };
98
99 gmacclk: gmacclk {
100 compatible = "fixed-clock";
101 #clock-cells = <0>;
102 clock-frequency = <125000000>;
103 };
104
105 pinctrl {
106 /* act as a simple bus, so children will be probed automatically */
107 #address-cells = <1>;
108 #size-cells = <1>;
109 compatible = "plxtech,nas782x-pinctrl", "simple-bus";
110 ranges;
111
112 plxtech,mux-mask = <
113 0xFFFFFFFF 0xCC0FFDF9 0xFC000E60 0x0F03F7E0 0xF00C0FE0
114 0x0003FFFF 0x00037FFF 0x0003FFF8 0x00000F00 0x0003F7F3
115 >;
116
117 GPIOA: gpio@44000000 {
118 compatible = "plxtech,nas782x-gpio";
119 reg = <0x44000000 0x100>, <0x44E00000 0x200>;
120 interrupts = <0 21 0x304>;
121 #gpio-cells = <2>;
122 gpio-controller;
123 interrupt-controller;
124 #interrupt-cells = <2>;
125 #gpio-lines = <32>; /* real gpio pin count */
126 };
127
128 GPIOB: gpio@44100000 {
129 compatible = "plxtech,nas782x-gpio";
130 reg = <0x44100000 0x100>, <0x44F00000 0x200>;
131 interrupts = <0 22 0x304>;
132 #gpio-cells = <2>;
133 gpio-controller;
134 interrupt-controller;
135 #interrupt-cells = <2>;
136 #gpio-lines = <18>; /* real gpio pin count */
137 };
138
139 uart0 {
140 pinctrl_uart0: uart0-0 {
141 plxtech,pins =
142 <0 30 5 0 /* MF_A30 PINMUX_ALT PINMUX_UARTA_SIN */
143 0 31 5 0>; /* MF_A31 PINMUX_ALT PINMUX_UARTA_SOUT */
144 };
145 };
146
147 gmac0 {
148 pinctrl_gmac0: gmac0-0 {
149 plxtech,pins =
150 <0 3 1 0 /* MF_A3 PINMUX_2 PINMUX_MACA_MDC */
151 0 4 1 0>; /* MF_A4 PINMUX_2 PINMUX_MACA_MDIO */
152 };
153 };
154
155 nand0 {
156 pinctrl_nand0: nand0-0 {
157 plxtech,pins =
158 <0 12 1 0 /* MF_A12 PINMUX_2 PINMUX_STATIC_DATA0 */
159 0 13 1 0 /* MF_A13 PINMUX_2 PINMUX_STATIC_DATA1 */
160 0 14 1 0 /* MF_A14 PINMUX_2 PINMUX_STATIC_DATA2 */
161 0 15 1 0 /* MF_A15 PINMUX_2 PINMUX_STATIC_DATA3 */
162 0 16 1 0 /* MF_A16 PINMUX_2 PINMUX_STATIC_DATA4 */
163 0 17 1 0 /* MF_A17 PINMUX_2 PINMUX_STATIC_DATA5 */
164 0 18 1 0 /* MF_A18 PINMUX_2 PINMUX_STATIC_DATA6 */
165 0 19 1 0 /* MF_A19 PINMUX_2 PINMUX_STATIC_DATA7 */
166
167 0 20 1 0 /* MF_A20 PINMUX_2 PINMUX_STATIC_NWE */
168 0 21 1 0 /* MF_A21 PINMUX_2 PINMUX_STATIC_NOE */
169 0 22 1 0 /* MF_A22 PINMUX_2 PINMUX_STATIC_NCS */
170 0 23 1 0 /* MF_A23 PINMUX_2 PINMUX_STATIC_ADDR18 */
171 0 24 1 0>; /* MF_A24 PINMUX_2 PINMUX_STATIC_ADDR19 */
172 };
173 };
174 };
175
176 pcie-controller@47C00000 {
177 compatible = "plxtech,nas782x-pcie";
178 device_type = "pci";
179 #address-cells = <3>;
180 #size-cells = <2>;
181
182 /* flag & space bus address host address size */
183 ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
184 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
185 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
186 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
187
188 bus-range = <0x00 0x7f>;
189
190 /* cfg inbound translator phy*/
191 reg = <0x47C00000 0x1000>, <0x47D00000 0x100>, <0x44A00000 0x10>;
192
193 #interrupt-cells = <1>;
194 /* wild card mask, match all bus address & interrupt specifier */
195 /* format: bus address mask, interrupt specifier mask */
196 /* each bit 1 means need match, 0 means ignored when match */
197 interrupt-map-mask = <0 0 0 0>;
198 /* format: a list of: bus address, interrupt specifier,
199 * parent interrupt controller & specifier */
200 interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
201
202 gpios = <&GPIOB 12 0>;
203 clocks = <&stdclk 8>, <&pllb>;
204 clock-names = "pcie", "busclk";
205 resets = <&rst 7>, <&rst 14>;
206 reset-names = "pcie", "phy";
207
208 plxtech,pcie-hcsl-bit = <2>;
209 plxtech,pcie-ctrl-offset = <0x120>;
210 plxtech,pcie-outbound-offset = <0x138>;
211 status = "disabled";
212 };
213
214 pcie-controller@47E00000 {
215 compatible = "plxtech,nas782x-pcie";
216 device_type = "pci";
217 #address-cells = <3>;
218 #size-cells = <2>;
219
220 /* flag & space bus address host address size */
221 ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
222 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
223 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
224 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
225
226 bus-range = <0x80 0xff>;
227
228 /* cfg inbound translator phy*/
229 reg = <0x47E00000 0x1000>, <0x47F00000 0x100>, <0x44A00000 0x10>;
230
231 #interrupt-cells = <1>;
232 /* wild card mask, match all bus address & interrupt specifier */
233 /* format: bus address mask, interrupt specifier mask */
234 /* each bit 1 means need match, 0 means ignored when match */
235 interrupt-map-mask = <0 0 0 0>;
236 /* format: a list of: bus address, interrupt specifier,
237 * parent interrupt controller & specifier */
238 interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
239
240 /* gpios = <&GPIOB 12 0>; */
241 clocks = <&stdclk 11>, <&pllb>;
242 clock-names = "pcie", "busclk";
243 resets = <&rst 23>, <&rst 14>;
244 reset-names = "pcie", "phy";
245
246 plxtech,pcie-hcsl-bit = <3>;
247 plxtech,pcie-ctrl-offset = <0x124>;
248 plxtech,pcie-outbound-offset = <0x174>;
249 status = "disabled";
250 };
251
252 local-timer@47000600 {
253 compatible = "arm,arm11mp-twd-timer";
254 reg = <0x47000600 0x20>;
255 interrupts = <1 13 0x304>; /* percpu, irq 29, cpu mask 3, level high */
256 clocks = <&twdclk>;
257 };
258
259 watchdog@47000620 {
260 compatible = "mpcore_wdt";
261 reg = <0x47000620 0x20>;
262 interrupts = <1 14 0x304>; /* percpu, irq 30, cpu mask 3, level high */
263 clocks = <&twdclk>;
264 };
265
266 timer@44400200 {
267 compatible = "plxtech,nas782x-rps-timer";
268 reg = <0x44400200 0x40>;
269 clocks = <&sysclk>;
270 };
271
272 uart0: uart@44200000 {
273 compatible = "ns16550a";
274 reg = <0x44200000 0x100>;
275 clock-frequency = <6250000>;
276 interrupts = <0 23 0x304>;
277 reg-shift = <0>;
278 fifo-size = <16>;
279 reg-io-width = <1>;
280 current-speed = <115200>;
281 no-loopback-test;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_uart0>;
284 status = "disabled";
285 };
286
287 sata@45900000 {
288 compatible = "plxtech,nas782x-sata";
289 /* ports dmactl sgdma */
290 reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
291 /* core phy descriptors (optional) */
292 <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
293 interrupts = <0 18 0x304>;
294 clocks = <&stdclk 4>;
295 resets = <&rst 11>, <&rst 12>, <&rst 13>;
296 reset-names = "sata", "link", "phy";
297 nr-ports = <1>;
298 status = "disabled";
299 };
300
301 nand@41000000 {
302 compatible = "plxtech,nand-nas782x", "gen_nand";
303 reg = <0x41000000 0x100000>, <0x41C00000 0x20>;
304 nand-ecc-mode = "soft";
305 clocks = <&stdclk 9>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_nand0>;
308 resets = <&rst 15>;
309 #address-cells = <1>;
310 #size-cells = <1>;
311 status = "disabled";
312 };
313
314 gmac: ethernet@40400000 {
315 compatible = "plxtech,nas782x-gmac", "snps,dwmac";
316 reg = <0x40400000 0x2000>;
317 interrupts = <0 8 0x304>, <0 17 0x304>;
318 interrupt-names = "macirq", "eth_wake_irq";
319 mac-address = [000000000000]; /* Filled in by U-Boot */
320 phy-mode = "rgmii";
321 clocks = <&stdclk 7>, <&gmacclk>;
322 clock-names = "gmac", "stmmaceth";
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_gmac0>;
325 resets = <&rst 6>;
326 status = "disabled";
327 };
328
329 ehci@40200100 {
330 compatible = "plxtech,nas782x-ehci";
331 reg = <0x40200100 0xf00>;
332 interrupts = <0 7 0x304>;
333 clocks = <&stdclk 6>, <&pllb>, <&stdclk 12>;
334 clock-names = "usb", "refsrc", "phyref";
335 resets = <&rst 4>, <&rst 5>, <&rst 26>;
336 reset-names = "host", "phya", "phyb";
337 /* Otherwise ref300 is used, which is derived from sata phy
338 * in that case, usb depends on sata initialization */
339 /* FIXME: how to make this dependency explicit ? */
340 plxtech,ehci_use_pllb;
341 status = "disabled";
342 };
343 };