kernel: bump 4.14 to 4.14.50 for 18.06
[openwrt/openwrt.git] / target / linux / oxnas / files / arch / arm / mach-oxnas / include / mach / hardware.h
1 /*
2 * arch/arm/mach-0x820/include/mach/hardware.h
3 *
4 * Copyright (C) 2009 Oxford Semiconductor Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #ifndef __ASM_ARCH_HARDWARE_H
12 #define __ASM_ARCH_HARDWARE_H
13
14 #include <linux/io.h>
15 #include <mach/iomap.h>
16
17 /*
18 * Location of flags and vectors in SRAM for controlling the booting of the
19 * secondary ARM11 processors.
20 */
21
22 #define OXNAS_SCU_BASE_VA OXNAS_PERCPU_BASE_VA
23 #define OXNAS_GICN_BASE_VA(n) (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100)
24
25 #define HOLDINGPEN_CPU IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
26 #define HOLDINGPEN_LOCATION IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
27
28 /**
29 * System block reset and clock control
30 */
31 #define SYS_CTRL_PCI_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20)
32 #define SYSCTRL_CLK_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24)
33 #define SYS_CTRL_CLK_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C)
34 #define SYS_CTRL_CLK_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30)
35 #define SYS_CTRL_RST_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34)
36 #define SYS_CTRL_RST_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38)
37
38 #define SYS_CTRL_PLLSYS_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48)
39 #define SYS_CTRL_CLK_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64)
40 #define SYS_CTRL_PLLSYS_KEY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C)
41 #define SYS_CTRL_GMAC_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78)
42 #define SYS_CTRL_GMAC_DELAY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100)
43
44 /* Scratch registers */
45 #define SYS_CTRL_SCRATCHWORD0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
46 #define SYS_CTRL_SCRATCHWORD1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
47 #define SYS_CTRL_SCRATCHWORD2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc)
48 #define SYS_CTRL_SCRATCHWORD3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0)
49
50 #define SYS_CTRL_PLLA_CTRL0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0)
51 #define SYS_CTRL_PLLA_CTRL1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4)
52 #define SYS_CTRL_PLLA_CTRL2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8)
53 #define SYS_CTRL_PLLA_CTRL3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC)
54
55 #define SYS_CTRL_USBHSMPH_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40)
56 #define SYS_CTRL_USBHSMPH_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44)
57 #define SYS_CTRL_REF300_DIV IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8)
58 #define SYS_CTRL_USBHSPHY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84)
59 #define SYS_CTRL_USB_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90)
60
61 /* pcie */
62 #define SYS_CTRL_HCSL_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114)
63
64 /* System control multi-function pin function selection */
65 #define SYS_CTRL_SECONDARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14)
66 #define SYS_CTRL_TERTIARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c)
67 #define SYS_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94)
68 #define SYS_CTRL_DEBUG_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c)
69 #define SYS_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4)
70 #define SYS_CTRL_PULLUP_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac)
71
72 /* Secure control multi-function pin function selection */
73 #define SEC_CTRL_SECONDARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14)
74 #define SEC_CTRL_TERTIARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c)
75 #define SEC_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94)
76 #define SEC_CTRL_DEBUG_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c)
77 #define SEC_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4)
78 #define SEC_CTRL_PULLUP_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac)
79
80 #define SEC_CTRL_COPRO_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68)
81 #define SEC_CTRL_SECURE_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98)
82 #define SEC_CTRL_LEON_DEBUG IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0)
83 #define SEC_CTRL_PLLB_DIV_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8)
84 #define SEC_CTRL_PLLB_CTRL0 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0)
85 #define SEC_CTRL_PLLB_CTRL1 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
86 #define SEC_CTRL_PLLB_CTRL8 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
87
88 #define RPSA_IRQ_SOFT IOMEM(OXNAS_RPSA_BASE_VA + 0x10)
89 #define RPSA_FIQ_ENABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x108)
90 #define RPSA_FIQ_DISABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x10C)
91 #define RPSA_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC)
92
93 #define RPSC_IRQ_SOFT IOMEM(OXNAS_RPSC_BASE_VA + 0x10)
94 #define RPSC_FIQ_ENABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x108)
95 #define RPSC_FIQ_DISABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x10C)
96 #define RPSC_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC)
97
98 #define RPSA_TIMER2_VAL IOMEM(OXNAS_RPSA_BASE_VA + 0x224)
99
100 #define REF300_DIV_INT_SHIFT 8
101 #define REF300_DIV_FRAC_SHIFT 0
102 #define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
103 #define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
104
105 #define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
106 #define USBHSPHY_SUSPENDM_MANUAL_STATE 15
107 #define USBHSPHY_ATE_ESET 14
108 #define USBHSPHY_TEST_DIN 6
109 #define USBHSPHY_TEST_ADD 2
110 #define USBHSPHY_TEST_DOUT_SEL 1
111 #define USBHSPHY_TEST_CLK 0
112
113 #define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
114 #define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
115 #define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
116 #define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
117
118 #define USBAMUX_DEVICE BIT(4)
119
120 #define USBPHY_REFCLKDIV_SHIFT 2
121 #define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
122 #define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
123 #define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
124
125 #define USB_CTRL_USB_CKO_SEL_BIT 0
126
127 #define USB_INT_CLK_XTAL 0
128 #define USB_INT_CLK_REF300 2
129 #define USB_INT_CLK_PLLB 3
130
131 #define SYS_CTRL_GMAC_CKEN_RX_IN 14
132 #define SYS_CTRL_GMAC_CKEN_RXN_OUT 13
133 #define SYS_CTRL_GMAC_CKEN_RX_OUT 12
134 #define SYS_CTRL_GMAC_CKEN_TX_IN 10
135 #define SYS_CTRL_GMAC_CKEN_TXN_OUT 9
136 #define SYS_CTRL_GMAC_CKEN_TX_OUT 8
137 #define SYS_CTRL_GMAC_RX_SOURCE 7
138 #define SYS_CTRL_GMAC_TX_SOURCE 6
139 #define SYS_CTRL_GMAC_LOW_TX_SOURCE 4
140 #define SYS_CTRL_GMAC_AUTO_TX_SOURCE 3
141 #define SYS_CTRL_GMAC_RGMII 2
142 #define SYS_CTRL_GMAC_SIMPLE_MUX 1
143 #define SYS_CTRL_GMAC_CKEN_GTX 0
144 #define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT 0
145 #define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT 8
146 #define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT 16
147 #define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT 24
148 #define SYS_CTRL_GMAC_TX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TX_VARDELAY_SHIFT)
149 #define SYS_CTRL_GMAC_TXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT)
150 #define SYS_CTRL_GMAC_RX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RX_VARDELAY_SHIFT)
151 #define SYS_CTRL_GMAC_RXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT)
152
153 #define PLLB_BYPASS 1
154 #define PLLB_ENSAT 3
155 #define PLLB_OUTDIV 4
156 #define PLLB_REFDIV 8
157 #define PLLB_DIV_INT_SHIFT 8
158 #define PLLB_DIV_FRAC_SHIFT 0
159 #define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
160 #define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
161
162 #define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0
163 #define SYS_CTRL_CKCTRL_SLOW_BIT 8
164
165 #define SYS_CTRL_UART2_DEQ_EN 0
166 #define SYS_CTRL_UART3_DEQ_EN 1
167 #define SYS_CTRL_UART3_IQ_EN 2
168 #define SYS_CTRL_UART4_IQ_EN 3
169 #define SYS_CTRL_UART4_NOT_PCI_MODE 4
170
171 #define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT 11
172
173 #define PLLA_REFDIV_MASK 0x3F
174 #define PLLA_REFDIV_SHIFT 8
175 #define PLLA_OUTDIV_MASK 0x7
176 #define PLLA_OUTDIV_SHIFT 4
177
178 /* bit numbers of clock control register */
179 #define SYS_CTRL_CLK_COPRO 0
180 #define SYS_CTRL_CLK_DMA 1
181 #define SYS_CTRL_CLK_CIPHER 2
182 #define SYS_CTRL_CLK_SD 3
183 #define SYS_CTRL_CLK_SATA 4
184 #define SYS_CTRL_CLK_I2S 5
185 #define SYS_CTRL_CLK_USBHS 6
186 #define SYS_CTRL_CLK_MACA 7
187 #define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA
188 #define SYS_CTRL_CLK_PCIEA 8
189 #define SYS_CTRL_CLK_STATIC 9
190 #define SYS_CTRL_CLK_MACB 10
191 #define SYS_CTRL_CLK_PCIEB 11
192 #define SYS_CTRL_CLK_REF600 12
193 #define SYS_CTRL_CLK_USBDEV 13
194 #define SYS_CTRL_CLK_DDR 14
195 #define SYS_CTRL_CLK_DDRPHY 15
196 #define SYS_CTRL_CLK_DDRCK 16
197
198
199 /* bit numbers of reset control register */
200 #define SYS_CTRL_RST_SCU 0
201 #define SYS_CTRL_RST_COPRO 1
202 #define SYS_CTRL_RST_ARM0 2
203 #define SYS_CTRL_RST_ARM1 3
204 #define SYS_CTRL_RST_USBHS 4
205 #define SYS_CTRL_RST_USBHSPHYA 5
206 #define SYS_CTRL_RST_MACA 6
207 #define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
208 #define SYS_CTRL_RST_PCIEA 7
209 #define SYS_CTRL_RST_SGDMA 8
210 #define SYS_CTRL_RST_CIPHER 9
211 #define SYS_CTRL_RST_DDR 10
212 #define SYS_CTRL_RST_SATA 11
213 #define SYS_CTRL_RST_SATA_LINK 12
214 #define SYS_CTRL_RST_SATA_PHY 13
215 #define SYS_CTRL_RST_PCIEPHY 14
216 #define SYS_CTRL_RST_STATIC 15
217 #define SYS_CTRL_RST_GPIO 16
218 #define SYS_CTRL_RST_UART1 17
219 #define SYS_CTRL_RST_UART2 18
220 #define SYS_CTRL_RST_MISC 19
221 #define SYS_CTRL_RST_I2S 20
222 #define SYS_CTRL_RST_SD 21
223 #define SYS_CTRL_RST_MACB 22
224 #define SYS_CTRL_RST_PCIEB 23
225 #define SYS_CTRL_RST_VIDEO 24
226 #define SYS_CTRL_RST_DDR_PHY 25
227 #define SYS_CTRL_RST_USBHSPHYB 26
228 #define SYS_CTRL_RST_USBDEV 27
229 #define SYS_CTRL_RST_ARMDBG 29
230 #define SYS_CTRL_RST_PLLA 30
231 #define SYS_CTRL_RST_PLLB 31
232
233 #endif