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oxnas: reboot target
[openwrt/openwrt.git] / target / linux / oxnas / files / drivers / ata / sata_oxnas.c
1 /*
2 * sata_oxnas
3 * A driver to interface the 934 based sata core present in the ox820
4 * with libata and scsi
5 * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
6 * based on ox820 sata code by:
7 * Copyright (c) 2007 Oxford Semiconductor Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/ata.h>
21 #include <linux/libata.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/clk.h>
30 #include <linux/reset.h>
31
32 #include <linux/io.h>
33 #include <linux/sizes.h>
34
35 static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
36 {
37 u32 val = readl_relaxed(p);
38
39 val &= ~mask;
40 writel_relaxed(val, p);
41 }
42
43 static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
44 {
45 u32 val = readl_relaxed(p);
46
47 val |= mask;
48 writel_relaxed(val, p);
49 }
50
51 static inline void oxnas_register_value_mask(void __iomem *p,
52 unsigned mask, unsigned new_value)
53 {
54 /* TODO sanity check mask & new_value = new_value */
55 u32 val = readl_relaxed(p);
56
57 val &= ~mask;
58 val |= new_value;
59 writel_relaxed(val, p);
60 }
61
62 /* sgdma request structure */
63 struct sgdma_request {
64 volatile u32 qualifier;
65 volatile u32 control;
66 dma_addr_t src_pa;
67 dma_addr_t dst_pa;
68 } __packed __aligned(4);
69
70
71 /* Controller information */
72 enum {
73 SATA_OXNAS_MAX_PRD = 254,
74 SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
75 sizeof(struct ata_bmdma_prd) +
76 sizeof(struct sgdma_request),
77 SATA_OXNAS_MAX_PORTS = 2,
78 /** The different Oxsemi SATA core version numbers */
79 SATA_OXNAS_CORE_VERSION = 0x1f3,
80 SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
81 SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
82 ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
83 SATA_OXNAS_QUEUE_DEPTH = 32,
84
85 SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
86 };
87
88
89 /*
90 * SATA Port Registers
91 */
92 enum {
93 /** sata host port register offsets */
94 ORB1 = 0x00,
95 ORB2 = 0x04,
96 ORB3 = 0x08,
97 ORB4 = 0x0C,
98 ORB5 = 0x10,
99 MASTER_STATUS = 0x10,
100 FIS_CTRL = 0x18,
101 FIS_DATA = 0x1C,
102 INT_STATUS = 0x30,
103 INT_CLEAR = 0x30,
104 INT_ENABLE = 0x34,
105 INT_DISABLE = 0x38,
106 VERSION = 0x3C,
107 SATA_CONTROL = 0x5C,
108 SATA_COMMAND = 0x60,
109 HID_FEATURES = 0x64,
110 PORT_CONTROL = 0x68,
111 DRIVE_CONTROL = 0x6C,
112 /** These registers allow access to the link layer registers
113 that reside in a different clock domain to the processor bus */
114 LINK_DATA = 0x70,
115 LINK_RD_ADDR = 0x74,
116 LINK_WR_ADDR = 0x78,
117 LINK_CONTROL = 0x7C,
118 /* window control */
119 WIN1LO = 0x80,
120 WIN1HI = 0x84,
121 WIN2LO = 0x88,
122 WIN2HI = 0x8C,
123 WIN0_CONTROL = 0x90,
124 };
125
126 /** sata port register bits */
127 enum{
128 /**
129 * commands to issue in the master status to tell it to move shadow ,
130 * registers to the actual device ,
131 */
132 SATA_OPCODE_MASK = 0x00000007,
133 CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
134 CMD_WRITE_TO_ORB_REGS = 0x2,
135 CMD_SYNC_ESCAPE = 0x7,
136 CMD_CORE_BUSY = (1 << 7),
137 CMD_DRIVE_SELECT_SHIFT = 12,
138 CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
139
140 /** interrupt bits */
141 INT_END_OF_CMD = 1 << 0,
142 INT_LINK_SERROR = 1 << 1,
143 INT_ERROR = 1 << 2,
144 INT_LINK_IRQ = 1 << 3,
145 INT_REG_ACCESS_ERR = 1 << 7,
146 INT_BIST_FIS = 1 << 11,
147 INT_MASKABLE = INT_END_OF_CMD |
148 INT_LINK_SERROR |
149 INT_ERROR |
150 INT_LINK_IRQ |
151 INT_REG_ACCESS_ERR |
152 INT_BIST_FIS,
153 INT_WANT = INT_END_OF_CMD |
154 INT_LINK_SERROR |
155 INT_REG_ACCESS_ERR |
156 INT_ERROR,
157 INT_ERRORS = INT_LINK_SERROR |
158 INT_REG_ACCESS_ERR |
159 INT_ERROR,
160
161 /** raw interrupt bits, unmaskable, but do not generate interrupts */
162 RAW_END_OF_CMD = INT_END_OF_CMD << 16,
163 RAW_LINK_SERROR = INT_LINK_SERROR << 16,
164 RAW_ERROR = INT_ERROR << 16,
165 RAW_LINK_IRQ = INT_LINK_IRQ << 16,
166 RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
167 RAW_BIST_FIS = INT_BIST_FIS << 16,
168 RAW_WANT = INT_WANT << 16,
169 RAW_ERRORS = INT_ERRORS << 16,
170
171 /**
172 * variables to write to the device control register to set the current
173 * device, ie. master or slave.
174 */
175 DR_CON_48 = 2,
176 DR_CON_28 = 0,
177
178 SATA_CTL_ERR_MASK = 0x00000016,
179
180 };
181
182 /* ATA SGDMA register offsets */
183 enum {
184 SGDMA_CONTROL = 0x0,
185 SGDMA_STATUS = 0x4,
186 SGDMA_REQUESTPTR = 0x8,
187 SGDMA_RESETS = 0xC,
188 SGDMA_CORESIZE = 0x10,
189 };
190
191 /* DMA controller register offsets */
192 enum {
193 DMA_CONTROL = 0x0,
194 DMA_CORESIZE = 0x20,
195
196 DMA_CONTROL_RESET = (1 << 12),
197 };
198
199 enum {
200 /* see DMA core docs for the values. Out means from memory (bus A) out
201 * to disk (bus B) */
202 SGDMA_REQCTL0OUT = 0x0497c03d,
203 /* burst mode disabled when no micro code used */
204 SGDMA_REQCTL0IN = 0x0493a3c1,
205 SGDMA_REQCTL1OUT = 0x0497c07d,
206 SGDMA_REQCTL1IN = 0x0497a3c5,
207 SGDMA_CONTROL_NOGO = 0x3e,
208 SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
209 SGDMA_ERRORMASK = 0x3f,
210 SGDMA_BUSY = 0x80,
211
212 SGDMA_RESETS_CTRL = 1 << 0,
213 SGDMA_RESETS_ARBT = 1 << 1,
214 SGDMA_RESETS_AHB = 1 << 2,
215 SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
216 SGDMA_RESETS_ARBT |
217 SGDMA_RESETS_AHB,
218
219 /* Final EOTs */
220 SGDMA_REQQUAL = 0x00220001,
221
222 };
223
224 /** SATA core register offsets */
225 enum {
226 DM_DBG1 = 0x000,
227 RAID_SET = 0x004,
228 DM_DBG2 = 0x008,
229 DATACOUNT_PORT0 = 0x010,
230 DATACOUNT_PORT1 = 0x014,
231 CORE_INT_STATUS = 0x030,
232 CORE_INT_CLEAR = 0x030,
233 CORE_INT_ENABLE = 0x034,
234 CORE_INT_DISABLE = 0x038,
235 CORE_REBUILD_ENABLE = 0x050,
236 CORE_FAILED_PORT_R = 0x054,
237 DEVICE_CONTROL = 0x068,
238 EXCESS = 0x06C,
239 RAID_SIZE_LOW = 0x070,
240 RAID_SIZE_HIGH = 0x074,
241 PORT_ERROR_MASK = 0x078,
242 IDLE_STATUS = 0x07C,
243 RAID_CONTROL = 0x090,
244 DATA_PLANE_CTRL = 0x0AC,
245 CORE_DATAPLANE_STAT = 0x0b8,
246 PROC_PC = 0x100,
247 CONFIG_IN = 0x3d8,
248 PROC_START = 0x3f0,
249 PROC_RESET = 0x3f4,
250 UCODE_STORE = 0x1000,
251 RAID_WP_BOT_LOW = 0x1FF0,
252 RAID_WP_BOT_HIGH = 0x1FF4,
253 RAID_WP_TOP_LOW = 0x1FF8,
254 RAID_WP_TOP_HIGH = 0x1FFC,
255 DATA_MUX_RAM0 = 0x8000,
256 DATA_MUX_RAM1 = 0xA000,
257 PORT_SIZE = 0x10000,
258 };
259
260 enum {
261 /* Sata core debug1 register bits */
262 CORE_PORT0_DATA_DIR_BIT = 20,
263 CORE_PORT1_DATA_DIR_BIT = 21,
264 CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
265 CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
266
267 /** sata core control register bits */
268 SCTL_CLR_ERR = 0x00003016,
269 RAID_CLR_ERR = 0x0000011e,
270
271 /* Interrupts direct from the ports */
272 NORMAL_INTS_WANTED = 0x00000303,
273
274 /* shift these left by port number */
275 COREINT_HOST = 0x00000001,
276 COREINT_END = 0x00000100,
277 CORERAW_HOST = COREINT_HOST << 16,
278 CORERAW_END = COREINT_END << 16,
279
280 /* Interrupts from the RAID controller only */
281 RAID_INTS_WANTED = 0x00008300,
282
283 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
284 IDLE_CORES = (1 << 18) | (1 << 19),
285
286 /* Data plane control error-mask mask and bit, these bit in the data
287 * plane control mask out errors from the ports that prevent the SGDMA
288 * care from sending an interrupt */
289 DPC_ERROR_MASK = 0x00000300,
290 DPC_ERROR_MASK_BIT = 0x00000100,
291 /* enable jbod micro-code */
292 DPC_JBOD_UCODE = 1 << 0,
293 DPC_FIS_SWCH = 1 << 1,
294
295 /** Device Control register bits */
296 DEVICE_CONTROL_DMABT = 1 << 4,
297 DEVICE_CONTROL_ABORT = 1 << 2,
298 DEVICE_CONTROL_PAD = 1 << 3,
299 DEVICE_CONTROL_PADPAT = 1 << 16,
300 DEVICE_CONTROL_PRTRST = 1 << 8,
301 DEVICE_CONTROL_RAMRST = 1 << 12,
302 DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
303
304 /** oxsemi HW raid modes */
305 OXNASSATA_NOTRAID = 0,
306 OXNASSATA_RAID0 = 1,
307 OXNASSATA_RAID1 = 2,
308 /** OX820 specific HW-RAID register values */
309 RAID_TWODISKS = 3,
310 UNKNOWN_MODE = ~0,
311
312 CONFIG_IN_RESUME = 2,
313 };
314
315 /* SATA PHY Registers */
316 enum {
317 PHY_STAT = 0x00,
318 PHY_DATA = 0x04,
319 };
320
321 enum {
322 STAT_READ_VALID = (1 << 21),
323 STAT_CR_ACK = (1 << 20),
324 STAT_CR_READ = (1 << 19),
325 STAT_CR_WRITE = (1 << 18),
326 STAT_CAP_DATA = (1 << 17),
327 STAT_CAP_ADDR = (1 << 16),
328
329 STAT_ACK_ANY = STAT_CR_ACK |
330 STAT_CR_READ |
331 STAT_CR_WRITE |
332 STAT_CAP_DATA |
333 STAT_CAP_ADDR,
334
335 CR_READ_ENABLE = (1 << 16),
336 CR_WRITE_ENABLE = (1 << 17),
337 CR_CAP_DATA = (1 << 18),
338 };
339
340 enum {
341 /* Link layer registers */
342 SERROR_IRQ_MASK = 5,
343 };
344
345 enum {
346 OXNAS_SATA_SOFTRESET = 1,
347 OXNAS_SATA_REINIT = 2,
348 };
349
350 enum {
351 OXNAS_SATA_UCODE_RAID0,
352 OXNAS_SATA_UCODE_RAID1,
353 OXNAS_SATA_UCODE_JBOD,
354 OXNAS_SATA_UCODE_NONE,
355 };
356
357 enum {
358 SATA_UNLOCKED,
359 SATA_WRITER,
360 SATA_READER,
361 SATA_REBUILD,
362 SATA_HWRAID,
363 SATA_SCSI_STACK
364 };
365
366 typedef irqreturn_t (*oxnas_sata_isr_callback_t)(int, unsigned long, int);
367
368 struct sata_oxnas_host_priv {
369 void __iomem *port_base;
370 void __iomem *dmactl_base;
371 void __iomem *sgdma_base;
372 void __iomem *core_base;
373 void __iomem *phy_base;
374 dma_addr_t dma_base;
375 void __iomem *dma_base_va;
376 size_t dma_size;
377 int irq;
378 int n_ports;
379 int current_ucode;
380 u32 port_frozen;
381 u32 port_in_eh;
382 struct clk *clk;
383 struct reset_control *rst_sata;
384 struct reset_control *rst_link;
385 struct reset_control *rst_phy;
386 spinlock_t phy_lock;
387 spinlock_t core_lock;
388 int core_locked;
389 int reentrant_port_no;
390 int hw_lock_count;
391 int direct_lock_count;
392 void *locker_uid;
393 int current_locker_type;
394 int scsi_nonblocking_attempts;
395 oxnas_sata_isr_callback_t isr_callback;
396 void *isr_arg;
397 wait_queue_head_t fast_wait_queue;
398 wait_queue_head_t scsi_wait_queue;
399 };
400
401
402 struct sata_oxnas_port_priv {
403 void __iomem *port_base;
404 void __iomem *dmactl_base;
405 void __iomem *sgdma_base;
406 void __iomem *core_base;
407 struct sgdma_request *sgdma_request;
408 dma_addr_t sgdma_request_pa;
409 };
410
411 static u8 sata_oxnas_check_status(struct ata_port *ap);
412 static int sata_oxnas_cleanup(struct ata_host *ah);
413 static void sata_oxnas_tf_load(struct ata_port *ap,
414 const struct ata_taskfile *tf);
415 static void sata_oxnas_irq_on(struct ata_port *ap);
416 static void sata_oxnas_post_reset_init(struct ata_port *ap);
417
418 static int sata_oxnas_acquire_hw(struct ata_port *ap, int may_sleep,
419 int timeout_jiffies);
420 static void sata_oxnas_release_hw(struct ata_port *ap);
421
422 static const void *HW_LOCKER_UID = (void *)0xdeadbeef;
423
424 /***************************************************************************
425 * ASIC access
426 ***************************************************************************/
427 static void wait_cr_ack(void __iomem *phy_base)
428 {
429 while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
430 ; /* wait for an ack bit to be set */
431 }
432
433 static u16 read_cr(void __iomem *phy_base, u16 address)
434 {
435 iowrite32((u32)address, phy_base + PHY_STAT);
436 wait_cr_ack(phy_base);
437 iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
438 wait_cr_ack(phy_base);
439 return (u16)ioread32(phy_base + PHY_STAT);
440 }
441
442 static void write_cr(void __iomem *phy_base, u16 data, u16 address)
443 {
444 iowrite32((u32)address, phy_base + PHY_STAT);
445 wait_cr_ack(phy_base);
446 iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
447 wait_cr_ack(phy_base);
448 iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
449 wait_cr_ack(phy_base);
450 }
451
452 #define PH_GAIN 2
453 #define FR_GAIN 3
454 #define PH_GAIN_OFFSET 6
455 #define FR_GAIN_OFFSET 8
456 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
457 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
458 #define USE_INT_SETTING (1<<5)
459
460 void workaround5458(struct ata_host *ah)
461 {
462 struct sata_oxnas_host_priv *hd = ah->private_data;
463 void __iomem *phy_base = hd->phy_base;
464 u16 rx_control;
465 unsigned i;
466
467 for (i = 0; i < 2; i++) {
468 rx_control = read_cr(phy_base, 0x201d + (i << 8));
469 rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
470 rx_control |= PH_GAIN << PH_GAIN_OFFSET;
471 rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
472 write_cr(phy_base, rx_control, 0x201d+(i<<8));
473 }
474 }
475
476 /**
477 * allows access to the link layer registers
478 * @param link_reg the link layer register to access (oxsemi indexing ie
479 * 00 = static config, 04 = phy ctrl)
480 */
481 void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
482 {
483 struct sata_oxnas_port_priv *pd = ap->private_data;
484 struct sata_oxnas_host_priv *hd = ap->host->private_data;
485 void __iomem *port_base = pd->port_base;
486 u32 patience;
487 unsigned long flags;
488
489 DPRINTK("P%d [0x%02x]->0x%08x\n", ap->port_no, link_reg, val);
490
491 spin_lock_irqsave(&hd->phy_lock, flags);
492 iowrite32(val, port_base + LINK_DATA);
493
494 /* accessed twice as a work around for a bug in the SATA abp bridge
495 * hardware (bug 6828) */
496 iowrite32(link_reg , port_base + LINK_WR_ADDR);
497 ioread32(port_base + LINK_WR_ADDR);
498
499 for (patience = 0x100000; patience > 0; --patience) {
500 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
501 break;
502 }
503 spin_unlock_irqrestore(&hd->phy_lock, flags);
504 }
505
506 static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
507 u32 val)
508 {
509 sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
510 return 0;
511 }
512
513 static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
514 u32 val)
515 {
516 return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
517 }
518
519 u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
520 {
521 struct sata_oxnas_port_priv *pd = ap->private_data;
522 struct sata_oxnas_host_priv *hd = ap->host->private_data;
523 void __iomem *port_base = pd->port_base;
524 u32 result;
525 u32 patience;
526 unsigned long flags;
527
528 spin_lock_irqsave(&hd->phy_lock, flags);
529 /* accessed twice as a work around for a bug in the SATA abp bridge
530 * hardware (bug 6828) */
531 iowrite32(link_reg, port_base + LINK_RD_ADDR);
532 ioread32(port_base + LINK_RD_ADDR);
533
534 for (patience = 0x100000; patience > 0; --patience) {
535 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
536 break;
537 }
538 if (patience == 0)
539 DPRINTK("link read timed out for port %d\n", ap->port_no);
540
541 result = ioread32(port_base + LINK_DATA);
542 spin_unlock_irqrestore(&hd->phy_lock, flags);
543
544 return result;
545 }
546
547 static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
548 u32 *val)
549 {
550 *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
551 return 0;
552 }
553
554 static int sata_oxnas_scr_read(struct ata_link *link,
555 unsigned int sc_reg, u32 *val)
556 {
557 return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
558 }
559
560 /**
561 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
562 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
563 * in the SATA core.
564 *
565 * @param ap hardware with the registers in
566 */
567 static void sata_oxnas_irq_clear(struct ata_port *ap)
568 {
569 struct sata_oxnas_port_priv *port_priv = ap->private_data;
570
571 /* clear pending interrupts */
572 iowrite32(~0, port_priv->port_base + INT_CLEAR);
573 iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
574 }
575
576 /**
577 * qc_issue is used to make a command active, once the hardware and S/G tables
578 * have been prepared. IDE BMDMA drivers use the helper function
579 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
580 * drivers roll their own ->qc_issue implementation, using this as the
581 * "issue new ATA command to hardware" hook.
582 * @param qc the queued command to issue
583 */
584 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
585 {
586 struct sata_oxnas_port_priv *pd = qc->ap->private_data;
587 struct sata_oxnas_host_priv *hd = qc->ap->host->private_data;
588
589 void __iomem *port_base = pd->port_base;
590 void __iomem *core_base = pd->core_base;
591 int port_no = qc->ap->port_no;
592 int no_microcode = (hd->current_ucode == UNKNOWN_MODE);
593 u32 reg;
594
595 /* check the core is idle */
596 if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
597 int count = 0;
598
599 DPRINTK("core busy for a command on port %d\n",
600 qc->ap->port_no);
601 do {
602 mdelay(1);
603 if (++count > 100) {
604 DPRINTK("core busy for a command on port %d\n",
605 qc->ap->port_no);
606 /* CrazyDumpDebug(); */
607 sata_oxnas_cleanup(qc->ap->host);
608 }
609 } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
610 }
611
612 /* enable passing of error signals to DMA sub-core by clearing the
613 * appropriate bit */
614 reg = ioread32(core_base + DATA_PLANE_CTRL);
615 if (no_microcode)
616 reg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1));
617 reg &= ~(DPC_ERROR_MASK_BIT << port_no);
618 iowrite32(reg, core_base + DATA_PLANE_CTRL);
619
620 /* Disable all interrupts for ports and RAID controller */
621 iowrite32(~0, port_base + INT_DISABLE);
622
623 /* Disable all interrupts for core */
624 iowrite32(~0, core_base + CORE_INT_DISABLE);
625 wmb();
626
627 /* Load the command settings into the orb registers */
628 sata_oxnas_tf_load(qc->ap, &qc->tf);
629
630 /* both pio and dma commands use dma */
631 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
632 /* Start the DMA */
633 iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
634 wmb();
635 }
636
637 /* enable End of command interrupt */
638 iowrite32(INT_WANT, port_base + INT_ENABLE);
639 iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
640 wmb();
641
642 /* Start the command */
643 reg = ioread32(port_base + SATA_COMMAND);
644 reg &= ~SATA_OPCODE_MASK;
645 reg |= CMD_WRITE_TO_ORB_REGS;
646 iowrite32(reg , port_base + SATA_COMMAND);
647 wmb();
648
649 return 0;
650 }
651
652 /**
653 * Will schedule the libATA error handler on the premise that there has
654 * been a hotplug event on the port specified
655 */
656 void sata_oxnas_checkforhotplug(struct ata_port *ap)
657 {
658 DPRINTK("ENTER\n");
659
660 ata_ehi_hotplugged(&ap->link.eh_info);
661 ata_port_freeze(ap);
662 }
663
664
665 /**************************************************************************/
666 /* Locking */
667 /**************************************************************************/
668 /**
669 * The underlying function that controls access to the sata core
670 *
671 * @return non-zero indicates that you have acquired exclusive access to the
672 * sata core.
673 */
674 static int __acquire_sata_core(
675 struct ata_host *ah,
676 int port_no,
677 oxnas_sata_isr_callback_t callback,
678 void *arg,
679 int may_sleep,
680 int timeout_jiffies,
681 int hw_access,
682 void *uid,
683 int locker_type)
684 {
685 unsigned long end = jiffies + timeout_jiffies;
686 int acquired = 0;
687 unsigned long flags;
688 int timed_out = 0;
689 struct sata_oxnas_host_priv *hd;
690
691 DEFINE_WAIT(wait);
692
693 if (!ah)
694 return acquired;
695
696 hd = ah->private_data;
697
698 spin_lock_irqsave(&hd->core_lock, flags);
699
700 DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, "
701 "callback %p, hw_access %d, core_locked %d, "
702 "reentrant_port_no %d, isr_callback %p\n",
703 uid, port_no, hd->hw_lock_count, hd->direct_lock_count,
704 callback, hw_access, hd->core_locked, hd->reentrant_port_no,
705 hd->isr_callback);
706
707 while (!timed_out) {
708 if (hd->core_locked ||
709 (!hw_access && hd->scsi_nonblocking_attempts)) {
710 /* Can only allow access if from SCSI/SATA stack and if
711 * reentrant access is allowed and this access is to the
712 * same port for which the lock is current held
713 */
714 if (hw_access && (port_no == hd->reentrant_port_no)) {
715 BUG_ON(!hd->hw_lock_count);
716 ++(hd->hw_lock_count);
717
718 DPRINTK("Allow SCSI/SATA re-entrant access to "
719 "uid %p port %d\n", uid, port_no);
720 acquired = 1;
721 break;
722 } else if (!hw_access) {
723 if ((locker_type == SATA_READER) &&
724 (hd->current_locker_type == SATA_READER)) {
725 WARN(1,
726 "Already locked by reader, "
727 "uid %p, locker_uid %p, "
728 "port %d, h/w count %d, "
729 "d count %d, hw_access %d\n",
730 uid, hd->locker_uid, port_no,
731 hd->hw_lock_count,
732 hd->direct_lock_count,
733 hw_access);
734 goto check_uid;
735 }
736
737 if ((locker_type != SATA_READER) &&
738 (locker_type != SATA_WRITER)) {
739 goto wait_for_lock;
740 }
741
742 check_uid:
743 WARN(uid == hd->locker_uid, "Attempt to lock "
744 "by locker type %d uid %p, already "
745 "locked by locker type %d with "
746 "locker_uid %p, port %d, "
747 "h/w count %d, d count %d, "
748 "hw_access %d\n", locker_type, uid,
749 hd->current_locker_type,
750 hd->locker_uid, port_no,
751 hd->hw_lock_count,
752 hd->direct_lock_count, hw_access);
753 }
754 } else {
755 WARN(hd->hw_lock_count || hd->direct_lock_count,
756 "Core unlocked but counts non-zero: uid %p, "
757 "locker_uid %p, port %d, h/w count %d, "
758 "d count %d, hw_access %d\n", uid,
759 hd->locker_uid, port_no, hd->hw_lock_count,
760 hd->direct_lock_count, hw_access);
761
762 BUG_ON(hd->current_locker_type != SATA_UNLOCKED);
763
764 WARN(hd->locker_uid, "Attempt to lock uid %p when "
765 "locker_uid %p is non-zero, port %d, "
766 "h/w count %d, d count %d, hw_access %d\n",
767 uid, hd->locker_uid, port_no, hd->hw_lock_count,
768 hd->direct_lock_count, hw_access);
769
770 if (!hw_access) {
771 /* Direct access attempting to acquire
772 * non-contented lock
773 */
774 /* Must have callback for direct access */
775 BUG_ON(!callback);
776 /* Sanity check lock state */
777 BUG_ON(hd->reentrant_port_no != -1);
778
779 hd->isr_callback = callback;
780 hd->isr_arg = arg;
781 ++(hd->direct_lock_count);
782
783 hd->current_locker_type = locker_type;
784 } else {
785 /* SCSI/SATA attempting to acquire
786 * non-contented lock
787 */
788 /* No callbacks for SCSI/SATA access */
789 BUG_ON(callback);
790 /* No callback args for SCSI/SATA access */
791 BUG_ON(arg);
792
793 /* Sanity check lock state */
794 BUG_ON(hd->isr_callback);
795 BUG_ON(hd->isr_arg);
796
797 ++(hd->hw_lock_count);
798 hd->reentrant_port_no = port_no;
799
800 hd->current_locker_type = SATA_SCSI_STACK;
801 }
802
803 hd->core_locked = 1;
804 hd->locker_uid = uid;
805 acquired = 1;
806 break;
807 }
808
809 wait_for_lock:
810 if (!may_sleep) {
811 DPRINTK("Denying for uid %p locker_type %d, "
812 "hw_access %d, port %d, current_locker_type %d as "
813 "cannot sleep\n", uid, locker_type, hw_access, port_no,
814 hd->current_locker_type);
815
816 if (hw_access)
817 ++(hd->scsi_nonblocking_attempts);
818
819 break;
820 }
821
822 /* Core is locked and we're allowed to sleep, so wait to be
823 * awoken when the core is unlocked
824 */
825 for (;;) {
826 prepare_to_wait(hw_access ? &hd->scsi_wait_queue :
827 &hd->fast_wait_queue,
828 &wait, TASK_UNINTERRUPTIBLE);
829 if (!hd->core_locked &&
830 !(!hw_access && hd->scsi_nonblocking_attempts)) {
831 /* We're going to use variables that will have
832 * been changed by the waker prior to clearing
833 * core_locked so we need to ensure we see
834 * changes to all those variables
835 */
836 smp_rmb();
837 break;
838 }
839 if (time_after(jiffies, end)) {
840 printk(KERN_WARNING "__acquire_sata_core() "
841 "uid %p failing for port %d timed out, "
842 "locker_uid %p, h/w count %d, "
843 "d count %d, callback %p, hw_access %d, "
844 "core_locked %d, reentrant_port_no %d, "
845 "isr_callback %p, isr_arg %p\n", uid,
846 port_no, hd->locker_uid,
847 hd->hw_lock_count,
848 hd->direct_lock_count, callback,
849 hw_access, hd->core_locked,
850 hd->reentrant_port_no, hd->isr_callback,
851 hd->isr_arg);
852 timed_out = 1;
853 break;
854 }
855 spin_unlock_irqrestore(&hd->core_lock, flags);
856 if (!schedule_timeout(4*HZ)) {
857 printk(KERN_INFO "__acquire_sata_core() uid %p, "
858 "locker_uid %p, timed-out of "
859 "schedule(), checking overall timeout\n",
860 uid, hd->locker_uid);
861 }
862 spin_lock_irqsave(&hd->core_lock, flags);
863 }
864 finish_wait(hw_access ? &hd->scsi_wait_queue :
865 &hd->fast_wait_queue, &wait);
866 }
867
868 if (hw_access && acquired) {
869 if (hd->scsi_nonblocking_attempts)
870 hd->scsi_nonblocking_attempts = 0;
871
872 /* Wake any other SCSI/SATA waiters so they can get reentrant
873 * access to the same port if appropriate. This is because if
874 * the SATA core is locked by fast access, or SCSI/SATA access
875 * to other port, then can have >1 SCSI/SATA waiters on the wait
876 * list so want to give reentrant accessors a chance to get
877 * access ASAP
878 */
879 if (!list_empty(&hd->scsi_wait_queue.head))
880 wake_up(&hd->scsi_wait_queue);
881 }
882
883 DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n",
884 uid, acquired, port_no, callback);
885
886 spin_unlock_irqrestore(&hd->core_lock, flags);
887
888 return acquired;
889 }
890
891 int sata_core_has_fast_waiters(struct ata_host *ah)
892 {
893 int has_waiters;
894 unsigned long flags;
895 struct sata_oxnas_host_priv *hd = ah->private_data;
896
897 spin_lock_irqsave(&hd->core_lock, flags);
898 has_waiters = !list_empty(&hd->fast_wait_queue.head);
899 spin_unlock_irqrestore(&hd->core_lock, flags);
900
901 return has_waiters;
902 }
903 EXPORT_SYMBOL(sata_core_has_fast_waiters);
904
905 int sata_core_has_scsi_waiters(struct ata_host *ah)
906 {
907 int has_waiters;
908 unsigned long flags;
909 struct sata_oxnas_host_priv *hd = ah->private_data;
910
911 spin_lock_irqsave(&hd->core_lock, flags);
912 has_waiters = hd->scsi_nonblocking_attempts ||
913 !list_empty(&hd->scsi_wait_queue.head);
914 spin_unlock_irqrestore(&hd->core_lock, flags);
915
916 return has_waiters;
917 }
918 EXPORT_SYMBOL(sata_core_has_scsi_waiters);
919
920 /*
921 * ata_port operation to gain ownership of the SATA hardware prior to issuing
922 * a command against a SATA host. Allows any number of users of the port against
923 * which the lock was first acquired, thus enforcing that only one SATA core
924 * port may be operated on at once.
925 */
926 static int sata_oxnas_acquire_hw(
927 struct ata_port *ap,
928 int may_sleep,
929 int timeout_jiffies)
930 {
931 return __acquire_sata_core(ap->host, ap->port_no, NULL, 0, may_sleep,
932 timeout_jiffies, 1, (void *)HW_LOCKER_UID,
933 SATA_SCSI_STACK);
934 }
935
936 /*
937 * operation to release ownership of the SATA hardware
938 */
939 static void sata_oxnas_release_hw(struct ata_port *ap)
940 {
941 unsigned long flags;
942 int released = 0;
943 struct sata_oxnas_host_priv *hd = ap->host->private_data;
944
945 spin_lock_irqsave(&hd->core_lock, flags);
946
947 DPRINTK("Entered port_no = %d, h/w count %d, d count %d, "
948 "core locked = %d, reentrant_port_no = %d, isr_callback %p\n",
949 ap->port_no, hd->hw_lock_count, hd->direct_lock_count,
950 hd->core_locked, hd->reentrant_port_no, hd->isr_callback);
951
952 if (!hd->core_locked) {
953 /* Nobody holds the SATA lock */
954 printk(KERN_WARNING "Nobody holds SATA lock, port_no %d\n",
955 ap->port_no);
956 released = 1;
957 } else if (!hd->hw_lock_count) {
958 /* SCSI/SATA has released without holding the lock */
959 printk(KERN_WARNING "SCSI/SATA does not hold SATA lock, "
960 "port_no %d\n", ap->port_no);
961 } else {
962 /* Trap incorrect usage */
963 BUG_ON(hd->reentrant_port_no == -1);
964 BUG_ON(ap->port_no != hd->reentrant_port_no);
965 BUG_ON(hd->direct_lock_count);
966 BUG_ON(hd->current_locker_type != SATA_SCSI_STACK);
967
968 WARN(!hd->locker_uid || (hd->locker_uid != HW_LOCKER_UID),
969 "Invalid locker uid %p, h/w count %d, d count %d, "
970 "reentrant_port_no %d, core_locked %d, "
971 "isr_callback %p\n", hd->locker_uid, hd->hw_lock_count,
972 hd->direct_lock_count, hd->reentrant_port_no,
973 hd->core_locked, hd->isr_callback);
974
975 if (--(hd->hw_lock_count)) {
976 DPRINTK("Still nested port_no %d\n", ap->port_no);
977 } else {
978 DPRINTK("Release port_no %d\n", ap->port_no);
979 hd->reentrant_port_no = -1;
980 hd->isr_callback = NULL;
981 hd->current_locker_type = SATA_UNLOCKED;
982 hd->locker_uid = 0;
983 hd->core_locked = 0;
984 released = 1;
985 wake_up(!list_empty(&hd->scsi_wait_queue.head) ?
986 &hd->scsi_wait_queue :
987 &hd->fast_wait_queue);
988 }
989 }
990
991 DPRINTK("Leaving, port_no %d, count %d\n", ap->port_no,
992 hd->hw_lock_count);
993
994 spin_unlock_irqrestore(&hd->core_lock, flags);
995
996 /* CONFIG_SATA_OX820_DIRECT_HWRAID */
997 /* if (released)
998 ox820hwraid_restart_queue();
999 } */
1000 }
1001
1002 static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
1003 {
1004 struct sata_oxnas_host_priv *hd = ah->private_data;
1005
1006 smp_rmb();
1007 return hd->port_in_eh || hd->port_frozen;
1008 }
1009
1010
1011 static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
1012 {
1013 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1014
1015 return (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) ||
1016 (hd->n_ports > 1 &&
1017 (ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) &
1018 CMD_CORE_BUSY));
1019 }
1020
1021 static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
1022 {
1023 struct sata_oxnas_port_priv *pd = ap->private_data;
1024
1025 return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
1026 }
1027
1028
1029 /**
1030 * Turns on the cores clock and resets it
1031 */
1032 static void sata_oxnas_reset_core(struct ata_host *ah)
1033 {
1034 struct sata_oxnas_host_priv *host_priv = ah->private_data;
1035 int n;
1036
1037 DPRINTK("ENTER\n");
1038 clk_prepare_enable(host_priv->clk);
1039
1040 reset_control_assert(host_priv->rst_sata);
1041 reset_control_assert(host_priv->rst_link);
1042 reset_control_assert(host_priv->rst_phy);
1043
1044 udelay(50);
1045
1046 /* un-reset the PHY, then Link and Controller */
1047 reset_control_deassert(host_priv->rst_phy);
1048 udelay(50);
1049
1050 reset_control_deassert(host_priv->rst_sata);
1051 reset_control_deassert(host_priv->rst_link);
1052 udelay(50);
1053
1054 workaround5458(ah);
1055 /* tune for sata compatibility */
1056 sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
1057
1058 for (n = 0; n < host_priv->n_ports; n++) {
1059 /* each port in turn */
1060 sata_oxnas_link_write(ah->ports[n], 0x70, 0x55629);
1061 }
1062 udelay(50);
1063 }
1064
1065
1066 /**
1067 * Called after an identify device command has worked out what kind of device
1068 * is on the port
1069 *
1070 * @param port The port to configure
1071 * @param pdev The hardware associated with controlling the port
1072 */
1073 static void sata_oxnas_dev_config(struct ata_device *pdev)
1074 {
1075 struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
1076 void __iomem *port_base = pd->port_base;
1077 u32 reg;
1078
1079 DPRINTK("ENTER\n");
1080 /* Set the bits to put the port into 28 or 48-bit node */
1081 reg = ioread32(port_base + DRIVE_CONTROL);
1082 reg &= ~3;
1083 reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
1084 iowrite32(reg, port_base + DRIVE_CONTROL);
1085
1086 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
1087 if (pdev->flags & ATA_DFLAG_LBA48) {
1088 reg = ioread32(port_base + PORT_CONTROL);
1089 reg |= 2;
1090 iowrite32(reg, port_base + PORT_CONTROL);
1091 }
1092 }
1093 /**
1094 * called to write a taskfile into the ORB registers
1095 * @param ap hardware with the registers in
1096 * @param tf taskfile to write to the registers
1097 */
1098 static void sata_oxnas_tf_load(struct ata_port *ap,
1099 const struct ata_taskfile *tf)
1100 {
1101 u32 count = 0;
1102 u32 Orb1 = 0;
1103 u32 Orb2 = 0;
1104 u32 Orb3 = 0;
1105 u32 Orb4 = 0;
1106 u32 Command_Reg;
1107
1108 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1109 void __iomem *port_base = port_priv->port_base;
1110 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
1111
1112 /* wait a maximum of 10ms for the core to be idle */
1113 do {
1114 Command_Reg = ioread32(port_base + SATA_COMMAND);
1115 if (!(Command_Reg & CMD_CORE_BUSY))
1116 break;
1117 count++;
1118 udelay(50);
1119 } while (count < 200);
1120
1121 /* check if the ctl register has interrupts disabled or enabled and
1122 * modify the interrupt enable registers on the ata core as required */
1123 if (tf->ctl & ATA_NIEN) {
1124 /* interrupts disabled */
1125 u32 mask = (COREINT_END << ap->port_no);
1126
1127 iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
1128 sata_oxnas_irq_clear(ap);
1129 } else {
1130 sata_oxnas_irq_on(ap);
1131 }
1132
1133 Orb2 |= (tf->command) << 24;
1134
1135 /* write 48 or 28 bit tf parameters */
1136 if (is_addr) {
1137 /* set LBA bit as it's an address */
1138 Orb1 |= (tf->device & ATA_LBA) << 24;
1139
1140 if (tf->flags & ATA_TFLAG_LBA48) {
1141 Orb1 |= ATA_LBA << 24;
1142 Orb2 |= (tf->hob_nsect) << 8;
1143 Orb3 |= (tf->hob_lbal) << 24;
1144 Orb4 |= (tf->hob_lbam) << 0;
1145 Orb4 |= (tf->hob_lbah) << 8;
1146 Orb4 |= (tf->hob_feature) << 16;
1147 } else {
1148 Orb3 |= (tf->device & 0xf) << 24;
1149 }
1150
1151 /* write 28-bit lba */
1152 Orb2 |= (tf->nsect) << 0;
1153 Orb2 |= (tf->feature) << 16;
1154 Orb3 |= (tf->lbal) << 0;
1155 Orb3 |= (tf->lbam) << 8;
1156 Orb3 |= (tf->lbah) << 16;
1157 Orb4 |= (tf->ctl) << 24;
1158 }
1159
1160 if (tf->flags & ATA_TFLAG_DEVICE)
1161 Orb1 |= (tf->device) << 24;
1162
1163 ap->last_ctl = tf->ctl;
1164
1165 /* write values to registers */
1166 iowrite32(Orb1, port_base + ORB1);
1167 iowrite32(Orb2, port_base + ORB2);
1168 iowrite32(Orb3, port_base + ORB3);
1169 iowrite32(Orb4, port_base + ORB4);
1170 }
1171
1172
1173 void sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force)
1174 {
1175 struct sata_oxnas_host_priv *host_priv = ah->private_data;
1176 void __iomem *core_base = host_priv->core_base;
1177
1178 unsigned int *src;
1179 void __iomem *dst;
1180 unsigned int progmicrocode = 0;
1181 unsigned int changeparameters = 0;
1182
1183 u32 previous_mode;
1184
1185 /* these micro-code programs _should_ include the version word */
1186
1187 /* JBOD */
1188 static const unsigned int jbod[] = {
1189 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
1190 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
1191 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
1192 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
1193 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
1194 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
1195 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
1196 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
1197 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
1198 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
1199 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
1200 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1201 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
1202 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1203 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
1204 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
1205 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
1206 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
1207 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
1208 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
1209 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
1210 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
1211 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
1212 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
1213 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
1214 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
1215 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
1216 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
1217 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
1218 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
1219 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
1220 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
1221 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
1222 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
1223 0x00718908, 0x0208A206, 0x00EE0005, ~0
1224 };
1225
1226 /* Bi-Modal RAID-0/1 */
1227 static const unsigned int raid[] = {
1228 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
1229 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
1230 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
1231 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
1232 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
1233 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
1234 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
1235 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
1236 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
1237 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
1238 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
1239 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
1240 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
1241 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
1242 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
1243 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
1244 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
1245 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
1246 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
1247 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
1248 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
1249 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
1250 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
1251 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
1252 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
1253 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
1254 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
1255 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
1256 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
1257 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
1258 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
1259 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
1260 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
1261 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
1262 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
1263 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
1264 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
1265 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
1266 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
1267 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
1268 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
1269 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
1270 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
1271 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
1272 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
1273 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
1274 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
1275 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
1276 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
1277 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
1278 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
1279 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
1280 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
1281 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
1282 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
1283 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
1284 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
1285 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
1286 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
1287 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
1288 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
1289 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
1290 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
1291 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
1292 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
1293 0x02400000, ~0
1294 };
1295
1296 DPRINTK("ENTER: mode:%d, force:%d\n", mode, force);
1297
1298 if (force)
1299 previous_mode = UNKNOWN_MODE;
1300 else
1301 previous_mode = host_priv->current_ucode;
1302
1303 if (mode == previous_mode)
1304 return;
1305
1306 host_priv->current_ucode = mode;
1307
1308 /* decide what needs to be done using the STD in my logbook */
1309 switch (previous_mode) {
1310 case OXNASSATA_RAID1:
1311 switch (mode) {
1312 case OXNASSATA_RAID0:
1313 changeparameters = 1;
1314 break;
1315 case OXNASSATA_NOTRAID:
1316 changeparameters = 1;
1317 progmicrocode = 1;
1318 break;
1319 }
1320 break;
1321 case OXNASSATA_RAID0:
1322 switch (mode) {
1323 case OXNASSATA_RAID1:
1324 changeparameters = 1;
1325 break;
1326 case OXNASSATA_NOTRAID:
1327 changeparameters = 1;
1328 progmicrocode = 1;
1329 break;
1330 }
1331 break;
1332 case OXNASSATA_NOTRAID:
1333 switch (mode) {
1334 case OXNASSATA_RAID0:
1335 case OXNASSATA_RAID1:
1336 changeparameters = 1;
1337 progmicrocode = 1;
1338 break;
1339 }
1340 break;
1341 case UNKNOWN_MODE:
1342 changeparameters = 1;
1343 progmicrocode = 1;
1344 break;
1345 }
1346
1347 /* no need to reprogram everything if already in the right mode */
1348 if (progmicrocode) {
1349 /* reset micro-code processor */
1350 iowrite32(1, core_base + PROC_RESET);
1351 wmb();
1352
1353 /* select micro-code */
1354 switch (mode) {
1355 case OXNASSATA_RAID1:
1356 case OXNASSATA_RAID0:
1357 VPRINTK("Loading RAID micro-code\n");
1358 src = (unsigned int *)&raid[1];
1359 break;
1360 case OXNASSATA_NOTRAID:
1361 VPRINTK("Loading JBOD micro-code\n");
1362 src = (unsigned int *)&jbod[1];
1363 break;
1364 default:
1365 BUG();
1366 break;
1367 }
1368
1369 /* load micro code */
1370 dst = core_base + UCODE_STORE;
1371 while (*src != ~0) {
1372 iowrite32(*src, dst);
1373 src++;
1374 dst += sizeof(*src);
1375 }
1376 wmb();
1377 }
1378
1379 if (changeparameters) {
1380 u32 reg;
1381 /* set other mode dependent flags */
1382 switch (mode) {
1383 case OXNASSATA_RAID1:
1384 /* clear JBOD mode */
1385 reg = ioread32(core_base + DATA_PLANE_CTRL);
1386 reg |= DPC_JBOD_UCODE;
1387 reg &= ~DPC_FIS_SWCH;
1388 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1389 wmb();
1390
1391 /* set the hardware up for RAID-1 */
1392 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1393 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1394 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1395 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1396 iowrite32(0, core_base + RAID_SIZE_LOW);
1397 iowrite32(0, core_base + RAID_SIZE_HIGH);
1398 wmb();
1399 break;
1400 case OXNASSATA_RAID0:
1401 /* clear JBOD mode */
1402 reg = ioread32(core_base + DATA_PLANE_CTRL);
1403 reg |= DPC_JBOD_UCODE;
1404 reg &= ~DPC_FIS_SWCH;
1405 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1406 wmb();
1407
1408 /* set the hardware up for RAID-1 */
1409 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1410 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1411 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1412 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1413 iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
1414 iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
1415 wmb();
1416 break;
1417 case OXNASSATA_NOTRAID:
1418 /* enable jbod mode */
1419 reg = ioread32(core_base + DATA_PLANE_CTRL);
1420 reg &= ~DPC_JBOD_UCODE;
1421 reg &= ~DPC_FIS_SWCH;
1422 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1423 wmb();
1424
1425 /* start micro-code processor*/
1426 iowrite32(1, core_base + PROC_START);
1427 break;
1428 default:
1429 reg = ioread32(core_base + DATA_PLANE_CTRL);
1430 reg |= DPC_JBOD_UCODE;
1431 reg &= ~DPC_FIS_SWCH;
1432 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1433 wmb();
1434 break;
1435 }
1436 }
1437 }
1438
1439 /**
1440 * sends a sync-escape if there is a link present
1441 */
1442 static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
1443 {
1444 struct sata_oxnas_port_priv *pd = ap->private_data;
1445 u32 reg;
1446
1447 /* read the SSTATUS register and only send a sync escape if there is a
1448 * link active */
1449 if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
1450 reg = ioread32(pd->port_base + SATA_COMMAND);
1451 reg &= ~SATA_OPCODE_MASK;
1452 reg |= CMD_SYNC_ESCAPE;
1453 iowrite32(reg, pd->port_base + SATA_COMMAND);
1454 }
1455 }
1456
1457 /* clears errors */
1458 static inline void sata_oxnas_clear_CS_error(struct ata_port *ap)
1459 {
1460 struct sata_oxnas_port_priv *pd = ap->private_data;
1461 u32 *base = pd->port_base;
1462 u32 reg;
1463
1464 reg = ioread32(base + SATA_CONTROL);
1465 reg &= SATA_CTL_ERR_MASK;
1466 iowrite32(reg, base + SATA_CONTROL);
1467 }
1468
1469 static inline void sata_oxnas_reset_sgdma(struct ata_port *ap)
1470 {
1471 struct sata_oxnas_port_priv *pd = ap->private_data;
1472
1473 iowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS);
1474 }
1475
1476 static inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert)
1477 {
1478 struct sata_oxnas_port_priv *pd = ap->private_data;
1479 u32 reg;
1480
1481 reg = ioread32(pd->dmactl_base + DMA_CONTROL);
1482 if (assert)
1483 reg |= DMA_CONTROL_RESET;
1484 else
1485 reg &= ~DMA_CONTROL_RESET;
1486
1487 iowrite32(reg, pd->dmactl_base + DMA_CONTROL);
1488 };
1489
1490 /**
1491 * Clears the error caused by the core's registers being accessed when the
1492 * core is busy.
1493 */
1494 static inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap)
1495 {
1496 struct sata_oxnas_port_priv *pd = ap->private_data;
1497 u32 *base = pd->port_base;
1498 u32 reg;
1499
1500 reg = ioread32(base + INT_STATUS);
1501
1502 DPRINTK("ENTER\n");
1503 if (reg & INT_REG_ACCESS_ERR) {
1504 DPRINTK("clearing register access error on port %d\n",
1505 ap->port_no);
1506 iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
1507 }
1508 reg = ioread32(base + INT_STATUS);
1509 if (reg & INT_REG_ACCESS_ERR)
1510 DPRINTK("register access error didn't clear\n");
1511 }
1512
1513 static inline void sata_oxnas_clear_sctl_error(struct ata_port *ap)
1514 {
1515 struct sata_oxnas_port_priv *pd = ap->private_data;
1516 u32 *base = pd->port_base;
1517 u32 reg;
1518
1519 reg = ioread32(base + SATA_CONTROL);
1520 reg |= SCTL_CLR_ERR;
1521 iowrite32(reg, base + SATA_CONTROL);
1522 }
1523
1524 static inline void sata_oxnas_clear_raid_error(struct ata_host *ah)
1525 {
1526 return;
1527 };
1528
1529 /**
1530 * Clean up all the state machines in the sata core.
1531 * @return post cleanup action required
1532 */
1533 static int sata_oxnas_cleanup(struct ata_host *ah)
1534 {
1535 struct sata_oxnas_host_priv *hd = ah->private_data;
1536 int actions_required = 0;
1537 int n;
1538
1539 printk(KERN_INFO "sata_oxnas: resetting SATA core\n");
1540 /* core not recovering, reset it */
1541 mdelay(5);
1542 sata_oxnas_reset_core(ah);
1543 mdelay(5);
1544 actions_required |= OXNAS_SATA_REINIT;
1545 /* Perform any SATA core re-initialisation after reset post reset init
1546 * needs to be called for both ports as there's one reset for both
1547 * ports */
1548 for (n = 0; n < hd->n_ports; n++)
1549 sata_oxnas_post_reset_init(ah->ports[n]);
1550
1551
1552 return actions_required;
1553 }
1554
1555 /**
1556 * ata_qc_new - Request an available ATA command, for queueing
1557 * @ap: Port associated with device @dev
1558 * @return non zero will refuse a new command, zero will may grant on subject
1559 * to conditions elsewhere.
1560 *
1561 */
1562 static int sata_oxnas_qc_new(struct ata_port *ap)
1563 {
1564 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1565
1566 DPRINTK("port %d\n", ap->port_no);
1567 smp_rmb();
1568 if (hd->port_frozen || hd->port_in_eh)
1569 return 1;
1570 else
1571 return !sata_oxnas_acquire_hw(ap, 0, 0);
1572 }
1573
1574 /**
1575 * releases the lock on the port the command used
1576 */
1577 static void sata_oxnas_qc_free(struct ata_queued_cmd *qc)
1578 {
1579 DPRINTK("\n");
1580 sata_oxnas_release_hw(qc->ap);
1581 }
1582
1583 static void sata_oxnas_freeze(struct ata_port *ap)
1584 {
1585 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1586
1587 DPRINTK("\n");
1588 hd->port_frozen |= BIT(ap->port_no);
1589 smp_wmb();
1590 }
1591
1592 static void sata_oxnas_thaw(struct ata_port *ap)
1593 {
1594 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1595
1596 DPRINTK("\n");
1597 hd->port_frozen &= ~BIT(ap->port_no);
1598 smp_wmb();
1599 }
1600
1601 void sata_oxnas_freeze_host(struct ata_port *ap)
1602 {
1603 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1604
1605 DPRINTK("ENTER\n");
1606 hd->port_in_eh |= BIT(ap->port_no);
1607 smp_wmb();
1608 }
1609
1610 void sata_oxnas_thaw_host(struct ata_port *ap)
1611 {
1612 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1613
1614 DPRINTK("ENTER\n");
1615 hd->port_in_eh &= ~BIT(ap->port_no);
1616 smp_wmb();
1617 }
1618
1619 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
1620 {
1621 DPRINTK("ENTER\n");
1622 /* If the core is busy here, make it idle */
1623 if (qc->flags & ATA_QCFLAG_FAILED)
1624 sata_oxnas_cleanup(qc->ap->host);
1625 }
1626
1627
1628 /**
1629 * turn on the interrupts
1630 *
1631 * @param ap Hardware with the registers in
1632 */
1633 static void sata_oxnas_irq_on(struct ata_port *ap)
1634 {
1635 struct sata_oxnas_port_priv *pd = ap->private_data;
1636 u32 mask = (COREINT_END << ap->port_no);
1637
1638 /* Clear pending interrupts */
1639 iowrite32(~0, pd->port_base + INT_CLEAR);
1640 iowrite32(mask, pd->core_base + CORE_INT_STATUS);
1641 wmb();
1642
1643 /* enable End of command interrupt */
1644 iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
1645 iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
1646 }
1647
1648
1649 /** @return true if the port has a cable connected */
1650 int sata_oxnas_check_link(struct ata_port *ap)
1651 {
1652 int reg;
1653
1654 sata_oxnas_scr_read_port(ap, SCR_STATUS, &reg);
1655 /* Check for the cable present indicated by SCR status bit-0 set */
1656 return reg & 0x1;
1657 }
1658
1659 /**
1660 * ata_std_postreset - standard postreset callback
1661 * @link: the target ata_link
1662 * @classes: classes of attached devices
1663 *
1664 * This function is invoked after a successful reset. Note that
1665 * the device might have been reset more than once using
1666 * different reset methods before postreset is invoked.
1667 *
1668 * LOCKING:
1669 * Kernel thread context (may sleep)
1670 */
1671 static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
1672 {
1673 struct ata_port *ap = link->ap;
1674 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1675
1676 unsigned int dev;
1677
1678 DPRINTK("ENTER\n");
1679 ata_std_postreset(link, classes);
1680
1681 /* turn on phy error detection by removing the masks */
1682 sata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003);
1683 if (hd->n_ports > 1)
1684 sata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003);
1685
1686 /* bail out if no device is present */
1687 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1688 DPRINTK("EXIT, no device\n");
1689 return;
1690 }
1691
1692 /* go through all the devices and configure them */
1693 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1694 if (ap->link.device[dev].class == ATA_DEV_ATA)
1695 sata_oxnas_dev_config(&(ap->link.device[dev]));
1696 }
1697
1698 DPRINTK("EXIT\n");
1699 }
1700
1701 /**
1702 * Called to read the hardware registers / DMA buffers, to
1703 * obtain the current set of taskfile register values.
1704 * @param ap hardware with the registers in
1705 * @param tf taskfile to read the registers into
1706 */
1707 static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1708 {
1709 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1710 void __iomem *port_base = port_priv->port_base;
1711 /* read the orb registers */
1712 u32 Orb1 = ioread32(port_base + ORB1);
1713 u32 Orb2 = ioread32(port_base + ORB2);
1714 u32 Orb3 = ioread32(port_base + ORB3);
1715 u32 Orb4 = ioread32(port_base + ORB4);
1716
1717 /* read common 28/48 bit tf parameters */
1718 tf->device = (Orb1 >> 24);
1719 tf->nsect = (Orb2 >> 0);
1720 tf->feature = (Orb2 >> 16);
1721 tf->command = sata_oxnas_check_status(ap);
1722
1723 /* read 48 or 28 bit tf parameters */
1724 if (tf->flags & ATA_TFLAG_LBA48) {
1725 tf->hob_nsect = (Orb2 >> 8);
1726 tf->lbal = (Orb3 >> 0);
1727 tf->lbam = (Orb3 >> 8);
1728 tf->lbah = (Orb3 >> 16);
1729 tf->hob_lbal = (Orb3 >> 24);
1730 tf->hob_lbam = (Orb4 >> 0);
1731 tf->hob_lbah = (Orb4 >> 8);
1732 /* feature ext and control are write only */
1733 } else {
1734 /* read 28-bit lba */
1735 tf->lbal = (Orb3 >> 0);
1736 tf->lbam = (Orb3 >> 8);
1737 tf->lbah = (Orb3 >> 16);
1738 }
1739 }
1740
1741 /**
1742 * Read a result task-file from the sata core registers.
1743 */
1744 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
1745 {
1746 /* Read the most recently received FIS from the SATA core ORB registers
1747 and convert to an ATA taskfile */
1748 sata_oxnas_tf_read(qc->ap, &qc->result_tf);
1749 return true;
1750 }
1751
1752 /**
1753 * Reads the Status ATA shadow register from hardware.
1754 *
1755 * @return The status register
1756 */
1757 static u8 sata_oxnas_check_status(struct ata_port *ap)
1758 {
1759 u32 Reg;
1760 u8 status;
1761 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1762 void __iomem *port_base = port_priv->port_base;
1763
1764 /* read byte 3 of Orb2 register */
1765 status = ioread32(port_base + ORB2) >> 24;
1766
1767 /* check for the drive going missing indicated by SCR status bits
1768 * 0-3 = 0 */
1769 sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
1770
1771 if (!(Reg & 0x1)) {
1772 status |= ATA_DF;
1773 status |= ATA_ERR;
1774 }
1775
1776 return status;
1777 }
1778
1779 static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force,
1780 int no_microcode)
1781 {
1782 struct sata_oxnas_host_priv *hd = ah->private_data;
1783
1784 DPRINTK("ENTER\n");
1785 if (no_microcode) {
1786 u32 reg;
1787
1788 sata_oxnas_set_mode(ah, UNKNOWN_MODE, force);
1789 reg = ioread32(hd->core_base + DEVICE_CONTROL);
1790 reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
1791 iowrite32(reg, hd->core_base + DEVICE_CONTROL);
1792 } else {
1793 /* JBOD uCode */
1794 sata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force);
1795 /* Turn the work around off as it may have been left on by any
1796 * HW-RAID code that we've been working with */
1797 iowrite32(0x0, hd->core_base + PORT_ERROR_MASK);
1798 }
1799 }
1800
1801 /**
1802 * Prepare as much as possible for a command without involving anything that is
1803 * shared between ports.
1804 */
1805 static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
1806 {
1807 struct sata_oxnas_port_priv *pd;
1808 int port_no = qc->ap->port_no;
1809
1810 /* if the port's not connected, complete now with an error */
1811 if (!sata_oxnas_check_link(qc->ap)) {
1812 ata_port_err(qc->ap,
1813 "port %d not connected completing with error\n",
1814 port_no);
1815 qc->err_mask |= AC_ERR_ATA_BUS;
1816 ata_qc_complete(qc);
1817 }
1818
1819 sata_oxnas_reset_ucode(qc->ap->host, 0, 0);
1820
1821 /* both pio and dma commands use dma */
1822 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
1823
1824 /* program the scatterlist into the prd table */
1825 ata_bmdma_qc_prep(qc);
1826
1827 /* point the sgdma controller at the dma request structure */
1828 pd = qc->ap->private_data;
1829
1830 iowrite32(pd->sgdma_request_pa,
1831 pd->sgdma_base + SGDMA_REQUESTPTR);
1832
1833 /* setup the request table */
1834 if (port_no == 0) {
1835 pd->sgdma_request->control =
1836 (qc->dma_dir == DMA_FROM_DEVICE) ?
1837 SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
1838 } else {
1839 pd->sgdma_request->control =
1840 (qc->dma_dir == DMA_FROM_DEVICE) ?
1841 SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
1842 }
1843 pd->sgdma_request->qualifier = SGDMA_REQQUAL;
1844 pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
1845 pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
1846 smp_wmb();
1847
1848 /* tell it to wait */
1849 iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
1850 }
1851 }
1852
1853 static int sata_oxnas_port_start(struct ata_port *ap)
1854 {
1855 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1856 struct device *dev = ap->host->dev;
1857 struct sata_oxnas_port_priv *pp;
1858 void *mem;
1859 dma_addr_t mem_dma;
1860
1861 DPRINTK("ENTER\n");
1862
1863 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
1864 if (!pp)
1865 return -ENOMEM;
1866
1867 pp->port_base = host_priv->port_base +
1868 (ap->port_no ? PORT_SIZE : 0);
1869 pp->dmactl_base = host_priv->dmactl_base +
1870 (ap->port_no ? DMA_CORESIZE : 0);
1871 pp->sgdma_base = host_priv->sgdma_base +
1872 (ap->port_no ? SGDMA_CORESIZE : 0);
1873 pp->core_base = host_priv->core_base;
1874
1875 /* preallocated */
1876 if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) {
1877 DPRINTK("using preallocated DMA\n");
1878 mem_dma = host_priv->dma_base +
1879 (ap->port_no ? SATA_OXNAS_DMA_SIZE : 0);
1880 mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
1881 } else {
1882 mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
1883 GFP_KERNEL);
1884 }
1885 if (!mem)
1886 goto err_ret;
1887
1888 pp->sgdma_request_pa = mem_dma;
1889 pp->sgdma_request = mem;
1890
1891 ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
1892 ap->bmdma_prd = mem + sizeof(struct sgdma_request);
1893
1894 ap->private_data = pp;
1895
1896 sata_oxnas_post_reset_init(ap);
1897
1898 return 0;
1899
1900 err_ret:
1901 kfree(pp);
1902 return -ENOMEM;
1903
1904 }
1905
1906 static void sata_oxnas_port_stop(struct ata_port *ap)
1907 {
1908 struct device *dev = ap->host->dev;
1909 struct sata_oxnas_port_priv *pp = ap->private_data;
1910 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1911
1912 DPRINTK("ENTER\n");
1913 ap->private_data = NULL;
1914 if (host_priv->dma_size) {
1915 iounmap(pp->sgdma_request);
1916 } else {
1917 dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
1918 pp->sgdma_request, pp->sgdma_request_pa);
1919 }
1920
1921 kfree(pp);
1922 }
1923
1924
1925 static void sata_oxnas_post_reset_init(struct ata_port *ap)
1926 {
1927 uint dev;
1928
1929 /* force to load u-code only once after reset */
1930 sata_oxnas_reset_ucode(ap->host, !ap->port_no, 0);
1931
1932 /* turn on phy error detection by removing the masks */
1933 sata_oxnas_link_write(ap, 0x0C, 0x30003);
1934
1935 /* enable hotplug event detection */
1936 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1937 sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
1938 sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
1939
1940 /* enable interrupts for ports */
1941 sata_oxnas_irq_on(ap);
1942
1943 /* go through all the devices and configure them */
1944 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1945 if (ap->link.device[dev].class == ATA_DEV_ATA) {
1946 sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
1947 sata_oxnas_dev_config(&(ap->link.device[dev]));
1948 }
1949 }
1950
1951 /* clean up any remaining errors */
1952 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1953 VPRINTK("done\n");
1954 }
1955
1956 /**
1957 * host_stop() is called when the rmmod or hot unplug process begins. The
1958 * hook must stop all hardware interrupts, DMA engines, etc.
1959 *
1960 * @param ap hardware with the registers in
1961 */
1962 static void sata_oxnas_host_stop(struct ata_host *host_set)
1963 {
1964 DPRINTK("\n");
1965 }
1966
1967
1968 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1969 static void sata_oxnas_error_handler(struct ata_port *ap)
1970 {
1971 DPRINTK("Enter port_no %d\n", ap->port_no);
1972 sata_oxnas_freeze_host(ap);
1973
1974 /* If the core is busy here, make it idle */
1975 sata_oxnas_cleanup(ap->host);
1976
1977 ata_std_error_handler(ap);
1978
1979 sata_oxnas_thaw_host(ap);
1980 }
1981
1982 static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
1983 unsigned long deadline)
1984 {
1985 struct ata_port *ap = link->ap;
1986 struct sata_oxnas_port_priv *pd = ap->private_data;
1987 void __iomem *port_base = pd->port_base;
1988 int rc;
1989
1990 struct ata_taskfile tf;
1991 u32 Command_Reg;
1992
1993 DPRINTK("ENTER\n");
1994
1995 port_base = pd->port_base;
1996
1997 if (ata_link_offline(link)) {
1998 DPRINTK("PHY reports no device\n");
1999 *class = ATA_DEV_NONE;
2000 goto out;
2001 }
2002
2003 /* write value to register */
2004 iowrite32(0, port_base + ORB1);
2005 iowrite32(0, port_base + ORB2);
2006 iowrite32(0, port_base + ORB3);
2007 iowrite32((ap->ctl) << 24, port_base + ORB4);
2008
2009 /* command the core to send a control FIS */
2010 Command_Reg = ioread32(port_base + SATA_COMMAND);
2011 Command_Reg &= ~SATA_OPCODE_MASK;
2012 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
2013 iowrite32(Command_Reg, port_base + SATA_COMMAND);
2014 udelay(20); /* FIXME: flush */
2015
2016 /* write value to register */
2017 iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
2018
2019 /* command the core to send a control FIS */
2020 Command_Reg &= ~SATA_OPCODE_MASK;
2021 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
2022 iowrite32(Command_Reg, port_base + SATA_COMMAND);
2023 udelay(20); /* FIXME: flush */
2024
2025 /* write value to register */
2026 iowrite32((ap->ctl) << 24, port_base + ORB4);
2027
2028 /* command the core to send a control FIS */
2029 Command_Reg &= ~SATA_OPCODE_MASK;
2030 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
2031 iowrite32(Command_Reg, port_base + SATA_COMMAND);
2032
2033 msleep(150);
2034
2035 rc = ata_sff_wait_ready(link, deadline);
2036
2037 /* if link is occupied, -ENODEV too is an error */
2038 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2039 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
2040 return rc;
2041 }
2042
2043 /* determine by signature whether we have ATA or ATAPI devices */
2044 sata_oxnas_tf_read(ap, &tf);
2045 *class = ata_dev_classify(&tf);
2046
2047 if (*class == ATA_DEV_UNKNOWN)
2048 *class = ATA_DEV_NONE;
2049
2050 out:
2051 DPRINTK("EXIT, class=%u\n", *class);
2052 return 0;
2053 }
2054
2055
2056 int sata_oxnas_init_controller(struct ata_host *host)
2057 {
2058 return 0;
2059 }
2060
2061 /**
2062 * Ref bug-6320
2063 *
2064 * This code is a work around for a DMA hardware bug that will repeat the
2065 * penultimate 8-bytes on some reads. This code will check that the amount
2066 * of data transferred is a multiple of 512 bytes, if not the in it will
2067 * fetch the correct data from a buffer in the SATA core and copy it into
2068 * memory.
2069 *
2070 * @param port SATA port to check and if necessary, correct.
2071 */
2072 static int sata_oxnas_bug_6320_detect(struct ata_port *ap)
2073 {
2074 struct sata_oxnas_port_priv *pd = ap->private_data;
2075 void __iomem *core_base = pd->core_base;
2076 int is_read;
2077 int quads_transferred;
2078 int remainder;
2079 int sector_quads_remaining;
2080 int bug_present = 0;
2081
2082 /* Only want to apply fix to reads */
2083 is_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ?
2084 BIT(CORE_PORT1_DATA_DIR_BIT) :
2085 BIT(CORE_PORT0_DATA_DIR_BIT)));
2086
2087 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
2088 transferred (datacount_port register counts quads transferred) */
2089 quads_transferred =
2090 ioread32(core_base + (ap->port_no ?
2091 DATACOUNT_PORT1 : DATACOUNT_PORT0));
2092
2093 remainder = quads_transferred & 0x7f;
2094 sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
2095
2096 if (is_read && (sector_quads_remaining == 2)) {
2097 bug_present = 1;
2098 } else if (sector_quads_remaining) {
2099 if (is_read) {
2100 ata_port_warn(ap, "SATA read fixup cannot deal with "
2101 "%d quads remaining\n",
2102 sector_quads_remaining);
2103 } else {
2104 ata_port_warn(ap, "SATA write fixup of %d quads "
2105 "remaining not supported\n",
2106 sector_quads_remaining);
2107 }
2108 }
2109
2110 return bug_present;
2111 }
2112
2113 /* This port done an interrupt */
2114 static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
2115 {
2116 struct ata_queued_cmd *qc;
2117 struct sata_oxnas_port_priv *pd = ap->private_data;
2118 void __iomem *port_base = pd->port_base;
2119
2120 u32 int_status;
2121 unsigned long flags = 0;
2122
2123 DPRINTK("ENTER port %d irqstatus %x\n", ap->port_no,
2124 ioread32(port_base + INT_STATUS));
2125
2126 if (ap->qc_active & (1 << ATA_TAG_INTERNAL)) {
2127 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
2128 DPRINTK("completing non-ncq cmd\n");
2129
2130 if (qc)
2131 ata_qc_complete(qc);
2132
2133 return;
2134 }
2135
2136 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2137
2138
2139 /* record the port's interrupt */
2140 int_status = ioread32(port_base + INT_STATUS);
2141
2142 /* If there's no command associated with this IRQ, ignore it. We may get
2143 * spurious interrupts when cleaning-up after a failed command, ignore
2144 * these too. */
2145 if (likely(qc)) {
2146 /* get the status before any error cleanup */
2147 qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
2148 if (force_error) {
2149 /* Pretend there has been a link error */
2150 qc->err_mask |= AC_ERR_ATA_BUS;
2151 DPRINTK(" ####force error####\n");
2152 }
2153 /* tell libata we're done */
2154 local_irq_save(flags);
2155 sata_oxnas_irq_clear(ap);
2156 local_irq_restore(flags);
2157 ata_qc_complete(qc);
2158 } else {
2159 VPRINTK("Ignoring interrupt, can't find the command tag="
2160 "%d %08x\n", ap->link.active_tag, ap->qc_active);
2161 }
2162
2163 /* maybe a hotplug event */
2164 if (unlikely(int_status & INT_LINK_SERROR)) {
2165 u32 serror;
2166
2167 sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
2168 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
2169 ata_ehi_hotplugged(&ap->link.eh_info);
2170 ata_port_freeze(ap);
2171 }
2172 }
2173 }
2174
2175 /**
2176 * irq_handler is the interrupt handling routine registered with the system,
2177 * by libata.
2178 */
2179 static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
2180 {
2181 struct ata_host *ah = dev_instance;
2182 struct sata_oxnas_host_priv *hd = ah->private_data;
2183 void __iomem *core_base = hd->core_base;
2184
2185 u32 int_status;
2186 irqreturn_t ret = IRQ_NONE;
2187 u32 port_no;
2188 u32 mask;
2189 int bug_present;
2190
2191 /* loop until there are no more interrupts */
2192 while ((int_status = (ioread32(core_base + CORE_INT_STATUS)) &
2193 (COREINT_END | (COREINT_END << 1)))) {
2194
2195 /* clear any interrupt */
2196 iowrite32(int_status, core_base + CORE_INT_CLEAR);
2197
2198 /* Only need workaround_bug_6320 for single disk systems as dual
2199 * disk will use uCode which prevents this read underrun problem
2200 * from occurring.
2201 * All single disk systems will use port 0 */
2202 for (port_no = 0; port_no < hd->n_ports; ++port_no) {
2203 /* check the raw end of command interrupt to see if the
2204 * port is done */
2205 mask = (COREINT_END << port_no);
2206 if (!(int_status & mask))
2207 continue;
2208
2209 /* this port had an interrupt, clear it */
2210 iowrite32(mask, core_base + CORE_INT_CLEAR);
2211 /* check for bug 6320 only if no microcode was loaded */
2212 bug_present = (hd->current_ucode == UNKNOWN_MODE) &&
2213 sata_oxnas_bug_6320_detect(ah->ports[port_no]);
2214
2215 sata_oxnas_port_irq(ah->ports[port_no],
2216 bug_present);
2217 ret = IRQ_HANDLED;
2218 }
2219 }
2220
2221 return ret;
2222 }
2223
2224 /*
2225 * scsi mid-layer and libata interface structures
2226 */
2227 static struct scsi_host_template sata_oxnas_sht = {
2228 ATA_NCQ_SHT("sata_oxnas"),
2229 .can_queue = SATA_OXNAS_QUEUE_DEPTH,
2230 .sg_tablesize = SATA_OXNAS_MAX_PRD,
2231 .dma_boundary = ATA_DMA_BOUNDARY,
2232 .unchecked_isa_dma = 0,
2233 };
2234
2235
2236 static struct ata_port_operations sata_oxnas_ops = {
2237 .inherits = &sata_port_ops,
2238 .qc_prep = sata_oxnas_qc_prep,
2239 .qc_issue = sata_oxnas_qc_issue,
2240 .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
2241 .qc_new = sata_oxnas_qc_new,
2242 .qc_free = sata_oxnas_qc_free,
2243
2244 .scr_read = sata_oxnas_scr_read,
2245 .scr_write = sata_oxnas_scr_write,
2246
2247 .freeze = sata_oxnas_freeze,
2248 .thaw = sata_oxnas_thaw,
2249 .softreset = sata_oxnas_softreset,
2250 /* .hardreset = sata_oxnas_hardreset, */
2251 .postreset = sata_oxnas_postreset,
2252 .error_handler = sata_oxnas_error_handler,
2253 .post_internal_cmd = sata_oxnas_post_internal_cmd,
2254
2255 .port_start = sata_oxnas_port_start,
2256 .port_stop = sata_oxnas_port_stop,
2257
2258 .host_stop = sata_oxnas_host_stop,
2259 /* .pmp_attach = sata_oxnas_pmp_attach, */
2260 /* .pmp_detach = sata_oxnas_pmp_detach, */
2261 .sff_check_status = sata_oxnas_check_status,
2262 .acquire_hw = sata_oxnas_acquire_hw,
2263 };
2264
2265 static const struct ata_port_info sata_oxnas_port_info = {
2266 .flags = SATA_OXNAS_HOST_FLAGS,
2267 .pio_mask = ATA_PIO4,
2268 .udma_mask = ATA_UDMA6,
2269 .port_ops = &sata_oxnas_ops,
2270 };
2271
2272 static int sata_oxnas_probe(struct platform_device *ofdev)
2273 {
2274 int retval = -ENXIO;
2275 int n_ports = 0;
2276 void __iomem *port_base = NULL;
2277 void __iomem *dmactl_base = NULL;
2278 void __iomem *sgdma_base = NULL;
2279 void __iomem *core_base = NULL;
2280 void __iomem *phy_base = NULL;
2281 struct reset_control *rstc;
2282
2283 struct resource res = {};
2284 struct sata_oxnas_host_priv *host_priv = NULL;
2285 int irq = 0;
2286 struct ata_host *host = NULL;
2287 struct clk *clk = NULL;
2288
2289 const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
2290
2291 of_property_read_u32(ofdev->dev.of_node, "nr-ports", &n_ports);
2292 if (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS)
2293 goto error_exit_with_cleanup;
2294
2295 port_base = of_iomap(ofdev->dev.of_node, 0);
2296 if (!port_base)
2297 goto error_exit_with_cleanup;
2298
2299 dmactl_base = of_iomap(ofdev->dev.of_node, 1);
2300 if (!dmactl_base)
2301 goto error_exit_with_cleanup;
2302
2303 sgdma_base = of_iomap(ofdev->dev.of_node, 2);
2304 if (!sgdma_base)
2305 goto error_exit_with_cleanup;
2306
2307 core_base = of_iomap(ofdev->dev.of_node, 3);
2308 if (!core_base)
2309 goto error_exit_with_cleanup;
2310
2311 phy_base = of_iomap(ofdev->dev.of_node, 4);
2312 if (!phy_base)
2313 goto error_exit_with_cleanup;
2314
2315 host_priv = devm_kzalloc(&ofdev->dev,
2316 sizeof(struct sata_oxnas_host_priv),
2317 GFP_KERNEL);
2318 if (!host_priv)
2319 goto error_exit_with_cleanup;
2320
2321 host_priv->port_base = port_base;
2322 host_priv->dmactl_base = dmactl_base;
2323 host_priv->sgdma_base = sgdma_base;
2324 host_priv->core_base = core_base;
2325 host_priv->phy_base = phy_base;
2326 host_priv->n_ports = n_ports;
2327 host_priv->current_ucode = UNKNOWN_MODE;
2328
2329 if (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) {
2330 host_priv->dma_base = res.start;
2331 host_priv->dma_size = resource_size(&res);
2332 }
2333
2334 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
2335 if (!irq) {
2336 dev_err(&ofdev->dev, "invalid irq from platform\n");
2337 goto error_exit_with_cleanup;
2338 }
2339 host_priv->irq = irq;
2340
2341 clk = of_clk_get(ofdev->dev.of_node, 0);
2342 if (IS_ERR(clk)) {
2343 retval = PTR_ERR(clk);
2344 clk = NULL;
2345 goto error_exit_with_cleanup;
2346 }
2347 host_priv->clk = clk;
2348
2349 rstc = devm_reset_control_get(&ofdev->dev, "sata");
2350 if (IS_ERR(rstc)) {
2351 retval = PTR_ERR(rstc);
2352 goto error_exit_with_cleanup;
2353 }
2354 host_priv->rst_sata = rstc;
2355
2356 rstc = devm_reset_control_get(&ofdev->dev, "link");
2357 if (IS_ERR(rstc)) {
2358 retval = PTR_ERR(rstc);
2359 goto error_exit_with_cleanup;
2360 }
2361 host_priv->rst_link = rstc;
2362
2363 rstc = devm_reset_control_get(&ofdev->dev, "phy");
2364 if (IS_ERR(rstc)) {
2365 retval = PTR_ERR(rstc);
2366 goto error_exit_with_cleanup;
2367 }
2368 host_priv->rst_phy = rstc;
2369
2370 /* allocate host structure */
2371 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, n_ports);
2372
2373 if (!host) {
2374 retval = -ENOMEM;
2375 goto error_exit_with_cleanup;
2376 }
2377 host->private_data = host_priv;
2378 host->iomap = port_base;
2379
2380 /* initialize core locking and queues */
2381 init_waitqueue_head(&host_priv->fast_wait_queue);
2382 init_waitqueue_head(&host_priv->scsi_wait_queue);
2383 spin_lock_init(&host_priv->phy_lock);
2384 spin_lock_init(&host_priv->core_lock);
2385 host_priv->core_locked = 0;
2386 host_priv->reentrant_port_no = -1;
2387 host_priv->hw_lock_count = 0;
2388 host_priv->direct_lock_count = 0;
2389 host_priv->locker_uid = 0;
2390 host_priv->current_locker_type = SATA_UNLOCKED;
2391 host_priv->isr_arg = NULL;
2392 host_priv->isr_callback = NULL;
2393
2394 /* initialize host controller */
2395 retval = sata_oxnas_init_controller(host);
2396 if (retval)
2397 goto error_exit_with_cleanup;
2398
2399 /*
2400 * Now, register with libATA core, this will also initiate the
2401 * device discovery process, invoking our port_start() handler &
2402 * error_handler() to execute a dummy softreset EH session
2403 */
2404 ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
2405 &sata_oxnas_sht);
2406
2407 return 0;
2408
2409 error_exit_with_cleanup:
2410 if (irq)
2411 irq_dispose_mapping(host_priv->irq);
2412 if (clk)
2413 clk_put(clk);
2414 if (host)
2415 ata_host_detach(host);
2416 if (port_base)
2417 iounmap(port_base);
2418 if (sgdma_base)
2419 iounmap(sgdma_base);
2420 if (core_base)
2421 iounmap(core_base);
2422 if (phy_base)
2423 iounmap(phy_base);
2424 return retval;
2425 }
2426
2427
2428 static int sata_oxnas_remove(struct platform_device *ofdev)
2429 {
2430 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
2431 struct sata_oxnas_host_priv *host_priv = host->private_data;
2432
2433 ata_host_detach(host);
2434
2435 irq_dispose_mapping(host_priv->irq);
2436 iounmap(host_priv->port_base);
2437 iounmap(host_priv->sgdma_base);
2438 iounmap(host_priv->core_base);
2439
2440 /* reset Controller, Link and PHY */
2441 reset_control_assert(host_priv->rst_sata);
2442 reset_control_assert(host_priv->rst_link);
2443 reset_control_assert(host_priv->rst_phy);
2444
2445 /* Disable the clock to the SATA block */
2446 clk_disable_unprepare(host_priv->clk);
2447 clk_put(host_priv->clk);
2448
2449 return 0;
2450 }
2451
2452 #ifdef CONFIG_PM
2453 static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
2454 {
2455 struct ata_host *host = dev_get_drvdata(&op->dev);
2456
2457 return ata_host_suspend(host, state);
2458 }
2459
2460 static int sata_oxnas_resume(struct platform_device *op)
2461 {
2462 struct ata_host *host = dev_get_drvdata(&op->dev);
2463 int ret;
2464
2465 ret = sata_oxnas_init_controller(host);
2466 if (ret) {
2467 dev_err(&op->dev, "Error initializing hardware\n");
2468 return ret;
2469 }
2470 ata_host_resume(host);
2471 return 0;
2472 }
2473 #endif
2474
2475
2476
2477 static struct of_device_id oxnas_sata_match[] = {
2478 {
2479 .compatible = "plxtech,nas782x-sata",
2480 },
2481 {},
2482 };
2483
2484 MODULE_DEVICE_TABLE(of, oxnas_sata_match);
2485
2486 static struct platform_driver oxnas_sata_driver = {
2487 .driver = {
2488 .name = "oxnas-sata",
2489 .owner = THIS_MODULE,
2490 .of_match_table = oxnas_sata_match,
2491 },
2492 .probe = sata_oxnas_probe,
2493 .remove = sata_oxnas_remove,
2494 #ifdef CONFIG_PM
2495 .suspend = sata_oxnas_suspend,
2496 .resume = sata_oxnas_resume,
2497 #endif
2498 };
2499
2500 module_platform_driver(oxnas_sata_driver);
2501
2502 MODULE_LICENSE("GPL");
2503 MODULE_VERSION("1.0");
2504 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
2505 MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core");
OpenWrt Source Repository