kernel: bump 4.14 to 4.14.50 for 18.06
[openwrt/openwrt.git] / target / linux / oxnas / files / drivers / clk / clk-oxnas.c
1 /*
2 * Copyright (C) 2010 Broadcom
3 * Copyright (C) 2012 Stephen Warren
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #include <linux/clk.h>
19 #include <linux/clkdev.h>
20 #include <linux/clk-provider.h>
21 #include <linux/of.h>
22 #include <linux/delay.h>
23 #include <linux/stringify.h>
24 #include <linux/reset.h>
25 #include <linux/io.h>
26 #include <mach/hardware.h>
27 #include <mach/utils.h>
28
29 #define MHZ (1000 * 1000)
30
31 struct clk_oxnas_pllb {
32 struct clk_hw hw;
33 struct device_node *devnode;
34 struct reset_control *rstc;
35 };
36
37 #define to_clk_oxnas_pllb(_hw) container_of(_hw, struct clk_oxnas_pllb, hw)
38
39 static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
40 unsigned long parent_rate)
41 {
42 unsigned long fin = parent_rate;
43 unsigned long pll0;
44 unsigned long fbdiv, refdiv, outdiv;
45
46 pll0 = readl_relaxed(SYS_CTRL_PLLA_CTRL0);
47 refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
48 refdiv += 1;
49 outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
50 outdiv += 1;
51 fbdiv = readl_relaxed(SYS_CTRL_PLLA_CTRL1);
52
53 /* seems we will not be here when pll is bypassed, so ignore this
54 * case */
55
56 return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
57 }
58
59 static const char *pll_clk_parents[] = {
60 "oscillator",
61 };
62
63 static struct clk_ops plla_ops = {
64 .recalc_rate = plla_clk_recalc_rate,
65 };
66
67 static struct clk_init_data clk_plla_init = {
68 .name = "plla",
69 .ops = &plla_ops,
70 .parent_names = pll_clk_parents,
71 .num_parents = ARRAY_SIZE(pll_clk_parents),
72 };
73
74 static struct clk_hw plla_hw = {
75 .init = &clk_plla_init,
76 };
77
78 static int pllb_clk_is_prepared(struct clk_hw *hw)
79 {
80 struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
81
82 return !!pllb->rstc;
83 }
84
85 static int pllb_clk_prepare(struct clk_hw *hw)
86 {
87 struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
88
89 pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
90
91 return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
92 }
93
94 static void pllb_clk_unprepare(struct clk_hw *hw)
95 {
96 struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
97
98 BUG_ON(IS_ERR(pllb->rstc));
99
100 reset_control_put(pllb->rstc);
101 pllb->rstc = NULL;
102 }
103
104 static int pllb_clk_enable(struct clk_hw *hw)
105 {
106 struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
107
108 BUG_ON(IS_ERR(pllb->rstc));
109
110 /* put PLL into bypass */
111 oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
112 wmb();
113 udelay(10);
114 reset_control_assert(pllb->rstc);
115 udelay(10);
116 /* set PLL B control information */
117 writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
118 SEC_CTRL_PLLB_CTRL0);
119 reset_control_deassert(pllb->rstc);
120 udelay(100);
121 oxnas_register_clear_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
122
123 return 0;
124 }
125
126 static void pllb_clk_disable(struct clk_hw *hw)
127 {
128 struct clk_oxnas_pllb *pllb = to_clk_oxnas_pllb(hw);
129
130 BUG_ON(IS_ERR(pllb->rstc));
131
132 /* put PLL into bypass */
133 oxnas_register_set_mask(SEC_CTRL_PLLB_CTRL0, BIT(PLLB_BYPASS));
134 wmb();
135 udelay(10);
136
137 reset_control_assert(pllb->rstc);
138 }
139
140 static struct clk_ops pllb_ops = {
141 .prepare = pllb_clk_prepare,
142 .unprepare = pllb_clk_unprepare,
143 .is_prepared = pllb_clk_is_prepared,
144 .enable = pllb_clk_enable,
145 .disable = pllb_clk_disable,
146 };
147
148 static struct clk_init_data clk_pllb_init = {
149 .name = "pllb",
150 .ops = &pllb_ops,
151 .parent_names = pll_clk_parents,
152 .num_parents = ARRAY_SIZE(pll_clk_parents),
153 };
154
155
156 /* standard gate clock */
157 struct clk_std {
158 struct clk_hw hw;
159 signed char bit;
160 };
161
162 #define NUM_STD_CLKS 17
163 #define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
164
165 static int std_clk_is_enabled(struct clk_hw *hw)
166 {
167 struct clk_std *std = to_stdclk(hw);
168
169 return readl_relaxed(SYSCTRL_CLK_STAT) & BIT(std->bit);
170 }
171
172 static int std_clk_enable(struct clk_hw *hw)
173 {
174 struct clk_std *std = to_stdclk(hw);
175
176 writel(BIT(std->bit), SYS_CTRL_CLK_SET_CTRL);
177 return 0;
178 }
179
180 static void std_clk_disable(struct clk_hw *hw)
181 {
182 struct clk_std *std = to_stdclk(hw);
183
184 writel(BIT(std->bit), SYS_CTRL_CLK_CLR_CTRL);
185 }
186
187 static struct clk_ops std_clk_ops = {
188 .enable = std_clk_enable,
189 .disable = std_clk_disable,
190 .is_enabled = std_clk_is_enabled,
191 };
192
193 static const char *std_clk_parents[] = {
194 "oscillator",
195 };
196
197 static const char *eth_parents[] = {
198 "gmacclk",
199 };
200
201 #define DECLARE_STD_CLKP(__clk, __bit, __parent) \
202 static struct clk_init_data clk_##__clk##_init = { \
203 .name = __stringify(__clk), \
204 .ops = &std_clk_ops, \
205 .parent_names = __parent, \
206 .num_parents = ARRAY_SIZE(__parent), \
207 }; \
208 \
209 static struct clk_std clk_##__clk = { \
210 .bit = __bit, \
211 .hw = { \
212 .init = &clk_##__clk##_init, \
213 }, \
214 }
215
216 #define DECLARE_STD_CLK(__clk, __bit) DECLARE_STD_CLKP(__clk, __bit, \
217 std_clk_parents)
218
219 DECLARE_STD_CLK(leon, 0);
220 DECLARE_STD_CLK(dma_sgdma, 1);
221 DECLARE_STD_CLK(cipher, 2);
222 DECLARE_STD_CLK(sd, 3);
223 DECLARE_STD_CLK(sata, 4);
224 DECLARE_STD_CLK(audio, 5);
225 DECLARE_STD_CLK(usbmph, 6);
226 DECLARE_STD_CLKP(etha, 7, eth_parents);
227 DECLARE_STD_CLK(pciea, 8);
228 DECLARE_STD_CLK(static, 9);
229 DECLARE_STD_CLK(ethb, 10);
230 DECLARE_STD_CLK(pcieb, 11);
231 DECLARE_STD_CLK(ref600, 12);
232 DECLARE_STD_CLK(usbdev, 13);
233
234 struct clk_hw *std_clk_hw_tbl[] = {
235 &clk_leon.hw,
236 &clk_dma_sgdma.hw,
237 &clk_cipher.hw,
238 &clk_sd.hw,
239 &clk_sata.hw,
240 &clk_audio.hw,
241 &clk_usbmph.hw,
242 &clk_etha.hw,
243 &clk_pciea.hw,
244 &clk_static.hw,
245 &clk_ethb.hw,
246 &clk_pcieb.hw,
247 &clk_ref600.hw,
248 &clk_usbdev.hw,
249 };
250
251 struct clk *std_clk_tbl[ARRAY_SIZE(std_clk_hw_tbl)];
252
253 static struct clk_onecell_data std_clk_data;
254
255 void __init oxnas_init_stdclk(struct device_node *np)
256 {
257 int i;
258
259 for (i = 0; i < ARRAY_SIZE(std_clk_hw_tbl); i++) {
260 std_clk_tbl[i] = clk_register(NULL, std_clk_hw_tbl[i]);
261 BUG_ON(IS_ERR(std_clk_tbl[i]));
262 }
263 std_clk_data.clks = std_clk_tbl;
264 std_clk_data.clk_num = ARRAY_SIZE(std_clk_tbl);
265 of_clk_add_provider(np, of_clk_src_onecell_get, &std_clk_data);
266 }
267 CLK_OF_DECLARE(oxnas_pllstd, "plxtech,nas782x-stdclk", oxnas_init_stdclk);
268
269 void __init oxnas_init_plla(struct device_node *np)
270 {
271 struct clk *clk;
272
273 clk = clk_register(NULL, &plla_hw);
274 BUG_ON(IS_ERR(clk));
275 /* mark it as enabled */
276 clk_prepare_enable(clk);
277 of_clk_add_provider(np, of_clk_src_simple_get, clk);
278 }
279 CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
280
281 void __init oxnas_init_pllb(struct device_node *np)
282 {
283 struct clk *clk;
284 struct clk_oxnas_pllb *pllb;
285
286 pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
287 BUG_ON(!pllb);
288
289 pllb->hw.init = &clk_pllb_init;
290 pllb->devnode = np;
291 pllb->rstc = NULL;
292
293 clk = clk_register(NULL, &pllb->hw);
294 BUG_ON(IS_ERR(clk));
295 of_clk_add_provider(np, of_clk_src_simple_get, clk);
296 }
297 CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);