6cc8f72c604c224620f8b64deb82f02026f6dfc0
[openwrt/openwrt.git] / target / linux / oxnas / files / drivers / pinctrl / pinctrl-oxnas.c
1 /*
2 * oxnas pinctrl driver based on at91 pinctrl driver
3 *
4 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Under GPLv2 only
7 */
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/version.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/slab.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/irqdomain.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28 /* Since we request GPIOs from ourself */
29 #include <linux/pinctrl/consumer.h>
30
31 #include "core.h"
32
33 #include <mach/utils.h>
34
35 #define MAX_NB_GPIO_PER_BANK 32
36 #define MAX_GPIO_BANKS 2
37
38 struct oxnas_gpio_chip {
39 struct gpio_chip chip;
40 struct pinctrl_gpio_range range;
41 void __iomem *regbase; /* GPIOA/B virtual address */
42 void __iomem *ctrlbase; /* SYS/SEC_CTRL virtual address */
43 struct irq_domain *domain; /* associated irq domain */
44 };
45
46 #define to_oxnas_gpio_chip(c) container_of(c, struct oxnas_gpio_chip, chip)
47
48 static struct oxnas_gpio_chip *gpio_chips[MAX_GPIO_BANKS];
49
50 static int gpio_banks;
51
52 #define PULL_UP (1 << 0)
53 #define PULL_DOWN (1 << 1)
54 #define DEBOUNCE (1 << 2)
55
56 /**
57 * struct oxnas_pmx_func - describes pinmux functions
58 * @name: the name of this specific function
59 * @groups: corresponding pin groups
60 * @ngroups: the number of groups
61 */
62 struct oxnas_pmx_func {
63 const char *name;
64 const char **groups;
65 unsigned ngroups;
66 };
67
68 enum oxnas_mux {
69 OXNAS_PINMUX_GPIO,
70 OXNAS_PINMUX_FUNC2,
71 OXNAS_PINMUX_FUNC3,
72 OXNAS_PINMUX_FUNC4,
73 OXNAS_PINMUX_DEBUG,
74 OXNAS_PINMUX_ALT,
75 };
76
77 enum {
78 INPUT_VALUE = 0,
79 OUTPUT_ENABLE = 4,
80 IRQ_PENDING = 0xC,
81 OUTPUT_VALUE = 0x10,
82 OUTPUT_SET = 0x14,
83 OUTPUT_CLEAR = 0x18,
84 OUTPUT_EN_SET = 0x1C,
85 OUTPUT_EN_CLEAR = 0x20,
86 DEBOUNCE_ENABLE = 0x24,
87 RE_IRQ_ENABLE = 0x28, /* rising edge */
88 FE_IRQ_ENABLE = 0x2C, /* falling edge */
89 RE_IRQ_PENDING = 0x30, /* rising edge */
90 FE_IRQ_PENDING = 0x34, /* falling edge */
91 CLOCK_DIV = 0x48,
92 PULL_ENABLE = 0x50,
93 PULL_SENSE = 0x54, /* 1 up, 0 down */
94
95
96 DEBOUNCE_MASK = 0x3FFF0000,
97 /* put hw debounce and soft config at same bit position*/
98 DEBOUNCE_SHIFT = 16
99 };
100
101 enum {
102 PINMUX_SECONDARY_SEL = 0x14,
103 PINMUX_TERTIARY_SEL = 0x8c,
104 PINMUX_QUATERNARY_SEL = 0x94,
105 PINMUX_DEBUG_SEL = 0x9c,
106 PINMUX_ALTERNATIVE_SEL = 0xa4,
107 PINMUX_PULLUP_SEL = 0xac,
108 };
109
110 /**
111 * struct oxnas_pmx_pin - describes an pin mux
112 * @bank: the bank of the pin
113 * @pin: the pin number in the @bank
114 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
115 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
116 */
117 struct oxnas_pmx_pin {
118 uint32_t bank;
119 uint32_t pin;
120 enum oxnas_mux mux;
121 unsigned long conf;
122 };
123
124 /**
125 * struct oxnas_pin_group - describes an pin group
126 * @name: the name of this specific pin group
127 * @pins_conf: the mux mode for each pin in this group. The size of this
128 * array is the same as pins.
129 * @pins: an array of discrete physical pins used in this group, taken
130 * from the driver-local pin enumeration space
131 * @npins: the number of pins in this group array, i.e. the number of
132 * elements in .pins so we can iterate over that array
133 */
134 struct oxnas_pin_group {
135 const char *name;
136 struct oxnas_pmx_pin *pins_conf;
137 unsigned int *pins;
138 unsigned npins;
139 };
140
141 struct oxnas_pinctrl {
142 struct device *dev;
143 struct pinctrl_dev *pctl;
144
145 int nbanks;
146
147 uint32_t *mux_mask;
148 int nmux;
149
150 struct oxnas_pmx_func *functions;
151 int nfunctions;
152
153 struct oxnas_pin_group *groups;
154 int ngroups;
155 };
156
157 static const inline struct oxnas_pin_group *oxnas_pinctrl_find_group_by_name(
158 const struct oxnas_pinctrl *info,
159 const char *name)
160 {
161 const struct oxnas_pin_group *grp = NULL;
162 int i;
163
164 for (i = 0; i < info->ngroups; i++) {
165 if (strcmp(info->groups[i].name, name))
166 continue;
167
168 grp = &info->groups[i];
169 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins,
170 grp->pins[0]);
171 break;
172 }
173
174 return grp;
175 }
176
177 static int oxnas_get_groups_count(struct pinctrl_dev *pctldev)
178 {
179 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
180
181 return info->ngroups;
182 }
183
184 static const char *oxnas_get_group_name(struct pinctrl_dev *pctldev,
185 unsigned selector)
186 {
187 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
188
189 return info->groups[selector].name;
190 }
191
192 static int oxnas_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
193 const unsigned **pins,
194 unsigned *npins)
195 {
196 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
197
198 if (selector >= info->ngroups)
199 return -EINVAL;
200
201 *pins = info->groups[selector].pins;
202 *npins = info->groups[selector].npins;
203
204 return 0;
205 }
206
207 static void oxnas_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
208 unsigned offset)
209 {
210 seq_printf(s, "%s", dev_name(pctldev->dev));
211 }
212
213 static int oxnas_dt_node_to_map(struct pinctrl_dev *pctldev,
214 struct device_node *np,
215 struct pinctrl_map **map, unsigned *num_maps)
216 {
217 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
218 const struct oxnas_pin_group *grp;
219 struct pinctrl_map *new_map;
220 struct device_node *parent;
221 int map_num = 1;
222 int i;
223
224 /*
225 * first find the group of this node and check if we need create
226 * config maps for pins
227 */
228 grp = oxnas_pinctrl_find_group_by_name(info, np->name);
229 if (!grp) {
230 dev_err(info->dev, "unable to find group for node %s\n",
231 np->name);
232 return -EINVAL;
233 }
234
235 map_num += grp->npins;
236 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
237 GFP_KERNEL);
238 if (!new_map)
239 return -ENOMEM;
240
241 *map = new_map;
242 *num_maps = map_num;
243
244 /* create mux map */
245 parent = of_get_parent(np);
246 if (!parent) {
247 devm_kfree(pctldev->dev, new_map);
248 return -EINVAL;
249 }
250 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
251 new_map[0].data.mux.function = parent->name;
252 new_map[0].data.mux.group = np->name;
253 of_node_put(parent);
254
255 /* create config map */
256 new_map++;
257 for (i = 0; i < grp->npins; i++) {
258 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
259 new_map[i].data.configs.group_or_pin =
260 pin_get_name(pctldev, grp->pins[i]);
261 new_map[i].data.configs.configs = &grp->pins_conf[i].conf;
262 new_map[i].data.configs.num_configs = 1;
263 }
264
265 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
266 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
267
268 return 0;
269 }
270
271 static void oxnas_dt_free_map(struct pinctrl_dev *pctldev,
272 struct pinctrl_map *map, unsigned num_maps)
273 {
274 }
275
276 static const struct pinctrl_ops oxnas_pctrl_ops = {
277 .get_groups_count = oxnas_get_groups_count,
278 .get_group_name = oxnas_get_group_name,
279 .get_group_pins = oxnas_get_group_pins,
280 .pin_dbg_show = oxnas_pin_dbg_show,
281 .dt_node_to_map = oxnas_dt_node_to_map,
282 .dt_free_map = oxnas_dt_free_map,
283 };
284
285 static void __iomem *pin_to_gpioctrl(struct oxnas_pinctrl *info,
286 unsigned int bank)
287 {
288 return gpio_chips[bank]->regbase;
289 }
290
291 static void __iomem *pin_to_muxctrl(struct oxnas_pinctrl *info,
292 unsigned int bank)
293 {
294 return gpio_chips[bank]->ctrlbase;
295 }
296
297
298 static inline int pin_to_bank(unsigned pin)
299 {
300 return pin / MAX_NB_GPIO_PER_BANK;
301 }
302
303 static unsigned pin_to_mask(unsigned int pin)
304 {
305 return 1 << pin;
306 }
307
308 static void oxnas_mux_disable_interrupt(void __iomem *pio, unsigned mask)
309 {
310 oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask);
311 oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask);
312 }
313
314 static unsigned oxnas_mux_get_pullup(void __iomem *pio, unsigned pin)
315 {
316 return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
317 (readl_relaxed(pio + PULL_SENSE) & BIT(pin));
318 }
319
320 static void oxnas_mux_set_pullup(void __iomem *pio, unsigned mask, bool on)
321 {
322 if (on) {
323 oxnas_register_set_mask(pio + PULL_SENSE, mask);
324 oxnas_register_set_mask(pio + PULL_ENABLE, mask);
325 } else {
326 oxnas_register_clear_mask(pio + PULL_ENABLE, mask);
327 }
328 }
329
330 static bool oxnas_mux_get_pulldown(void __iomem *pio, unsigned pin)
331 {
332 return (readl_relaxed(pio + PULL_ENABLE) & BIT(pin)) &&
333 (!(readl_relaxed(pio + PULL_SENSE) & BIT(pin)));
334 }
335
336 static void oxnas_mux_set_pulldown(void __iomem *pio, unsigned mask, bool on)
337 {
338 if (on) {
339 oxnas_register_clear_mask(pio + PULL_SENSE, mask);
340 oxnas_register_set_mask(pio + PULL_ENABLE, mask);
341 } else {
342 oxnas_register_clear_mask(pio + PULL_ENABLE, mask);
343 };
344 }
345
346 /* unfortunately debounce control are shared */
347 static bool oxnas_mux_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
348 {
349 *div = __raw_readl(pio + CLOCK_DIV) & DEBOUNCE_MASK;
350 return __raw_readl(pio + DEBOUNCE_ENABLE) & BIT(pin);
351 }
352
353 static void oxnas_mux_set_debounce(void __iomem *pio, unsigned mask,
354 bool is_on, u32 div)
355 {
356 if (is_on) {
357 oxnas_register_value_mask(pio + CLOCK_DIV, DEBOUNCE_MASK, div);
358 oxnas_register_set_mask(pio + DEBOUNCE_ENABLE, mask);
359 } else {
360 oxnas_register_clear_mask(pio + DEBOUNCE_ENABLE, mask);
361 }
362 }
363
364
365 static void oxnas_mux_set_func2(void __iomem *cio, unsigned mask)
366 {
367 /* in fact, SECONDARY takes precedence, so clear others is not necessary */
368 oxnas_register_set_mask(cio + PINMUX_SECONDARY_SEL, mask);
369 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
370 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
371 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
372 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
373 }
374
375 static void oxnas_mux_set_func3(void __iomem *cio, unsigned mask)
376 {
377 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
378 oxnas_register_set_mask(cio + PINMUX_TERTIARY_SEL, mask);
379 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
380 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
381 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
382 }
383
384 static void oxnas_mux_set_func4(void __iomem *cio, unsigned mask)
385 {
386 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
387 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
388 oxnas_register_set_mask(cio + PINMUX_QUATERNARY_SEL, mask);
389 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
390 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
391 }
392
393 static void oxnas_mux_set_func_dbg(void __iomem *cio, unsigned mask)
394 {
395 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
396 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
397 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
398 oxnas_register_set_mask(cio + PINMUX_DEBUG_SEL, mask);
399 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
400 }
401
402 static void oxnas_mux_set_func_alt(void __iomem *cio, unsigned mask)
403 {
404 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
405 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
406 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
407 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
408 oxnas_register_set_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
409 }
410
411 static void oxnas_mux_set_gpio(void __iomem *cio, unsigned mask)
412 {
413 oxnas_register_clear_mask(cio + PINMUX_SECONDARY_SEL, mask);
414 oxnas_register_clear_mask(cio + PINMUX_TERTIARY_SEL, mask);
415 oxnas_register_clear_mask(cio + PINMUX_QUATERNARY_SEL, mask);
416 oxnas_register_clear_mask(cio + PINMUX_DEBUG_SEL, mask);
417 oxnas_register_clear_mask(cio + PINMUX_ALTERNATIVE_SEL, mask);
418 }
419
420 static enum oxnas_mux oxnas_mux_get_func(void __iomem *cio, unsigned mask)
421 {
422 if (readl_relaxed(cio + PINMUX_SECONDARY_SEL) & mask)
423 return OXNAS_PINMUX_FUNC2;
424 if (readl_relaxed(cio + PINMUX_TERTIARY_SEL) & mask)
425 return OXNAS_PINMUX_FUNC3;
426 if (readl_relaxed(cio + PINMUX_QUATERNARY_SEL) & mask)
427 return OXNAS_PINMUX_FUNC4;
428 if (readl_relaxed(cio + PINMUX_DEBUG_SEL) & mask)
429 return OXNAS_PINMUX_DEBUG;
430 if (readl_relaxed(cio + PINMUX_ALTERNATIVE_SEL) & mask)
431 return OXNAS_PINMUX_ALT;
432 return OXNAS_PINMUX_GPIO;
433 }
434
435
436 static void oxnas_pin_dbg(const struct device *dev,
437 const struct oxnas_pmx_pin *pin)
438 {
439 if (pin->mux) {
440 dev_dbg(dev,
441 "MF_%c%d configured as periph%c with conf = 0x%lu\n",
442 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A',
443 pin->conf);
444 } else {
445 dev_dbg(dev, "MF_%c%d configured as gpio with conf = 0x%lu\n",
446 pin->bank + 'A', pin->pin, pin->conf);
447 }
448 }
449
450 static int pin_check_config(struct oxnas_pinctrl *info, const char *name,
451 int index, const struct oxnas_pmx_pin *pin)
452 {
453 int mux;
454
455 /* check if it's a valid config */
456 if (pin->bank >= info->nbanks) {
457 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n",
458 name, index, pin->bank, info->nbanks);
459 return -EINVAL;
460 }
461
462 if (pin->pin >= MAX_NB_GPIO_PER_BANK) {
463 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n",
464 name, index, pin->pin, MAX_NB_GPIO_PER_BANK);
465 return -EINVAL;
466 }
467 /* gpio always allowed */
468 if (!pin->mux)
469 return 0;
470
471 mux = pin->mux - 1;
472
473 if (mux >= info->nmux) {
474 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n",
475 name, index, mux, info->nmux);
476 return -EINVAL;
477 }
478
479 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) {
480 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for MF_%c%d\n",
481 name, index, mux, pin->bank + 'A', pin->pin);
482 return -EINVAL;
483 }
484
485 return 0;
486 }
487
488 static void oxnas_mux_gpio_enable(void __iomem *cio, void __iomem *pio,
489 unsigned mask, bool input)
490 {
491 oxnas_mux_set_gpio(cio, mask);
492 if (input)
493 writel_relaxed(mask, pio + OUTPUT_EN_CLEAR);
494 else
495 writel_relaxed(mask, pio + OUTPUT_EN_SET);
496 }
497
498 static void oxnas_mux_gpio_disable(void __iomem *cio, void __iomem *pio,
499 unsigned mask)
500 {
501 /* when switch to other function, gpio is disabled automatically */
502 return;
503 }
504
505 static int oxnas_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
506 unsigned group)
507 {
508 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
509 const struct oxnas_pmx_pin *pins_conf = info->groups[group].pins_conf;
510 const struct oxnas_pmx_pin *pin;
511 uint32_t npins = info->groups[group].npins;
512 int i, ret;
513 unsigned mask;
514 void __iomem *pio;
515 void __iomem *cio;
516
517 dev_dbg(info->dev, "enable function %s group %s\n",
518 info->functions[selector].name, info->groups[group].name);
519
520 /* first check that all the pins of the group are valid with a valid
521 * paramter */
522 for (i = 0; i < npins; i++) {
523 pin = &pins_conf[i];
524 ret = pin_check_config(info, info->groups[group].name, i, pin);
525 if (ret)
526 return ret;
527 }
528
529 for (i = 0; i < npins; i++) {
530 pin = &pins_conf[i];
531 oxnas_pin_dbg(info->dev, pin);
532
533 pio = pin_to_gpioctrl(info, pin->bank);
534 cio = pin_to_muxctrl(info, pin->bank);
535
536 mask = pin_to_mask(pin->pin);
537 oxnas_mux_disable_interrupt(pio, mask);
538
539 switch (pin->mux) {
540 case OXNAS_PINMUX_GPIO:
541 oxnas_mux_gpio_enable(cio, pio, mask, 1);
542 break;
543 case OXNAS_PINMUX_FUNC2:
544 oxnas_mux_set_func2(cio, mask);
545 break;
546 case OXNAS_PINMUX_FUNC3:
547 oxnas_mux_set_func3(cio, mask);
548 break;
549 case OXNAS_PINMUX_FUNC4:
550 oxnas_mux_set_func4(cio, mask);
551 break;
552 case OXNAS_PINMUX_DEBUG:
553 oxnas_mux_set_func_dbg(cio, mask);
554 break;
555 case OXNAS_PINMUX_ALT:
556 oxnas_mux_set_func_alt(cio, mask);
557 break;
558 }
559 if (pin->mux)
560 oxnas_mux_gpio_disable(cio, pio, mask);
561 }
562
563 return 0;
564 }
565
566 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
567 static void oxnas_pmx_disable(struct pinctrl_dev *pctldev, unsigned selector,
568 unsigned group)
569 {
570 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
571 const struct oxnas_pmx_pin *pins_conf = info->groups[group].pins_conf;
572 const struct oxnas_pmx_pin *pin;
573 uint32_t npins = info->groups[group].npins;
574 int i;
575 unsigned mask;
576 void __iomem *pio;
577 void __iomem *cio;
578
579 for (i = 0; i < npins; i++) {
580 pin = &pins_conf[i];
581 oxnas_pin_dbg(info->dev, pin);
582 pio = pin_to_gpioctrl(info, pin->bank);
583 cio = pin_to_muxctrl(info, pin->bank);
584 mask = pin_to_mask(pin->pin);
585 oxnas_mux_gpio_enable(cio, pio, mask, 1);
586 }
587 }
588 #endif
589
590 static int oxnas_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
591 {
592 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
593
594 return info->nfunctions;
595 }
596
597 static const char *oxnas_pmx_get_func_name(struct pinctrl_dev *pctldev,
598 unsigned selector)
599 {
600 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
601
602 return info->functions[selector].name;
603 }
604
605 static int oxnas_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
606 const char * const **groups,
607 unsigned * const num_groups)
608 {
609 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
610
611 *groups = info->functions[selector].groups;
612 *num_groups = info->functions[selector].ngroups;
613
614 return 0;
615 }
616
617 static int oxnas_gpio_request_enable(struct pinctrl_dev *pctldev,
618 struct pinctrl_gpio_range *range,
619 unsigned offset)
620 {
621 struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
622 struct oxnas_gpio_chip *oxnas_chip;
623 struct gpio_chip *chip;
624 unsigned mask;
625
626 if (!range) {
627 dev_err(npct->dev, "invalid range\n");
628 return -EINVAL;
629 }
630 if (!range->gc) {
631 dev_err(npct->dev, "missing GPIO chip in range\n");
632 return -EINVAL;
633 }
634 chip = range->gc;
635 oxnas_chip = container_of(chip, struct oxnas_gpio_chip, chip);
636
637 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
638
639 mask = 1 << (offset - chip->base);
640
641 dev_dbg(npct->dev, "enable pin %u as MF_%c%d 0x%x\n",
642 offset, 'A' + range->id, offset - chip->base, mask);
643
644 oxnas_mux_set_gpio(oxnas_chip->ctrlbase, mask);
645
646 return 0;
647 }
648
649 static void oxnas_gpio_disable_free(struct pinctrl_dev *pctldev,
650 struct pinctrl_gpio_range *range,
651 unsigned offset)
652 {
653 struct oxnas_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
654
655 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
656 /* Set the pin to some default state, GPIO is usually default */
657 }
658
659 static const struct pinmux_ops oxnas_pmx_ops = {
660 .get_functions_count = oxnas_pmx_get_funcs_count,
661 .get_function_name = oxnas_pmx_get_func_name,
662 .get_function_groups = oxnas_pmx_get_groups,
663 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0))
664 .set_mux = oxnas_pmx_set_mux,
665 #else
666 .enable = oxnas_pmx_set_mux,
667 #endif
668 #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 16, 0))
669 .disable = oxnas_pmx_disable,
670 #endif
671 .gpio_request_enable = oxnas_gpio_request_enable,
672 .gpio_disable_free = oxnas_gpio_disable_free,
673 };
674
675 static int oxnas_pinconf_get(struct pinctrl_dev *pctldev,
676 unsigned pin_id, unsigned long *config)
677 {
678 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
679 void __iomem *pio;
680 unsigned pin;
681 int div;
682
683 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__,
684 __LINE__, pin_id, *config);
685 pio = pin_to_gpioctrl(info, pin_to_bank(pin_id));
686 pin = pin_id % MAX_NB_GPIO_PER_BANK;
687
688 if (oxnas_mux_get_pullup(pio, pin))
689 *config |= PULL_UP;
690
691 if (oxnas_mux_get_pulldown(pio, pin))
692 *config |= PULL_DOWN;
693
694 if (oxnas_mux_get_debounce(pio, pin, &div))
695 *config |= DEBOUNCE | div;
696 return 0;
697 }
698
699 static int oxnas_pinconf_set(struct pinctrl_dev *pctldev,
700 unsigned pin_id, unsigned long *configs,
701 unsigned num_configs)
702 {
703 struct oxnas_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
704 unsigned mask;
705 void __iomem *pio;
706 int i;
707 unsigned long config;
708
709 pio = pin_to_gpioctrl(info, pin_to_bank(pin_id));
710 mask = pin_to_mask(pin_id % MAX_NB_GPIO_PER_BANK);
711
712 for (i = 0; i < num_configs; i++) {
713 config = configs[i];
714
715 dev_dbg(info->dev,
716 "%s:%d, pin_id=%d, config=0x%lx",
717 __func__, __LINE__, pin_id, config);
718
719 if ((config & PULL_UP) && (config & PULL_DOWN))
720 return -EINVAL;
721
722 oxnas_mux_set_pullup(pio, mask, config & PULL_UP);
723 oxnas_mux_set_pulldown(pio, mask, config & PULL_DOWN);
724 oxnas_mux_set_debounce(pio, mask, config & DEBOUNCE,
725 config & DEBOUNCE_MASK);
726
727 } /* for each config */
728
729 return 0;
730 }
731
732 static void oxnas_pinconf_dbg_show(struct pinctrl_dev *pctldev,
733 struct seq_file *s, unsigned pin_id)
734 {
735
736 }
737
738 static void oxnas_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
739 struct seq_file *s, unsigned group)
740 {
741 }
742
743 static const struct pinconf_ops oxnas_pinconf_ops = {
744 .pin_config_get = oxnas_pinconf_get,
745 .pin_config_set = oxnas_pinconf_set,
746 .pin_config_dbg_show = oxnas_pinconf_dbg_show,
747 .pin_config_group_dbg_show = oxnas_pinconf_group_dbg_show,
748 };
749
750 static struct pinctrl_desc oxnas_pinctrl_desc = {
751 .pctlops = &oxnas_pctrl_ops,
752 .pmxops = &oxnas_pmx_ops,
753 .confops = &oxnas_pinconf_ops,
754 .owner = THIS_MODULE,
755 };
756
757 static const char *gpio_compat = "plxtech,nas782x-gpio";
758
759 static void oxnas_pinctrl_child_count(struct oxnas_pinctrl *info,
760 struct device_node *np)
761 {
762 struct device_node *child;
763
764 for_each_child_of_node(np, child) {
765 if (of_device_is_compatible(child, gpio_compat)) {
766 info->nbanks++;
767 } else {
768 info->nfunctions++;
769 info->ngroups += of_get_child_count(child);
770 }
771 }
772 }
773
774 static int oxnas_pinctrl_mux_mask(struct oxnas_pinctrl *info,
775 struct device_node *np)
776 {
777 int ret = 0;
778 int size;
779 const __be32 *list;
780
781 list = of_get_property(np, "plxtech,mux-mask", &size);
782 if (!list) {
783 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
784 return -EINVAL;
785 }
786
787 size /= sizeof(*list);
788 if (!size || size % info->nbanks) {
789 dev_err(info->dev, "wrong mux mask array should be by %d\n",
790 info->nbanks);
791 return -EINVAL;
792 }
793 info->nmux = size / info->nbanks;
794
795 info->mux_mask = devm_kzalloc(info->dev, sizeof(u32) * size, GFP_KERNEL);
796 if (!info->mux_mask) {
797 dev_err(info->dev, "could not alloc mux_mask\n");
798 return -ENOMEM;
799 }
800
801 ret = of_property_read_u32_array(np, "plxtech,mux-mask",
802 info->mux_mask, size);
803 if (ret)
804 dev_err(info->dev, "can not read the mux-mask of %d\n", size);
805 return ret;
806 }
807
808 static int oxnas_pinctrl_parse_groups(struct device_node *np,
809 struct oxnas_pin_group *grp,
810 struct oxnas_pinctrl *info, u32 index)
811 {
812 struct oxnas_pmx_pin *pin;
813 int size;
814 const __be32 *list;
815 int i, j;
816
817 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
818
819 /* Initialise group */
820 grp->name = np->name;
821
822 /*
823 * the binding format is plxtech,pins = <bank pin mux CONFIG ...>,
824 * do sanity check and calculate pins number
825 */
826 list = of_get_property(np, "plxtech,pins", &size);
827 /* we do not check return since it's safe node passed down */
828 size /= sizeof(*list);
829 if (!size || size % 4) {
830 dev_err(info->dev, "wrong pins number or pins and configs"
831 " should be divisible by 4\n");
832 return -EINVAL;
833 }
834
835 grp->npins = size / 4;
836 pin = grp->pins_conf = devm_kzalloc(info->dev,
837 grp->npins * sizeof(struct oxnas_pmx_pin),
838 GFP_KERNEL);
839 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
840 GFP_KERNEL);
841 if (!grp->pins_conf || !grp->pins)
842 return -ENOMEM;
843
844 for (i = 0, j = 0; i < size; i += 4, j++) {
845 pin->bank = be32_to_cpu(*list++);
846 pin->pin = be32_to_cpu(*list++);
847 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin;
848 pin->mux = be32_to_cpu(*list++);
849 pin->conf = be32_to_cpu(*list++);
850
851 oxnas_pin_dbg(info->dev, pin);
852 pin++;
853 }
854
855 return 0;
856 }
857
858 static int oxnas_pinctrl_parse_functions(struct device_node *np,
859 struct oxnas_pinctrl *info, u32 index)
860 {
861 struct device_node *child;
862 struct oxnas_pmx_func *func;
863 struct oxnas_pin_group *grp;
864 int ret;
865 static u32 grp_index;
866 u32 i = 0;
867
868 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
869
870 func = &info->functions[index];
871
872 /* Initialise function */
873 func->name = np->name;
874 func->ngroups = of_get_child_count(np);
875 if (func->ngroups <= 0) {
876 dev_err(info->dev, "no groups defined\n");
877 return -EINVAL;
878 }
879 func->groups = devm_kzalloc(info->dev,
880 func->ngroups * sizeof(char *), GFP_KERNEL);
881 if (!func->groups)
882 return -ENOMEM;
883
884 for_each_child_of_node(np, child) {
885 func->groups[i] = child->name;
886 grp = &info->groups[grp_index++];
887 ret = oxnas_pinctrl_parse_groups(child, grp, info, i++);
888 if (ret)
889 return ret;
890 }
891
892 return 0;
893 }
894
895 static struct of_device_id oxnas_pinctrl_of_match[] = {
896 { .compatible = "plxtech,nas782x-pinctrl"},
897 { /* sentinel */ }
898 };
899
900 static int oxnas_pinctrl_probe_dt(struct platform_device *pdev,
901 struct oxnas_pinctrl *info)
902 {
903 int ret = 0;
904 int i, j;
905 uint32_t *tmp;
906 struct device_node *np = pdev->dev.of_node;
907 struct device_node *child;
908
909 if (!np)
910 return -ENODEV;
911
912 info->dev = &pdev->dev;
913
914 oxnas_pinctrl_child_count(info, np);
915
916 if (info->nbanks < 1) {
917 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n");
918 return -EINVAL;
919 }
920
921 ret = oxnas_pinctrl_mux_mask(info, np);
922 if (ret)
923 return ret;
924
925 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux);
926
927 dev_dbg(&pdev->dev, "mux-mask\n");
928 tmp = info->mux_mask;
929 for (i = 0; i < info->nbanks; i++)
930 for (j = 0; j < info->nmux; j++, tmp++)
931 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]);
932
933 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
934 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
935 info->functions = devm_kzalloc(&pdev->dev, info->nfunctions *
936 sizeof(struct oxnas_pmx_func),
937 GFP_KERNEL);
938 if (!info->functions)
939 return -ENOMEM;
940
941 info->groups = devm_kzalloc(&pdev->dev, info->ngroups *
942 sizeof(struct oxnas_pin_group),
943 GFP_KERNEL);
944 if (!info->groups)
945 return -ENOMEM;
946
947 dev_dbg(&pdev->dev, "nbanks = %d\n", info->nbanks);
948 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
949 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
950
951 i = 0;
952
953 for_each_child_of_node(np, child) {
954 if (of_device_is_compatible(child, gpio_compat))
955 continue;
956 ret = oxnas_pinctrl_parse_functions(child, info, i++);
957 if (ret) {
958 dev_err(&pdev->dev, "failed to parse function\n");
959 return ret;
960 }
961 }
962
963 return 0;
964 }
965
966 static int oxnas_pinctrl_probe(struct platform_device *pdev)
967 {
968 struct oxnas_pinctrl *info;
969 struct pinctrl_pin_desc *pdesc;
970 int ret, i, j, k;
971
972 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
973 if (!info)
974 return -ENOMEM;
975
976 ret = oxnas_pinctrl_probe_dt(pdev, info);
977 if (ret)
978 return ret;
979
980 /*
981 * We need all the GPIO drivers to probe FIRST, or we will not be able
982 * to obtain references to the struct gpio_chip * for them, and we
983 * need this to proceed.
984 */
985 for (i = 0; i < info->nbanks; i++) {
986 if (!gpio_chips[i]) {
987 dev_warn(&pdev->dev,
988 "GPIO chip %d not registered yet\n", i);
989 devm_kfree(&pdev->dev, info);
990 return -EPROBE_DEFER;
991 }
992 }
993
994 oxnas_pinctrl_desc.name = dev_name(&pdev->dev);
995 oxnas_pinctrl_desc.npins = info->nbanks * MAX_NB_GPIO_PER_BANK;
996 oxnas_pinctrl_desc.pins = pdesc =
997 devm_kzalloc(&pdev->dev, sizeof(*pdesc) *
998 oxnas_pinctrl_desc.npins, GFP_KERNEL);
999
1000 if (!oxnas_pinctrl_desc.pins)
1001 return -ENOMEM;
1002
1003 for (i = 0 , k = 0; i < info->nbanks; i++) {
1004 for (j = 0; j < MAX_NB_GPIO_PER_BANK; j++, k++) {
1005 pdesc->number = k;
1006 pdesc->name = kasprintf(GFP_KERNEL, "MF_%c%d", i + 'A',
1007 j);
1008 pdesc++;
1009 }
1010 }
1011
1012 platform_set_drvdata(pdev, info);
1013 info->pctl = pinctrl_register(&oxnas_pinctrl_desc, &pdev->dev, info);
1014
1015 if (!info->pctl) {
1016 dev_err(&pdev->dev, "could not register OX820 pinctrl driver\n");
1017 ret = -EINVAL;
1018 goto err;
1019 }
1020
1021 /* We will handle a range of GPIO pins */
1022 for (i = 0; i < info->nbanks; i++)
1023 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range);
1024
1025 dev_info(&pdev->dev, "initialized OX820 pinctrl driver\n");
1026
1027 return 0;
1028
1029 err:
1030 return ret;
1031 }
1032
1033 static int oxnas_pinctrl_remove(struct platform_device *pdev)
1034 {
1035 struct oxnas_pinctrl *info = platform_get_drvdata(pdev);
1036
1037 pinctrl_unregister(info->pctl);
1038
1039 return 0;
1040 }
1041
1042 static int oxnas_gpio_request(struct gpio_chip *chip, unsigned offset)
1043 {
1044 /*
1045 * Map back to global GPIO space and request muxing, the direction
1046 * parameter does not matter for this controller.
1047 */
1048 int gpio = chip->base + offset;
1049 int bank = chip->base / chip->ngpio;
1050
1051 dev_dbg(chip->dev, "%s:%d MF_%c%d(%d)\n", __func__, __LINE__,
1052 'A' + bank, offset, gpio);
1053
1054 return pinctrl_request_gpio(gpio);
1055 }
1056
1057 static void oxnas_gpio_free(struct gpio_chip *chip, unsigned offset)
1058 {
1059 int gpio = chip->base + offset;
1060
1061 pinctrl_free_gpio(gpio);
1062 }
1063
1064 static int oxnas_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1065 {
1066 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1067 void __iomem *pio = oxnas_gpio->regbase;
1068
1069 writel_relaxed(BIT(offset), pio + OUTPUT_EN_CLEAR);
1070 return 0;
1071 }
1072
1073 static int oxnas_gpio_get(struct gpio_chip *chip, unsigned offset)
1074 {
1075 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1076 void __iomem *pio = oxnas_gpio->regbase;
1077 unsigned mask = 1 << offset;
1078 u32 pdsr;
1079
1080 pdsr = readl_relaxed(pio + INPUT_VALUE);
1081 return (pdsr & mask) != 0;
1082 }
1083
1084 static void oxnas_gpio_set(struct gpio_chip *chip, unsigned offset,
1085 int val)
1086 {
1087 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1088 void __iomem *pio = oxnas_gpio->regbase;
1089
1090 if (val)
1091 writel_relaxed(BIT(offset), pio + OUTPUT_SET);
1092 else
1093 writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR);
1094
1095 }
1096
1097 static int oxnas_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1098 int val)
1099 {
1100 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1101 void __iomem *pio = oxnas_gpio->regbase;
1102
1103 if (val)
1104 writel_relaxed(BIT(offset), pio + OUTPUT_SET);
1105 else
1106 writel_relaxed(BIT(offset), pio + OUTPUT_CLEAR);
1107
1108 writel_relaxed(BIT(offset), pio + OUTPUT_EN_SET);
1109
1110 return 0;
1111 }
1112
1113 static int oxnas_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1114 {
1115 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1116 int virq;
1117
1118 if (offset < chip->ngpio)
1119 virq = irq_create_mapping(oxnas_gpio->domain, offset);
1120 else
1121 virq = -ENXIO;
1122
1123 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
1124 chip->label, offset + chip->base, virq);
1125 return virq;
1126 }
1127
1128 #ifdef CONFIG_DEBUG_FS
1129 static void oxnas_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1130 {
1131 enum oxnas_mux mode;
1132 int i;
1133 struct oxnas_gpio_chip *oxnas_gpio = to_oxnas_gpio_chip(chip);
1134 void __iomem *pio = oxnas_gpio->regbase;
1135 void __iomem *cio = oxnas_gpio->ctrlbase;
1136
1137 for (i = 0; i < chip->ngpio; i++) {
1138 unsigned pin = chip->base + i;
1139 unsigned mask = pin_to_mask(pin);
1140 const char *gpio_label;
1141 u32 pdsr;
1142
1143 gpio_label = gpiochip_is_requested(chip, i);
1144 if (!gpio_label)
1145 continue;
1146 /* FIXME */
1147 mode = oxnas_mux_get_func(cio, mask);
1148 seq_printf(s, "[%s] GPIO%s%d: ",
1149 gpio_label, chip->label, i);
1150 if (mode == OXNAS_PINMUX_GPIO) {
1151 pdsr = readl_relaxed(pio + INPUT_VALUE);
1152
1153 seq_printf(s, "[gpio] %s\n",
1154 pdsr & mask ?
1155 "set" : "clear");
1156 } else {
1157 seq_printf(s, "[periph %c]\n",
1158 mode + 'A' - 1);
1159 }
1160 }
1161 }
1162 #else
1163 #define oxnas_gpio_dbg_show NULL
1164 #endif
1165
1166 /* Several AIC controller irqs are dispatched through this GPIO handler.
1167 * To use any AT91_PIN_* as an externally triggered IRQ, first call
1168 * oxnas_set_gpio_input() then maybe enable its glitch filter.
1169 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1170 * handler.
1171 */
1172
1173 static void gpio_irq_mask(struct irq_data *d)
1174 {
1175 struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d);
1176 void __iomem *pio = oxnas_gpio->regbase;
1177 unsigned mask = 1 << d->hwirq;
1178 unsigned type = irqd_get_trigger_type(d);
1179
1180 /* FIXME: need proper lock */
1181 if (type & IRQ_TYPE_EDGE_RISING)
1182 oxnas_register_clear_mask(pio + RE_IRQ_ENABLE, mask);
1183 if (type & IRQ_TYPE_EDGE_FALLING)
1184 oxnas_register_clear_mask(pio + FE_IRQ_ENABLE, mask);
1185 }
1186
1187 static void gpio_irq_unmask(struct irq_data *d)
1188 {
1189 struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(d);
1190 void __iomem *pio = oxnas_gpio->regbase;
1191 unsigned mask = 1 << d->hwirq;
1192 unsigned type = irqd_get_trigger_type(d);
1193
1194 /* FIXME: need proper lock */
1195 if (type & IRQ_TYPE_EDGE_RISING)
1196 oxnas_register_set_mask(pio + RE_IRQ_ENABLE, mask);
1197 if (type & IRQ_TYPE_EDGE_FALLING)
1198 oxnas_register_set_mask(pio + FE_IRQ_ENABLE, mask);
1199 }
1200
1201
1202 static int gpio_irq_type(struct irq_data *d, unsigned type)
1203 {
1204 if ((type & IRQ_TYPE_EDGE_BOTH) == 0) {
1205 pr_warn("OX820: Unsupported type for irq %d\n",
1206 gpio_to_irq(d->irq));
1207 return -EINVAL;
1208 }
1209 /* seems no way to set trigger type without enable irq, so leave it to unmask time */
1210
1211 return 0;
1212 }
1213
1214 static struct irq_chip gpio_irqchip = {
1215 .name = "GPIO",
1216 .irq_disable = gpio_irq_mask,
1217 .irq_mask = gpio_irq_mask,
1218 .irq_unmask = gpio_irq_unmask,
1219 .irq_set_type = gpio_irq_type,
1220 };
1221
1222 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1223 {
1224 struct irq_chip *chip = irq_desc_get_chip(desc);
1225 struct irq_data *idata = irq_desc_get_irq_data(desc);
1226 struct oxnas_gpio_chip *oxnas_gpio = irq_data_get_irq_chip_data(idata);
1227 void __iomem *pio = oxnas_gpio->regbase;
1228 unsigned long isr;
1229 int n;
1230
1231 chained_irq_enter(chip, desc);
1232 for (;;) {
1233 /* TODO: see if it works */
1234 isr = readl_relaxed(pio + IRQ_PENDING);
1235 if (!isr)
1236 break;
1237 /* acks pending interrupts */
1238 writel_relaxed(isr, pio + IRQ_PENDING);
1239
1240 for_each_set_bit(n, &isr, BITS_PER_LONG) {
1241 generic_handle_irq(irq_find_mapping(oxnas_gpio->domain,
1242 n));
1243 }
1244 }
1245 chained_irq_exit(chip, desc);
1246 /* now it may re-trigger */
1247 }
1248
1249 /*
1250 * This lock class tells lockdep that GPIO irqs are in a different
1251 * category than their parents, so it won't report false recursion.
1252 */
1253 static struct lock_class_key gpio_lock_class;
1254
1255 static int oxnas_gpio_irq_map(struct irq_domain *h, unsigned int virq,
1256 irq_hw_number_t hw)
1257 {
1258 struct oxnas_gpio_chip *oxnas_gpio = h->host_data;
1259
1260 irq_set_lockdep_class(virq, &gpio_lock_class);
1261
1262 irq_set_chip_and_handler(virq, &gpio_irqchip, handle_edge_irq);
1263 set_irq_flags(virq, IRQF_VALID);
1264 irq_set_chip_data(virq, oxnas_gpio);
1265
1266 return 0;
1267 }
1268
1269 static int oxnas_gpio_irq_domain_xlate(struct irq_domain *d,
1270 struct device_node *ctrlr,
1271 const u32 *intspec,
1272 unsigned int intsize,
1273 irq_hw_number_t *out_hwirq,
1274 unsigned int *out_type)
1275 {
1276 struct oxnas_gpio_chip *oxnas_gpio = d->host_data;
1277 int ret;
1278 int pin = oxnas_gpio->chip.base + intspec[0];
1279
1280 if (WARN_ON(intsize < 2))
1281 return -EINVAL;
1282 *out_hwirq = intspec[0];
1283 *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1284
1285 ret = gpio_request(pin, ctrlr->full_name);
1286 if (ret)
1287 return ret;
1288
1289 ret = gpio_direction_input(pin);
1290 if (ret)
1291 return ret;
1292
1293 return 0;
1294 }
1295
1296 static struct irq_domain_ops oxnas_gpio_ops = {
1297 .map = oxnas_gpio_irq_map,
1298 .xlate = oxnas_gpio_irq_domain_xlate,
1299 };
1300
1301 static int oxnas_gpio_of_irq_setup(struct device_node *node,
1302 struct oxnas_gpio_chip *oxnas_gpio,
1303 unsigned int irq)
1304 {
1305 /* Disable irqs of this controller */
1306 writel_relaxed(0, oxnas_gpio->regbase + RE_IRQ_ENABLE);
1307 writel_relaxed(0, oxnas_gpio->regbase + FE_IRQ_ENABLE);
1308
1309 /* Setup irq domain */
1310 oxnas_gpio->domain = irq_domain_add_linear(node, oxnas_gpio->chip.ngpio,
1311 &oxnas_gpio_ops, oxnas_gpio);
1312 if (!oxnas_gpio->domain)
1313 panic("oxnas_gpio: couldn't allocate irq domain (DT).\n");
1314
1315 irq_set_chip_data(irq, oxnas_gpio);
1316 irq_set_chained_handler(irq, gpio_irq_handler);
1317
1318 return 0;
1319 }
1320
1321 /* This structure is replicated for each GPIO block allocated at probe time */
1322 static struct gpio_chip oxnas_gpio_template = {
1323 .request = oxnas_gpio_request,
1324 .free = oxnas_gpio_free,
1325 .direction_input = oxnas_gpio_direction_input,
1326 .get = oxnas_gpio_get,
1327 .direction_output = oxnas_gpio_direction_output,
1328 .set = oxnas_gpio_set,
1329 .to_irq = oxnas_gpio_to_irq,
1330 .dbg_show = oxnas_gpio_dbg_show,
1331 .can_sleep = 0,
1332 .ngpio = MAX_NB_GPIO_PER_BANK,
1333 };
1334
1335 static struct of_device_id oxnas_gpio_of_match[] = {
1336 { .compatible = "plxtech,nas782x-gpio"},
1337 { /* sentinel */ }
1338 };
1339
1340 static int oxnas_gpio_probe(struct platform_device *pdev)
1341 {
1342 struct device_node *np = pdev->dev.of_node;
1343 struct resource *res;
1344 struct oxnas_gpio_chip *oxnas_chip = NULL;
1345 struct gpio_chip *chip;
1346 struct pinctrl_gpio_range *range;
1347 int ret = 0;
1348 int irq, i;
1349 int alias_idx = of_alias_get_id(np, "gpio");
1350 uint32_t ngpio;
1351 char **names;
1352
1353 BUG_ON(alias_idx >= ARRAY_SIZE(gpio_chips));
1354 if (gpio_chips[alias_idx]) {
1355 ret = -EBUSY;
1356 goto err;
1357 }
1358
1359 irq = platform_get_irq(pdev, 0);
1360 if (irq < 0) {
1361 ret = irq;
1362 goto err;
1363 }
1364
1365 oxnas_chip = devm_kzalloc(&pdev->dev, sizeof(*oxnas_chip), GFP_KERNEL);
1366 if (!oxnas_chip) {
1367 ret = -ENOMEM;
1368 goto err;
1369 }
1370
1371 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1372 oxnas_chip->regbase = devm_ioremap_resource(&pdev->dev, res);
1373 if (IS_ERR(oxnas_chip->regbase)) {
1374 ret = PTR_ERR(oxnas_chip->regbase);
1375 goto err;
1376 }
1377
1378 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1379 oxnas_chip->ctrlbase = devm_ioremap_resource(&pdev->dev, res);
1380 if (IS_ERR(oxnas_chip->ctrlbase)) {
1381 ret = PTR_ERR(oxnas_chip->ctrlbase);
1382 goto err;
1383 }
1384
1385 oxnas_chip->chip = oxnas_gpio_template;
1386
1387 chip = &oxnas_chip->chip;
1388 chip->of_node = np;
1389 chip->label = dev_name(&pdev->dev);
1390 chip->dev = &pdev->dev;
1391 chip->owner = THIS_MODULE;
1392 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK;
1393
1394 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) {
1395 if (ngpio > MAX_NB_GPIO_PER_BANK)
1396 pr_err("oxnas_gpio.%d, gpio-nb >= %d failback to %d\n",
1397 alias_idx, MAX_NB_GPIO_PER_BANK,
1398 MAX_NB_GPIO_PER_BANK);
1399 else
1400 chip->ngpio = ngpio;
1401 }
1402
1403 names = devm_kzalloc(&pdev->dev, sizeof(char *) * chip->ngpio,
1404 GFP_KERNEL);
1405
1406 if (!names) {
1407 ret = -ENOMEM;
1408 goto err;
1409 }
1410
1411 for (i = 0; i < chip->ngpio; i++)
1412 names[i] = kasprintf(GFP_KERNEL, "MF_%c%d", alias_idx + 'A', i);
1413
1414 chip->names = (const char *const *)names;
1415
1416 range = &oxnas_chip->range;
1417 range->name = chip->label;
1418 range->id = alias_idx;
1419 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK;
1420
1421 range->npins = chip->ngpio;
1422 range->gc = chip;
1423
1424 ret = gpiochip_add(chip);
1425 if (ret)
1426 goto err;
1427
1428 gpio_chips[alias_idx] = oxnas_chip;
1429 gpio_banks = max(gpio_banks, alias_idx + 1);
1430
1431 oxnas_gpio_of_irq_setup(np, oxnas_chip, irq);
1432
1433 dev_info(&pdev->dev, "at address %p\n", oxnas_chip->regbase);
1434
1435 return 0;
1436 err:
1437 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx);
1438
1439 return ret;
1440 }
1441
1442 static struct platform_driver oxnas_gpio_driver = {
1443 .driver = {
1444 .name = "gpio-oxnas",
1445 .owner = THIS_MODULE,
1446 .of_match_table = of_match_ptr(oxnas_gpio_of_match),
1447 },
1448 .probe = oxnas_gpio_probe,
1449 };
1450
1451 static struct platform_driver oxnas_pinctrl_driver = {
1452 .driver = {
1453 .name = "pinctrl-oxnas",
1454 .owner = THIS_MODULE,
1455 .of_match_table = of_match_ptr(oxnas_pinctrl_of_match),
1456 },
1457 .probe = oxnas_pinctrl_probe,
1458 .remove = oxnas_pinctrl_remove,
1459 };
1460
1461 static int __init oxnas_pinctrl_init(void)
1462 {
1463 int ret;
1464
1465 ret = platform_driver_register(&oxnas_gpio_driver);
1466 if (ret)
1467 return ret;
1468 return platform_driver_register(&oxnas_pinctrl_driver);
1469 }
1470 arch_initcall(oxnas_pinctrl_init);
1471
1472 static void __exit oxnas_pinctrl_exit(void)
1473 {
1474 platform_driver_unregister(&oxnas_pinctrl_driver);
1475 }
1476
1477 module_exit(oxnas_pinctrl_exit);
1478 MODULE_AUTHOR("Ma Hajun <mahaijuns@gmail.com>");
1479 MODULE_DESCRIPTION("Plxtech Nas782x pinctrl driver");
1480 MODULE_LICENSE("GPL v2");