target/linux/oxnas/patches-4.14/002-irqchip-versatile-fpga-Apply-clear-mask-earlier.patch

   1 From patchwork Sat Mar 21 13:38:42 2020
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   3 MIME-Version: 1.0
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   5 X-Patchwork-Submitter: Sungbo Eo <mans0n@gorani.run>
   6 X-Patchwork-Id: 11451163
   7 From: Sungbo Eo <mans0n@gorani.run>
   8 To: linux-oxnas@groups.io, Linus Walleij <linus.walleij@linaro.org>,
   9  Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>,
  10  Marc Zyngier <maz@kernel.org>, linux-arm-kernel@lists.infradead.org,
  11  linux-kernel@vger.kernel.org
  12 Subject: [PATCH] irqchip/versatile-fpga: Apply clear-mask earlier
  13 Date: Sat, 21 Mar 2020 22:38:42 +0900
  14 Message-Id: <20200321133842.2408823-1-mans0n@gorani.run>
  15 MIME-Version: 1.0
  16 Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
  17
  18 Clear its own IRQs before the parent IRQ get enabled, so that the
  19 remaining IRQs do not accidentally interrupt the parent IRQ controller.
  20
  21 This patch also fixes a reboot bug on OX820 SoC, where the remaining
  22 rps-timer IRQ raises a GIC interrupt that is left pending. After that,
  23 the rps-timer IRQ is cleared during driver initialization, and there's
  24 no IRQ left in rps-irq when local_irq_enable() is called, which evokes
  25 an error message "unexpected IRQ trap".
  26
  27 Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded interrupts from DT")
  28 Signed-off-by: Sungbo Eo <mans0n@gorani.run>
  29 Cc: Neil Armstrong <narmstrong@baylibre.com>
  30 Cc: Daniel Golle <daniel@makrotopia.org>
  31 ---
  32  drivers/irqchip/irq-versatile-fpga.c | 6 +++---
  33  1 file changed, 3 insertions(+), 3 deletions(-)
  34
  35 --- a/drivers/irqchip/irq-versatile-fpga.c
  36 +++ b/drivers/irqchip/irq-versatile-fpga.c
  37 @@ -212,6 +212,9 @@ int __init fpga_irq_of_init(struct devic
  38         if (of_property_read_u32(node, "valid-mask", &valid_mask))
  39                 valid_mask = 0;
  40
  41 +       writel(clear_mask, base + IRQ_ENABLE_CLEAR);
  42 +       writel(clear_mask, base + FIQ_ENABLE_CLEAR);
  43 +
  44         /* Some chips are cascaded from a parent IRQ */
  45         parent_irq = irq_of_parse_and_map(node, 0);
  46         if (!parent_irq) {
  47 @@ -221,9 +224,6 @@ int __init fpga_irq_of_init(struct devic
  48
  49         fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);
  50
  51 -       writel(clear_mask, base + IRQ_ENABLE_CLEAR);
  52 -       writel(clear_mask, base + FIQ_ENABLE_CLEAR);
  53 -
  54         /*
  55          * On Versatile AB/PB, some secondary interrupts have a direct
  56          * pass-thru to the primary controller for IRQs 20 and 22-31 which need