target/linux/oxnas/patches-4.14/100-oxnas-clk-plla-pllb.patch

   1 --- a/drivers/clk/clk-oxnas.c
   2 +++ b/drivers/clk/clk-oxnas.c
   3 @@ -16,19 +16,42 @@
   4   * along with this program.  If not, see <http://www.gnu.org/licenses/>.
   5   */
   6
   7 +#include <linux/clk.h>
   8 +#include <linux/clkdev.h>
   9  #include <linux/clk-provider.h>
  10  #include <linux/kernel.h>
  11  #include <linux/init.h>
  12 +#include <linux/delay.h>
  13  #include <linux/of.h>
  14  #include <linux/of_device.h>
  15  #include <linux/platform_device.h>
  16  #include <linux/stringify.h>
  17  #include <linux/regmap.h>
  18  #include <linux/mfd/syscon.h>
  19 +#include <linux/reset.h>
  20
  21  #include <dt-bindings/clock/oxsemi,ox810se.h>
  22  #include <dt-bindings/clock/oxsemi,ox820.h>
  23
  24 +#define REF300_DIV_INT_SHIFT           8
  25 +#define REF300_DIV_FRAC_SHIFT          0
  26 +#define REF300_DIV_INT(val)            ((val) << REF300_DIV_INT_SHIFT)
  27 +#define REF300_DIV_FRAC(val)           ((val) << REF300_DIV_FRAC_SHIFT)
  28 +
  29 +#define PLLB_BYPASS                    1
  30 +#define PLLB_ENSAT                     3
  31 +#define PLLB_OUTDIV                    4
  32 +#define PLLB_REFDIV                    8
  33 +#define PLLB_DIV_INT_SHIFT             8
  34 +#define PLLB_DIV_FRAC_SHIFT            0
  35 +#define PLLB_DIV_INT(val)              ((val) << PLLB_DIV_INT_SHIFT)
  36 +#define PLLB_DIV_FRAC(val)             ((val) << PLLB_DIV_FRAC_SHIFT)
  37 +
  38 +#define PLLA_REFDIV_MASK               0x3F
  39 +#define PLLA_REFDIV_SHIFT              8
  40 +#define PLLA_OUTDIV_MASK               0x7
  41 +#define PLLA_OUTDIV_SHIFT              4
  42 +
  43  /* Standard regmap gate clocks */
  44  struct clk_oxnas_gate {
  45         struct clk_hw hw;
  46 @@ -49,6 +70,135 @@ struct oxnas_stdclk_data {
  47  #define CLK_SET_REGOFFSET      0x2c
  48  #define CLK_CLR_REGOFFSET      0x30
  49
  50 +#define PLLA_CTRL0_REGOFFSET   0x1f0
  51 +#define PLLA_CTRL1_REGOFFSET   0x1f4
  52 +#define PLLB_CTRL0_REGOFFSET   0x1001f0
  53 +#define MHZ (1000 * 1000)
  54 +
  55 +struct clk_oxnas_pll {
  56 +       struct clk_hw hw;
  57 +       struct device_node *devnode;
  58 +       struct reset_control *rstc;
  59 +       struct regmap *syscon;
  60 +};
  61 +
  62 +#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw)
  63 +
  64 +static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
  65 +       unsigned long parent_rate)
  66 +{
  67 +       struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw);
  68 +       unsigned long fin = parent_rate;
  69 +       unsigned long refdiv, outdiv;
  70 +       unsigned int pll0, fbdiv;
  71 +
  72 +       BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0));
  73 +
  74 +       refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
  75 +       refdiv += 1;
  76 +       outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
  77 +       outdiv += 1;
  78 +
  79 +       BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv));
  80 +       /* seems we will not be here when pll is bypassed, so ignore this
  81 +        * case */
  82 +
  83 +       return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
  84 +}
  85 +
  86 +static const char *pll_clk_parents[] = {
  87 +       "oscillator",
  88 +};
  89 +
  90 +static struct clk_ops plla_ops = {
  91 +       .recalc_rate = plla_clk_recalc_rate,
  92 +};
  93 +
  94 +static struct clk_init_data clk_plla_init = {
  95 +       .name = "plla",
  96 +       .ops = &plla_ops,
  97 +       .parent_names = pll_clk_parents,
  98 +       .num_parents = ARRAY_SIZE(pll_clk_parents),
  99 +};
 100 +
 101 +static int pllb_clk_is_prepared(struct clk_hw *hw)
 102 +{
 103 +       struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
 104 +
 105 +       return !!pllb->rstc;
 106 +}
 107 +
 108 +static int pllb_clk_prepare(struct clk_hw *hw)
 109 +{
 110 +       struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
 111 +
 112 +       pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
 113 +
 114 +       return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
 115 +}
 116 +
 117 +static void pllb_clk_unprepare(struct clk_hw *hw)
 118 +{
 119 +       struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
 120 +
 121 +       BUG_ON(IS_ERR(pllb->rstc));
 122 +
 123 +       reset_control_put(pllb->rstc);
 124 +       pllb->rstc = NULL;
 125 +}
 126 +
 127 +static int pllb_clk_enable(struct clk_hw *hw)
 128 +{
 129 +       struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
 130 +
 131 +       BUG_ON(IS_ERR(pllb->rstc));
 132 +
 133 +       /* put PLL into bypass */
 134 +       regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
 135 +       wmb();
 136 +       udelay(10);
 137 +       reset_control_assert(pllb->rstc);
 138 +       udelay(10);
 139 +       /* set PLL B control information */
 140 +       regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff,
 141 +                         (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV));
 142 +       reset_control_deassert(pllb->rstc);
 143 +       udelay(100);
 144 +       regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0);
 145 +
 146 +       return 0;
 147 +}
 148 +
 149 +static void pllb_clk_disable(struct clk_hw *hw)
 150 +{
 151 +       struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
 152 +
 153 +       BUG_ON(IS_ERR(pllb->rstc));
 154 +
 155 +       /* put PLL into bypass */
 156 +       regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
 157 +
 158 +       wmb();
 159 +       udelay(10);
 160 +
 161 +       reset_control_assert(pllb->rstc);
 162 +}
 163 +
 164 +static struct clk_ops pllb_ops = {
 165 +       .prepare = pllb_clk_prepare,
 166 +       .unprepare = pllb_clk_unprepare,
 167 +       .is_prepared = pllb_clk_is_prepared,
 168 +       .enable = pllb_clk_enable,
 169 +       .disable = pllb_clk_disable,
 170 +};
 171 +
 172 +static struct clk_init_data clk_pllb_init = {
 173 +       .name = "pllb",
 174 +       .ops = &pllb_ops,
 175 +       .parent_names = pll_clk_parents,
 176 +       .num_parents = ARRAY_SIZE(pll_clk_parents),
 177 +};
 178 +
 179  static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
 180  {
 181         return container_of(hw, struct clk_oxnas_gate, hw);
 182 @@ -262,3 +412,42 @@ static struct platform_driver oxnas_stdc
 183         },
 184  };
 185  builtin_platform_driver(oxnas_stdclk_driver);
 186 +
 187 +void __init oxnas_init_plla(struct device_node *np)
 188 +{
 189 +       struct clk *clk;
 190 +       struct clk_oxnas_pll *plla;
 191 +
 192 +       plla = kmalloc(sizeof(*plla), GFP_KERNEL);
 193 +       BUG_ON(!plla);
 194 +
 195 +       plla->syscon = syscon_node_to_regmap(of_get_parent(np));
 196 +       plla->hw.init = &clk_plla_init;
 197 +       plla->devnode = np;
 198 +       plla->rstc = NULL;
 199 +       clk = clk_register(NULL, &plla->hw);
 200 +       BUG_ON(IS_ERR(clk));
 201 +       /* mark it as enabled */
 202 +       clk_prepare_enable(clk);
 203 +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
 204 +}
 205 +CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
 206 +
 207 +void __init oxnas_init_pllb(struct device_node *np)
 208 +{
 209 +       struct clk *clk;
 210 +       struct clk_oxnas_pll *pllb;
 211 +
 212 +       pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
 213 +       BUG_ON(!pllb);
 214 +
 215 +       pllb->syscon = syscon_node_to_regmap(of_get_parent(np));
 216 +       pllb->hw.init = &clk_pllb_init;
 217 +       pllb->devnode = np;
 218 +       pllb->rstc = NULL;
 219 +
 220 +       clk = clk_register(NULL, &pllb->hw);
 221 +       BUG_ON(IS_ERR(clk));
 222 +       of_clk_add_provider(np, of_clk_src_simple_get, clk);
 223 +}
 224 +CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
 225 --- a/arch/arm/boot/dts/ox820.dtsi
 226 +++ b/arch/arm/boot/dts/ox820.dtsi
 227 @@ -60,12 +60,6 @@
 228                         clocks = <&osc>;
 229                 };
 230
 231 -               plla: plla {
 232 -                       compatible = "fixed-clock";
 233 -                       #clock-cells = <0>;
 234 -                       clock-frequency = <850000000>;
 235 -               };
 236 -
 237                 armclk: armclk {
 238                         compatible = "fixed-factor-clock";
 239                         #clock-cells = <0>;
 240 @@ -265,6 +259,19 @@
 241                                         compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
 242                                         #clock-cells = <1>;
 243                                 };
 244 +
 245 +                               plla: plla {
 246 +                                       compatible = "plxtech,nas782x-plla";
 247 +                                       #clock-cells = <0>;
 248 +                                       clocks = <&osc>;
 249 +                               };
 250 +
 251 +                               pllb: pllb {
 252 +                                       compatible = "plxtech,nas782x-pllb";
 253 +                                       #clock-cells = <0>;
 254 +                                       clocks = <&osc>;
 255 +                                       resets = <&reset RESET_PLLB>;
 256 +                               };
 257                         };
 258                 };
 259
 260 @@ -286,6 +293,13 @@
 261                                 clocks = <&armclk>;
 262                         };
 263
 264 +                       watchdog@620 {
 265 +                               compatible = "mpcore_wdt";
 266 +                               reg = <0x620 0x20>;
 267 +                               interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
 268 +                               clocks = <&armclk>;
 269 +                       };
 270 +
 271                         gic: gic@1000 {
 272                                 compatible = "arm,arm11mp-gic";
 273                                 interrupt-controller;