pistachio: add kernel 4.14 support
[openwrt/openwrt.git] / target / linux / pistachio / patches-4.14 / 413-mtd-Introduce-SPI-NAND-framework.patch
1 From 082a89a78e29b15008284df90441747cb742f149 Mon Sep 17 00:00:00 2001
2 From: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
3 Date: Tue, 2 Dec 2014 09:58:52 -0300
4 Subject: mtd: Introduce SPI NAND framework
5
6 Add a new framework, to support SPI NAND devices. The framework registers
7 a NAND chip and handles the generic SPI NAND protocol, calling device-specific
8 hooks for each SPI NAND command.
9
10 The following is the stack design, from userspace to hardware. This commit
11 adds the "SPI NAND core" layer.
12
13 Userspace
14 ------------------
15 MTD
16 ------------------
17 NAND core
18 ------------------
19 SPI NAND core
20 ------------------
21 SPI NAND device
22 ------------------
23 SPI core
24 ------------------
25 SPI master
26 ------------------
27 Hardware
28
29 (based on http://lists.infradead.org/pipermail/linux-mtd/2014-December/056763.html)
30
31 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
32 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
33 Signed-off-by: Ian Pozella <Ian.Pozella@imgtec.com>
34 ---
35 drivers/mtd/Kconfig | 2 +
36 drivers/mtd/Makefile | 1 +
37 drivers/mtd/spi-nand/Kconfig | 7 +
38 drivers/mtd/spi-nand/Makefile | 1 +
39 drivers/mtd/spi-nand/spi-nand-base.c | 566 +++++++++++++++++++++++++++++++++++
40 include/linux/mtd/spi-nand.h | 54 ++++
41 6 files changed, 631 insertions(+)
42 create mode 100644 drivers/mtd/spi-nand/Kconfig
43 create mode 100644 drivers/mtd/spi-nand/Makefile
44 create mode 100644 drivers/mtd/spi-nand/spi-nand-base.c
45 create mode 100644 include/linux/mtd/spi-nand.h
46
47 --- a/drivers/mtd/Kconfig
48 +++ b/drivers/mtd/Kconfig
49 @@ -373,6 +373,8 @@ source "drivers/mtd/onenand/Kconfig"
50
51 source "drivers/mtd/lpddr/Kconfig"
52
53 +source "drivers/mtd/spi-nand/Kconfig"
54 +
55 source "drivers/mtd/spi-nor/Kconfig"
56
57 source "drivers/mtd/ubi/Kconfig"
58 --- a/drivers/mtd/Makefile
59 +++ b/drivers/mtd/Makefile
60 @@ -37,5 +37,6 @@ inftl-objs := inftlcore.o inftlmount.o
61
62 obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
63
64 +obj-$(CONFIG_MTD_SPI_NAND) += spi-nand/
65 obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/
66 obj-$(CONFIG_MTD_UBI) += ubi/
67 --- /dev/null
68 +++ b/drivers/mtd/spi-nand/Kconfig
69 @@ -0,0 +1,7 @@
70 +menuconfig MTD_SPI_NAND
71 + tristate "SPI NAND device support"
72 + depends on MTD
73 + select MTD_NAND
74 + help
75 + This is the framework for the SPI NAND.
76 +
77 --- /dev/null
78 +++ b/drivers/mtd/spi-nand/Makefile
79 @@ -0,0 +1 @@
80 +obj-$(CONFIG_MTD_SPI_NAND) += spi-nand-base.o
81 --- /dev/null
82 +++ b/drivers/mtd/spi-nand/spi-nand-base.c
83 @@ -0,0 +1,566 @@
84 +/*
85 + * Copyright (C) 2014 Imagination Technologies Ltd.
86 + *
87 + * This program is free software; you can redistribute it and/or modify
88 + * it under the terms of the GNU General Public License as published by
89 + * the Free Software Foundation; version 2 of the License.
90 + *
91 + * Notes:
92 + * 1. Erase and program operations need to call write_enable() first,
93 + * to clear the enable bit. This bit is cleared automatically after
94 + * the erase or program operation.
95 + *
96 + */
97 +
98 +#include <linux/device.h>
99 +#include <linux/err.h>
100 +#include <linux/errno.h>
101 +#include <linux/kernel.h>
102 +#include <linux/module.h>
103 +#include <linux/mtd/rawnand.h>
104 +#include <linux/mtd/mtd.h>
105 +#include <linux/mtd/partitions.h>
106 +#include <linux/mtd/spi-nand.h>
107 +#include <linux/of.h>
108 +#include <linux/slab.h>
109 +
110 +/* Registers common to all devices */
111 +#define SPI_NAND_LOCK_REG 0xa0
112 +#define SPI_NAND_PROT_UNLOCK_ALL 0x0
113 +
114 +#define SPI_NAND_FEATURE_REG 0xb0
115 +#define SPI_NAND_ECC_EN BIT(4)
116 +#define SPI_NAND_QUAD_EN BIT(0)
117 +
118 +#define SPI_NAND_STATUS_REG 0xc0
119 +#define SPI_NAND_STATUS_REG_ECC_MASK 0x3
120 +#define SPI_NAND_STATUS_REG_ECC_SHIFT 4
121 +#define SPI_NAND_STATUS_REG_PROG_FAIL BIT(3)
122 +#define SPI_NAND_STATUS_REG_ERASE_FAIL BIT(2)
123 +#define SPI_NAND_STATUS_REG_WREN BIT(1)
124 +#define SPI_NAND_STATUS_REG_BUSY BIT(0)
125 +
126 +#define SPI_NAND_CMD_BUF_LEN 8
127 +
128 +/* Rewind and fill the buffer with 0xff */
129 +static void spi_nand_clear_buffer(struct spi_nand *snand)
130 +{
131 + snand->buf_start = 0;
132 + memset(snand->data_buf, 0xff, snand->buf_size);
133 +}
134 +
135 +static int spi_nand_enable_ecc(struct spi_nand *snand)
136 +{
137 + int ret;
138 +
139 + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
140 + if (ret)
141 + return ret;
142 +
143 + snand->buf[0] |= SPI_NAND_ECC_EN;
144 + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
145 + if (ret)
146 + return ret;
147 + snand->ecc = true;
148 +
149 + return 0;
150 +}
151 +
152 +static int spi_nand_disable_ecc(struct spi_nand *snand)
153 +{
154 + int ret;
155 +
156 + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
157 + if (ret)
158 + return ret;
159 +
160 + snand->buf[0] &= ~SPI_NAND_ECC_EN;
161 + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
162 + if (ret)
163 + return ret;
164 + snand->ecc = false;
165 +
166 + return 0;
167 +}
168 +
169 +static int spi_nand_enable_quad(struct spi_nand *snand)
170 +{
171 + int ret;
172 +
173 + ret = snand->read_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
174 + if (ret)
175 + return ret;
176 +
177 + snand->buf[0] |= SPI_NAND_QUAD_EN;
178 + ret = snand->write_reg(snand, SPI_NAND_FEATURE_REG, snand->buf);
179 + if (ret)
180 + return ret;
181 +
182 + return 0;
183 +}
184 +/*
185 + * Wait until the status register busy bit is cleared.
186 + * Returns a negatie errno on error or time out, and a non-negative status
187 + * value if the device is ready.
188 + */
189 +static int spi_nand_wait_till_ready(struct spi_nand *snand)
190 +{
191 + unsigned long deadline = jiffies + msecs_to_jiffies(100);
192 + bool timeout = false;
193 + int ret;
194 +
195 + /*
196 + * Perhaps we should set a different timeout for each
197 + * operation (reset, read, write, erase).
198 + */
199 + while (!timeout) {
200 + if (time_after_eq(jiffies, deadline))
201 + timeout = true;
202 +
203 + ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf);
204 + if (ret < 0) {
205 + dev_err(snand->dev, "error reading status register\n");
206 + return ret;
207 + } else if (!(snand->buf[0] & SPI_NAND_STATUS_REG_BUSY)) {
208 + return snand->buf[0];
209 + }
210 +
211 + cond_resched();
212 + }
213 +
214 + dev_err(snand->dev, "operation timed out\n");
215 +
216 + return -ETIMEDOUT;
217 +}
218 +
219 +static int spi_nand_reset(struct spi_nand *snand)
220 +{
221 + int ret;
222 +
223 + ret = snand->reset(snand);
224 + if (ret < 0) {
225 + dev_err(snand->dev, "reset command failed\n");
226 + return ret;
227 + }
228 +
229 + /*
230 + * The NAND core won't wait after a device reset, so we need
231 + * to do that here.
232 + */
233 + ret = spi_nand_wait_till_ready(snand);
234 + if (ret < 0)
235 + return ret;
236 + return 0;
237 +}
238 +
239 +static int spi_nand_status(struct spi_nand *snand)
240 +{
241 + int ret, status;
242 +
243 + ret = snand->read_reg(snand, SPI_NAND_STATUS_REG, snand->buf);
244 + if (ret < 0) {
245 + dev_err(snand->dev, "error reading status register\n");
246 + return ret;
247 + }
248 + status = snand->buf[0];
249 +
250 + /* Convert this into standard NAND_STATUS values */
251 + if (status & SPI_NAND_STATUS_REG_BUSY)
252 + snand->buf[0] = 0;
253 + else
254 + snand->buf[0] = NAND_STATUS_READY;
255 +
256 + if (status & SPI_NAND_STATUS_REG_PROG_FAIL ||
257 + status & SPI_NAND_STATUS_REG_ERASE_FAIL)
258 + snand->buf[0] |= NAND_STATUS_FAIL;
259 +
260 + /*
261 + * Since we unlock the entire device at initialization, unconditionally
262 + * set the WP bit to indicate it's not protected.
263 + */
264 + snand->buf[0] |= NAND_STATUS_WP;
265 + return 0;
266 +}
267 +
268 +static int spi_nand_erase(struct spi_nand *snand, int page_addr)
269 +{
270 + int ret;
271 +
272 + ret = snand->write_enable(snand);
273 + if (ret < 0) {
274 + dev_err(snand->dev, "write enable command failed\n");
275 + return ret;
276 + }
277 +
278 + ret = snand->block_erase(snand, page_addr);
279 + if (ret < 0) {
280 + dev_err(snand->dev, "block erase command failed\n");
281 + return ret;
282 + }
283 +
284 + return 0;
285 +}
286 +
287 +static int spi_nand_write(struct spi_nand *snand)
288 +{
289 + int ret;
290 +
291 + /* Enable quad mode */
292 + ret = spi_nand_enable_quad(snand);
293 + if (ret) {
294 + dev_err(snand->dev, "error %d enabling quad mode\n", ret);
295 + return ret;
296 + }
297 + /* Store the page to cache */
298 + ret = snand->store_cache(snand, 0, snand->buf_size, snand->data_buf);
299 + if (ret < 0) {
300 + dev_err(snand->dev, "error %d storing page 0x%x to cache\n",
301 + ret, snand->page_addr);
302 + return ret;
303 + }
304 +
305 + ret = snand->write_enable(snand);
306 + if (ret < 0) {
307 + dev_err(snand->dev, "write enable command failed\n");
308 + return ret;
309 + }
310 +
311 + /* Get page from the device cache into our internal buffer */
312 + ret = snand->write_page(snand, snand->page_addr);
313 + if (ret < 0) {
314 + dev_err(snand->dev, "error %d reading page 0x%x from cache\n",
315 + ret, snand->page_addr);
316 + return ret;
317 + }
318 +
319 + return 0;
320 +}
321 +
322 +static int spi_nand_read_id(struct spi_nand *snand)
323 +{
324 + int ret;
325 +
326 + ret = snand->read_id(snand, snand->data_buf);
327 + if (ret < 0) {
328 + dev_err(snand->dev, "error %d reading ID\n", ret);
329 + return ret;
330 + }
331 + return 0;
332 +}
333 +
334 +static int spi_nand_read_page(struct spi_nand *snand, unsigned int page_addr,
335 + unsigned int page_offset, size_t length)
336 +{
337 + unsigned int corrected = 0, ecc_error = 0;
338 + int ret;
339 +
340 + /* Load a page into the cache register */
341 + ret = snand->load_page(snand, page_addr);
342 + if (ret < 0) {
343 + dev_err(snand->dev, "error %d loading page 0x%x to cache\n",
344 + ret, page_addr);
345 + return ret;
346 + }
347 +
348 + ret = spi_nand_wait_till_ready(snand);
349 + if (ret < 0)
350 + return ret;
351 +
352 + if (snand->ecc) {
353 + snand->get_ecc_status(ret, &corrected, &ecc_error);
354 + snand->bitflips = corrected;
355 +
356 + /*
357 + * If there's an ECC error, print a message and notify MTD
358 + * about it. Then complete the read, to load actual data on
359 + * the buffer (instead of the status result).
360 + */
361 + if (ecc_error) {
362 + dev_err(snand->dev,
363 + "internal ECC error reading page 0x%x\n",
364 + page_addr);
365 + snand->nand_chip.mtd.ecc_stats.failed++;
366 + } else {
367 + snand->nand_chip.mtd.ecc_stats.corrected += corrected;
368 + }
369 + }
370 +
371 + /* Enable quad mode */
372 + ret = spi_nand_enable_quad(snand);
373 + if (ret) {
374 + dev_err(snand->dev, "error %d enabling quad mode\n", ret);
375 + return ret;
376 + }
377 + /* Get page from the device cache into our internal buffer */
378 + ret = snand->read_cache(snand, page_offset, length, snand->data_buf);
379 + if (ret < 0) {
380 + dev_err(snand->dev, "error %d reading page 0x%x from cache\n",
381 + ret, page_addr);
382 + return ret;
383 + }
384 + return 0;
385 +}
386 +
387 +static u8 spi_nand_read_byte(struct mtd_info *mtd)
388 +{
389 + struct nand_chip *chip = mtd_to_nand(mtd);
390 + struct spi_nand *snand = nand_get_controller_data(chip);
391 + char val = 0xff;
392 +
393 + if (snand->buf_start < snand->buf_size)
394 + val = snand->data_buf[snand->buf_start++];
395 + return val;
396 +}
397 +
398 +static void spi_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
399 +{
400 + struct nand_chip *chip = mtd_to_nand(mtd);
401 + struct spi_nand *snand = nand_get_controller_data(chip);
402 + size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start);
403 +
404 + memcpy(snand->data_buf + snand->buf_start, buf, n);
405 + snand->buf_start += n;
406 +}
407 +
408 +static void spi_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
409 +{
410 + struct nand_chip *chip = mtd_to_nand(mtd);
411 + struct spi_nand *snand = nand_get_controller_data(chip);
412 + size_t n = min_t(size_t, len, snand->buf_size - snand->buf_start);
413 +
414 + memcpy(buf, snand->data_buf + snand->buf_start, n);
415 + snand->buf_start += n;
416 +}
417 +
418 +static int spi_nand_write_page_hwecc(struct mtd_info *mtd,
419 + struct nand_chip *chip, const uint8_t *buf, int oob_required,
420 + int page)
421 +{
422 + chip->write_buf(mtd, buf, mtd->writesize);
423 + chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
424 +
425 + return 0;
426 +}
427 +
428 +static int spi_nand_read_page_hwecc(struct mtd_info *mtd,
429 + struct nand_chip *chip, uint8_t *buf, int oob_required,
430 + int page)
431 +{
432 + struct spi_nand *snand = nand_get_controller_data(chip);
433 +
434 + chip->read_buf(mtd, buf, mtd->writesize);
435 + chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
436 +
437 + return snand->bitflips;
438 +}
439 +
440 +static int spi_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
441 +{
442 + struct spi_nand *snand = nand_get_controller_data(chip);
443 + int ret;
444 +
445 + ret = spi_nand_wait_till_ready(snand);
446 +
447 + if (ret < 0) {
448 + return NAND_STATUS_FAIL;
449 + } else if (ret & SPI_NAND_STATUS_REG_PROG_FAIL) {
450 + dev_err(snand->dev, "page program failed\n");
451 + return NAND_STATUS_FAIL;
452 + } else if (ret & SPI_NAND_STATUS_REG_ERASE_FAIL) {
453 + dev_err(snand->dev, "block erase failed\n");
454 + return NAND_STATUS_FAIL;
455 + }
456 +
457 + return NAND_STATUS_READY;
458 +}
459 +
460 +static void spi_nand_cmdfunc(struct mtd_info *mtd, unsigned int command,
461 + int column, int page_addr)
462 +{
463 + struct nand_chip *chip = mtd_to_nand(mtd);
464 + struct spi_nand *snand = nand_get_controller_data(chip);
465 +
466 + /*
467 + * In case there's any unsupported command, let's make sure
468 + * we don't keep garbage around in the buffer.
469 + */
470 + if (command != NAND_CMD_PAGEPROG) {
471 + spi_nand_clear_buffer(snand);
472 + snand->page_addr = 0;
473 + }
474 +
475 + switch (command) {
476 + case NAND_CMD_READ0:
477 + spi_nand_read_page(snand, page_addr, 0, mtd->writesize);
478 + break;
479 + case NAND_CMD_READOOB:
480 + spi_nand_disable_ecc(snand);
481 + spi_nand_read_page(snand, page_addr, mtd->writesize,
482 + mtd->oobsize);
483 + spi_nand_enable_ecc(snand);
484 + break;
485 + case NAND_CMD_READID:
486 + spi_nand_read_id(snand);
487 + break;
488 + case NAND_CMD_ERASE1:
489 + spi_nand_erase(snand, page_addr);
490 + break;
491 + case NAND_CMD_ERASE2:
492 + /* There's nothing to do here, as the erase is one-step */
493 + break;
494 + case NAND_CMD_SEQIN:
495 + snand->buf_start = column;
496 + snand->page_addr = page_addr;
497 + break;
498 + case NAND_CMD_PAGEPROG:
499 + spi_nand_write(snand);
500 + break;
501 + case NAND_CMD_STATUS:
502 + spi_nand_status(snand);
503 + break;
504 + case NAND_CMD_RESET:
505 + spi_nand_reset(snand);
506 + break;
507 + default:
508 + dev_err(&mtd->dev, "unknown command 0x%x\n", command);
509 + }
510 +}
511 +
512 +static void spi_nand_select_chip(struct mtd_info *mtd, int chip)
513 +{
514 + /* We need this to override the default */
515 +}
516 +
517 +int spi_nand_check(struct spi_nand *snand)
518 +{
519 + if (!snand->dev)
520 + return -ENODEV;
521 + if (!snand->read_cache)
522 + return -ENODEV;
523 + if (!snand->load_page)
524 + return -ENODEV;
525 + if (!snand->store_cache)
526 + return -ENODEV;
527 + if (!snand->write_page)
528 + return -ENODEV;
529 + if (!snand->write_reg)
530 + return -ENODEV;
531 + if (!snand->read_reg)
532 + return -ENODEV;
533 + if (!snand->block_erase)
534 + return -ENODEV;
535 + if (!snand->reset)
536 + return -ENODEV;
537 + if (!snand->write_enable)
538 + return -ENODEV;
539 + if (!snand->write_disable)
540 + return -ENODEV;
541 + if (!snand->get_ecc_status)
542 + return -ENODEV;
543 + return 0;
544 +}
545 +
546 +int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids)
547 +{
548 + struct nand_chip *chip = &snand->nand_chip;
549 + struct mtd_info *mtd = nand_to_mtd(chip);
550 + struct device_node *np = snand->dev->of_node;
551 + const char __maybe_unused *of_mtd_name = NULL;
552 + int ret;
553 +
554 + /* Let's check all the hooks are in-place so we don't panic later */
555 + ret = spi_nand_check(snand);
556 + if (ret)
557 + return ret;
558 +
559 + nand_set_controller_data(chip, snand);
560 + nand_set_flash_node(chip, np);
561 + chip->read_buf = spi_nand_read_buf;
562 + chip->write_buf = spi_nand_write_buf;
563 + chip->read_byte = spi_nand_read_byte;
564 + chip->cmdfunc = spi_nand_cmdfunc;
565 + chip->waitfunc = spi_nand_waitfunc;
566 + chip->select_chip = spi_nand_select_chip;
567 + chip->options |= NAND_NO_SUBPAGE_WRITE;
568 + chip->bits_per_cell = 1;
569 +
570 + mtd_set_ooblayout(mtd, snand->ooblayout);
571 + chip->ecc.read_page = spi_nand_read_page_hwecc;
572 + chip->ecc.write_page = spi_nand_write_page_hwecc;
573 + chip->ecc.mode = NAND_ECC_HW;
574 +
575 + if (of_property_read_bool(np, "nand-on-flash-bbt"))
576 + chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
577 +
578 +#ifdef CONFIG_MTD_OF_PARTS
579 + of_property_read_string(np, "linux,mtd-name", &of_mtd_name);
580 +#endif
581 + if (of_mtd_name)
582 + mtd->name = of_mtd_name;
583 + else
584 + mtd->name = snand->name;
585 + mtd->owner = THIS_MODULE;
586 +
587 + /* Allocate buffer to be used to read/write the internal registers */
588 + snand->buf = kmalloc(SPI_NAND_CMD_BUF_LEN, GFP_KERNEL);
589 + if (!snand->buf)
590 + return -ENOMEM;
591 +
592 + /* This is enabled at device power up but we'd better make sure */
593 + ret = spi_nand_enable_ecc(snand);
594 + if (ret)
595 + return ret;
596 +
597 + /* Preallocate buffer for flash identification (NAND_CMD_READID) */
598 + snand->buf_size = SPI_NAND_CMD_BUF_LEN;
599 + snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL);
600 +
601 + ret = nand_scan_ident(mtd, 1, flash_ids);
602 + if (ret)
603 + return ret;
604 +
605 + /*
606 + * SPI NAND has on-die ECC, which means we can correct as much as
607 + * we are required to. This must be done after identification of
608 + * the device.
609 + */
610 + chip->ecc.strength = chip->ecc_strength_ds;
611 + chip->ecc.size = chip->ecc_step_ds;
612 +
613 + /*
614 + * Unlock all the device before calling nand_scan_tail. This is needed
615 + * in case the in-flash bad block table needs to be created.
616 + * We could override __nand_unlock(), but since it's not currently used
617 + * by the NAND core we call this explicitly.
618 + */
619 + snand->buf[0] = SPI_NAND_PROT_UNLOCK_ALL;
620 + ret = snand->write_reg(snand, SPI_NAND_LOCK_REG, snand->buf);
621 + if (ret)
622 + return ret;
623 +
624 + /* Free the buffer and allocate a good one, to fit a page plus OOB */
625 + kfree(snand->data_buf);
626 +
627 + snand->buf_size = mtd->writesize + mtd->oobsize;
628 + snand->data_buf = kmalloc(snand->buf_size, GFP_KERNEL);
629 + if (!snand->data_buf)
630 + return -ENOMEM;
631 +
632 + ret = nand_scan_tail(mtd);
633 + if (ret)
634 + return ret;
635 +
636 + return mtd_device_register(mtd, NULL, 0);
637 +}
638 +EXPORT_SYMBOL_GPL(spi_nand_register);
639 +
640 +void spi_nand_unregister(struct spi_nand *snand)
641 +{
642 + kfree(snand->buf);
643 + kfree(snand->data_buf);
644 +}
645 +EXPORT_SYMBOL_GPL(spi_nand_unregister);
646 +
647 +MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@imgtec.com>");
648 +MODULE_DESCRIPTION("Framework for SPI NAND");
649 +MODULE_LICENSE("GPL v2");
650 --- /dev/null
651 +++ b/include/linux/mtd/spi-nand.h
652 @@ -0,0 +1,54 @@
653 +/*
654 + * Copyright (C) 2014 Imagination Technologies Ltd.
655 + *
656 + * This program is free software; you can redistribute it and/or modify
657 + * it under the terms of the GNU General Public License as published by
658 + * the Free Software Foundation; version 2 of the License.
659 + */
660 +
661 +#ifndef __LINUX_MTD_SPI_NAND_H
662 +#define __LINUX_MTD_SPI_NAND_H
663 +
664 +#include <linux/mtd/mtd.h>
665 +#include <linux/mtd/rawnand.h>
666 +
667 +struct spi_nand {
668 + struct nand_chip nand_chip;
669 + struct device *dev;
670 + const char *name;
671 +
672 + u8 *buf, *data_buf;
673 + size_t buf_size;
674 + off_t buf_start;
675 + unsigned int page_addr;
676 + unsigned int bitflips;
677 + bool ecc;
678 + struct mtd_ooblayout_ops *ooblayout;
679 +
680 + int (*reset)(struct spi_nand *snand);
681 + int (*read_id)(struct spi_nand *snand, u8 *buf);
682 +
683 + int (*write_disable)(struct spi_nand *snand);
684 + int (*write_enable)(struct spi_nand *snand);
685 +
686 + int (*read_reg)(struct spi_nand *snand, u8 opcode, u8 *buf);
687 + int (*write_reg)(struct spi_nand *snand, u8 opcode, u8 *buf);
688 + void (*get_ecc_status)(unsigned int status,
689 + unsigned int *corrected,
690 + unsigned int *ecc_errors);
691 +
692 + int (*store_cache)(struct spi_nand *snand, unsigned int page_offset,
693 + size_t length, u8 *write_buf);
694 + int (*write_page)(struct spi_nand *snand, unsigned int page_addr);
695 + int (*load_page)(struct spi_nand *snand, unsigned int page_addr);
696 + int (*read_cache)(struct spi_nand *snand, unsigned int page_offset,
697 + size_t length, u8 *read_buf);
698 + int (*block_erase)(struct spi_nand *snand, unsigned int page_addr);
699 +
700 + void *priv;
701 +};
702 +
703 +int spi_nand_register(struct spi_nand *snand, struct nand_flash_dev *flash_ids);
704 +void spi_nand_unregister(struct spi_nand *snand);
705 +
706 +#endif