target/linux/pistachio/patches-4.9/108-clk-pistachio-Fix-wrong-SDHost-card-speed.patch

   1 From 3642843a06025ec333d7e92580cf52cb8db2a652 Mon Sep 17 00:00:00 2001
   2 From: Govindraj Raja <Govindraj.Raja@imgtec.com>
   3 Date: Fri, 8 Jan 2016 16:36:07 +0000
   4 Subject: clk: pistachio: Fix wrong SDHost card speed
   5
   6 The SDHost currently clocks the card 4x slower than it
   7 should do, because there is fixed divide by 4 in the
   8 sdhost wrapper that is not present in the clock tree.
   9 To model this add a fixed divide by 4 clock node in
  10 the SDHost clock path.
  11
  12 This will ensure the right clock frequency is selected when
  13 the mmc driver tries to configure frequency on card insert.
  14
  15 Signed-off-by: Govindraj Raja <Govindraj.Raja@imgtec.com>
  16 ---
  17  drivers/clk/pistachio/clk-pistachio.c     | 3 ++-
  18  include/dt-bindings/clock/pistachio-clk.h | 1 +
  19  2 files changed, 3 insertions(+), 1 deletion(-)
  20
  21 --- a/drivers/clk/pistachio/clk-pistachio.c
  22 +++ b/drivers/clk/pistachio/clk-pistachio.c
  23 @@ -44,7 +44,7 @@ static struct pistachio_gate pistachio_g
  24         GATE(CLK_AUX_ADC_INTERNAL, "aux_adc_internal", "sys_internal_div",
  25              0x104, 22),
  26         GATE(CLK_AUX_ADC, "aux_adc", "aux_adc_div", 0x104, 23),
  27 -       GATE(CLK_SD_HOST, "sd_host", "sd_host_div", 0x104, 24),
  28 +       GATE(CLK_SD_HOST, "sd_host", "sd_host_div4", 0x104, 24),
  29         GATE(CLK_BT, "bt", "bt_div", 0x104, 25),
  30         GATE(CLK_BT_DIV4, "bt_div4", "bt_div4_div", 0x104, 26),
  31         GATE(CLK_BT_DIV8, "bt_div8", "bt_div8_div", 0x104, 27),
  32 @@ -54,6 +54,7 @@ static struct pistachio_gate pistachio_g
  33  static struct pistachio_fixed_factor pistachio_ffs[] __initdata = {
  34         FIXED_FACTOR(CLK_WIFI_DIV4, "wifi_div4", "wifi_pll", 4),
  35         FIXED_FACTOR(CLK_WIFI_DIV8, "wifi_div8", "wifi_pll", 8),
  36 +       FIXED_FACTOR(CLK_SDHOST_DIV4, "sd_host_div4", "sd_host_div", 4),
  37  };
  38
  39  static struct pistachio_div pistachio_divs[] __initdata = {
  40 --- a/include/dt-bindings/clock/pistachio-clk.h
  41 +++ b/include/dt-bindings/clock/pistachio-clk.h
  42 @@ -21,6 +21,7 @@
  43  /* Fixed-factor clocks */
  44  #define CLK_WIFI_DIV4                  16
  45  #define CLK_WIFI_DIV8                  17
  46 +#define CLK_SDHOST_DIV4                        18
  47
  48  /* Gate clocks */
  49  #define CLK_MIPS                       32