ramips: Fix GB-PC1 cpuclock again
[openwrt/openwrt.git] / target / linux / ramips / dts / SL-R7205.dts
1 /dts-v1/;
2
3 #include "rt3050.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "skyline,sl-r7205", "ralink,rt3052-soc";
10 model = "Skyline SL-R7205 Wireless 3G Router";
11
12 cfi@1f000000 {
13 compatible = "cfi-flash";
14 reg = <0x1f000000 0x800000>;
15 bank-width = <2>;
16 device-width = <2>;
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 partition@0 {
21 label = "u-boot";
22 reg = <0x0 0x30000>;
23 read-only;
24 };
25
26 partition@30000 {
27 label = "u-boot-env";
28 reg = <0x30000 0x10000>;
29 read-only;
30 };
31
32 factory: partition@40000 {
33 label = "factory";
34 reg = <0x40000 0x10000>;
35 read-only;
36 };
37
38 partition@50000 {
39 label = "firmware";
40 reg = <0x50000 0x3b0000>;
41 };
42 };
43
44 gpio-leds {
45 compatible = "gpio-leds";
46
47 wifi {
48 label = "sl-r7205:green:wifi";
49 gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
50 };
51 };
52
53 gpio-keys-polled {
54 compatible = "gpio-keys-polled";
55 #address-cells = <1>;
56 #size-cells = <0>;
57 poll-interval = <20>;
58
59 reset {
60 label = "reset";
61 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
62 linux,code = <KEY_RESTART>;
63 };
64
65 wps {
66 label = "wps";
67 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_WPS_BUTTON>;
69 };
70 };
71 };
72
73 &pinctrl {
74 state_default: pinctrl0 {
75 gpio {
76 ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf";
77 ralink,function = "gpio";
78 };
79 };
80 };
81
82 &ethernet {
83 mtd-mac-address = <&factory 0x4>;
84 };
85
86 &esw {
87 mediatek,portmap = <0x3e>;
88 };
89
90 &wmac {
91 ralink,mtd-eeprom = <&factory 0>;
92 };
93
94 &otg {
95 status = "okay";
96 };