target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "mediatek,mtk7621-soc";
   7
   8         cpus {
   9                 cpu@0 {
  10                         compatible = "mips,mips1004Kc";
  11                 };
  12
  13                 cpu@1 {
  14                         compatible = "mips,mips1004Kc";
  15                 };
  16         };
  17
  18         cpuintc: cpuintc@0 {
  19                 #address-cells = <0>;
  20                 #interrupt-cells = <1>;
  21                 interrupt-controller;
  22                 compatible = "mti,cpu-interrupt-controller";
  23         };
  24
  25         aliases {
  26                 serial0 = &uartlite;
  27         };
  28
  29         cpuclock: cpuclock@0 {
  30                 #clock-cells = <0>;
  31                 compatible = "fixed-clock";
  32
  33                 /* FIXME: there should be way to detect this */
  34                 clock-frequency = <880000000>;
  35         };
  36
  37         sysclock: sysclock@0 {
  38                 #clock-cells = <0>;
  39                 compatible = "fixed-clock";
  40
  41                 /* FIXME: there should be way to detect this */
  42                 clock-frequency = <50000000>;
  43         };
  44
  45         palmbus: palmbus@1E000000 {
  46                 compatible = "palmbus";
  47                 reg = <0x1E000000 0x100000>;
  48                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 sysc: sysc@0 {
  54                         compatible = "mtk,mt7621-sysc";
  55                         reg = <0x0 0x100>;
  56                 };
  57
  58                 wdt: wdt@100 {
  59                         compatible = "mtk,mt7621-wdt";
  60                         reg = <0x100 0x100>;
  61                 };
  62
  63                 gpio@600 {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66
  67                         compatible = "mtk,mt7621-gpio";
  68                         reg = <0x600 0x100>;
  69
  70                         gpio0: bank@0 {
  71                                 reg = <0>;
  72                                 compatible = "mtk,mt7621-gpio-bank";
  73                                 gpio-controller;
  74                                 #gpio-cells = <2>;
  75                         };
  76
  77                         gpio1: bank@1 {
  78                                 reg = <1>;
  79                                 compatible = "mtk,mt7621-gpio-bank";
  80                                 gpio-controller;
  81                                 #gpio-cells = <2>;
  82                         };
  83
  84                         gpio2: bank@2 {
  85                                 reg = <2>;
  86                                 compatible = "mtk,mt7621-gpio-bank";
  87                                 gpio-controller;
  88                                 #gpio-cells = <2>;
  89                         };
  90                 };
  91
  92                 memc: memc@5000 {
  93                         compatible = "mtk,mt7621-memc";
  94                         reg = <0x300 0x100>;
  95                 };
  96
  97                 cpc: cpc@1fbf0000 {
  98                              compatible = "mtk,mt7621-cpc";
  99                              reg = <0x1fbf0000 0x8000>;
 100                 };
 101
 102                 mc: mc@1fbf8000 {
 103                             compatible = "mtk,mt7621-mc";
 104                             reg = <0x1fbf8000 0x8000>;
 105                 };
 106
 107                 uartlite: uartlite@c00 {
 108                         compatible = "ns16550a";
 109                         reg = <0xc00 0x100>;
 110
 111                         clocks = <&sysclock>;
 112                         clock-frequency = <50000000>;
 113
 114                         interrupt-parent = <&gic>;
 115                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 116
 117                         reg-shift = <2>;
 118                         reg-io-width = <4>;
 119                         no-loopback-test;
 120                 };
 121
 122                 spi0: spi@b00 {
 123                         status = "okay";
 124
 125                         compatible = "ralink,mt7621-spi";
 126                         reg = <0xb00 0x100>;
 127
 128                         clocks = <&sysclock>;
 129
 130                         resets = <&rstctrl 18>;
 131                         reset-names = "spi";
 132
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135
 136                         pinctrl-names = "default";
 137                         pinctrl-0 = <&spi_pins>;
 138
 139                         m25p80@0 {
 140                                 #address-cells = <1>;
 141                                 #size-cells = <1>;
 142                                 reg = <0 0>;
 143                                 spi-max-frequency = <10000000>;
 144                                 m25p,chunked-io = <32>;
 145                         };
 146                 };
 147         };
 148
 149         pinctrl: pinctrl {
 150                 compatible = "ralink,rt2880-pinmux";
 151                 pinctrl-names = "default";
 152                 pinctrl-0 = <&state_default>;
 153
 154                 state_default: pinctrl0 {
 155                 };
 156
 157                 spi_pins: spi {
 158                         spi {
 159                                 ralink,group = "spi";
 160                                 ralink,function = "spi";
 161                         };
 162                 };
 163
 164                 i2c_pins: i2c {
 165                         i2c {
 166                                 ralink,group = "i2c";
 167                                 ralink,function = "i2c";
 168                         };
 169                 };
 170
 171                 uart1_pins: uart1 {
 172                         uart1 {
 173                                 ralink,group = "uart1";
 174                                 ralink,function = "uart1";
 175                         };
 176                 };
 177
 178                 uart2_pins: uart2 {
 179                         uart2 {
 180                                 ralink,group = "uart2";
 181                                 ralink,function = "uart2";
 182                         };
 183                 };
 184
 185                 uart3_pins: uart3 {
 186                         uart3 {
 187                                 ralink,group = "uart3";
 188                                 ralink,function = "uart3";
 189                         };
 190                 };
 191
 192                 rgmii1_pins: rgmii1 {
 193                         rgmii1 {
 194                                 ralink,group = "rgmii1";
 195                                 ralink,function = "rgmii1";
 196                         };
 197                 };
 198
 199                 rgmii2_pins: rgmii2 {
 200                         rgmii2 {
 201                                 ralink,group = "rgmii2";
 202                                 ralink,function = "rgmii2";
 203                         };
 204                 };
 205
 206                 mdio_pins: mdio {
 207                         mdio {
 208                                 ralink,group = "mdio";
 209                                 ralink,function = "mdio";
 210                         };
 211                 };
 212
 213                 pcie_pins: pcie {
 214                         pcie {
 215                                 ralink,group = "pcie";
 216                                 ralink,function = "pcie rst";
 217                         };
 218                 };
 219
 220                 nand_pins: nand {
 221                         spi-nand {
 222                                 ralink,group = "spi";
 223                                 ralink,function = "nand1";
 224                         };
 225
 226                         sdhci-nand {
 227                                 ralink,group = "sdhci";
 228                                 ralink,function = "nand2";
 229                         };
 230                 };
 231
 232                 sdhci_pins: sdhci {
 233                         sdhci {
 234                                 ralink,group = "sdhci";
 235                                 ralink,function = "sdhci";
 236                         };
 237                 };
 238         };
 239
 240         rstctrl: rstctrl {
 241                 compatible = "ralink,rt2880-reset";
 242                 #reset-cells = <1>;
 243         };
 244
 245         clkctrl: clkctrl {
 246                 compatible = "ralink,rt2880-clock";
 247                 #clock-cells = <1>;
 248         };
 249
 250         sdhci: sdhci@1E130000 {
 251                 compatible = "ralink,mt7620-sdhci";
 252                 reg = <0x1E130000 0x4000>;
 253
 254                 interrupt-parent = <&gic>;
 255                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 256         };
 257
 258         xhci: xhci@1E1C0000 {
 259                 status = "okay";
 260
 261                 compatible = "mediatek,mt8173-xhci";
 262                 reg = <0x1e1c0000 0x1000
 263                        0x1e1d0700 0x0100>;
 264
 265                 clocks = <&sysclock>;
 266                 clock-names = "sys_ck";
 267
 268                 interrupt-parent = <&gic>;
 269                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 270         };
 271
 272         gic: interrupt-controller@1fbc0000 {
 273                 compatible = "mti,gic";
 274                 reg = <0x1fbc0000 0x2000>;
 275
 276                 interrupt-controller;
 277                 #interrupt-cells = <3>;
 278
 279                 mti,reserved-cpu-vectors = <7>;
 280
 281                 timer {
 282                         compatible = "mti,gic-timer";
 283                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 284                         clocks = <&cpuclock>;
 285                 };
 286         };
 287
 288         nand: nand@1e003000 {
 289                 status = "disabled";
 290
 291                 compatible = "mtk,mt7621-nand";
 292                 bank-width = <2>;
 293                 reg = <0x1e003000 0x800
 294                         0x1e003800 0x800>;
 295                 #address-cells = <1>;
 296                 #size-cells = <1>;
 297         };
 298
 299         ethernet: ethernet@1e100000 {
 300                 compatible = "mediatek,mt7621-eth";
 301                 reg = <0x1e100000 0x10000>;
 302
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305
 306                 resets = <&rstctrl 6 &rstctrl 23>;
 307                 reset-names = "fe", "eth";
 308
 309                 interrupt-parent = <&gic>;
 310                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 311
 312                 mediatek,switch = <&gsw>;
 313
 314                 mdio-bus {
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317
 318                         phy1f: ethernet-phy@1f {
 319                                 reg = <0x1f>;
 320                                 phy-mode = "rgmii";
 321                         };
 322                 };
 323         };
 324
 325         gsw: gsw@1e110000 {
 326                 compatible = "mediatek,mt7621-gsw";
 327                 reg = <0x1e110000 0x8000>;
 328                 interrupt-parent = <&gic>;
 329                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 330         };
 331
 332         pcie: pcie@1e140000 {
 333                 compatible = "mediatek,mt7621-pci";
 334                 reg = <0x1e140000 0x100
 335                         0x1e142000 0x100>;
 336
 337                 #address-cells = <3>;
 338                 #size-cells = <2>;
 339
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&pcie_pins>;
 342
 343                 device_type = "pci";
 344
 345                 bus-range = <0 255>;
 346                 ranges = <
 347                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 348                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 349                 >;
 350
 351                 interrupt-parent = <&gic>;
 352                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 353                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 354                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 355
 356                 status = "okay";
 357
 358                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 359                 reset-names = "pcie0", "pcie1", "pcie2";
 360                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 361                 clock-names = "pcie0", "pcie1", "pcie2";
 362
 363                 pcie0 {
 364                         reg = <0x0000 0 0 0 0>;
 365
 366                         #address-cells = <3>;
 367                         #size-cells = <2>;
 368
 369                         device_type = "pci";
 370                 };
 371
 372                 pcie1 {
 373                         reg = <0x0800 0 0 0 0>;
 374
 375                         #address-cells = <3>;
 376                         #size-cells = <2>;
 377
 378                         device_type = "pci";
 379                 };
 380
 381                 pcie2 {
 382                         reg = <0x1000 0 0 0 0>;
 383
 384                         #address-cells = <3>;
 385                         #size-cells = <2>;
 386
 387                         device_type = "pci";
 388                 };
 389         };
 390 };