ramips: fix MT7621 dtsi
[openwrt/openwrt.git] / target / linux / ramips / dts / mt7621.dtsi
1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/clock/mt7621-clk.h>
3
4 / {
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mediatek,mt7621-soc";
8
9 cpus {
10 #address-cells = <1>;
11 #size-cells = <0>;
12
13 cpu@0 {
14 device_type = "cpu";
15 compatible = "mips,mips1004Kc";
16 reg = <0>;
17 };
18
19 cpu@1 {
20 device_type = "cpu";
21 compatible = "mips,mips1004Kc";
22 reg = <1>;
23 };
24 };
25
26 cpuintc: cpuintc {
27 #address-cells = <0>;
28 #interrupt-cells = <1>;
29 interrupt-controller;
30 compatible = "mti,cpu-interrupt-controller";
31 };
32
33 aliases {
34 serial0 = &uartlite;
35 };
36
37 pll: pll {
38 compatible = "mediatek,mt7621-pll", "syscon";
39
40 #clock-cells = <1>;
41 clock-output-names = "cpu", "bus";
42 };
43
44 sysclock: sysclock {
45 #clock-cells = <0>;
46 compatible = "fixed-clock";
47
48 /* FIXME: there should be way to detect this */
49 clock-frequency = <50000000>;
50 };
51
52
53
54 palmbus: palmbus@1E000000 {
55 compatible = "palmbus";
56 reg = <0x1E000000 0x100000>;
57 ranges = <0x0 0x1E000000 0x0FFFFF>;
58
59 #address-cells = <1>;
60 #size-cells = <1>;
61
62 sysc: sysc@0 {
63 compatible = "mtk,mt7621-sysc";
64 reg = <0x0 0x100>;
65 };
66
67 wdt: wdt@100 {
68 compatible = "mediatek,mt7621-wdt";
69 reg = <0x100 0x100>;
70 };
71
72 gpio@600 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 compatible = "mtk,mt7621-gpio";
77 reg = <0x600 0x100>;
78
79 gpio0: bank@0 {
80 reg = <0>;
81 compatible = "mtk,mt7621-gpio-bank";
82 gpio-controller;
83 #gpio-cells = <2>;
84 };
85
86 gpio1: bank@1 {
87 reg = <1>;
88 compatible = "mtk,mt7621-gpio-bank";
89 gpio-controller;
90 #gpio-cells = <2>;
91 };
92
93 gpio2: bank@2 {
94 reg = <2>;
95 compatible = "mtk,mt7621-gpio-bank";
96 gpio-controller;
97 #gpio-cells = <2>;
98 };
99 };
100
101 i2c: i2c@900 {
102 compatible = "mediatek,mt7621-i2c";
103 reg = <0x900 0x100>;
104
105 clocks = <&sysclock>;
106
107 resets = <&rstctrl 16>;
108 reset-names = "i2c";
109
110 #address-cells = <1>;
111 #size-cells = <0>;
112
113 status = "disabled";
114
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2c_pins>;
117 };
118
119 i2s: i2s@a00 {
120 compatible = "mediatek,mt7621-i2s";
121 reg = <0xa00 0x100>;
122
123 clocks = <&sysclock>;
124
125 resets = <&rstctrl 17>;
126 reset-names = "i2s";
127
128 interrupt-parent = <&gic>;
129 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
130
131 txdma-req = <2>;
132 rxdma-req = <3>;
133
134 dmas = <&gdma 4>,
135 <&gdma 6>;
136 dma-names = "tx", "rx";
137
138 status = "disabled";
139 };
140
141 systick: systick@500 {
142 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
143 reg = <0x500 0x10>;
144
145 resets = <&rstctrl 28>;
146 reset-names = "intc";
147
148 interrupt-parent = <&gic>;
149 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
150 };
151
152 memc: memc@5000 {
153 compatible = "mtk,mt7621-memc";
154 reg = <0x5000 0x1000>;
155 };
156
157 cpc: cpc@1fbf0000 {
158 compatible = "mtk,mt7621-cpc";
159 reg = <0x1fbf0000 0x8000>;
160 };
161
162 mc: mc@1fbf8000 {
163 compatible = "mtk,mt7621-mc";
164 reg = <0x1fbf8000 0x8000>;
165 };
166
167 uartlite: uartlite@c00 {
168 compatible = "ns16550a";
169 reg = <0xc00 0x100>;
170
171 clock-frequency = <50000000>;
172
173 interrupt-parent = <&gic>;
174 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
175
176 reg-shift = <2>;
177 reg-io-width = <4>;
178 no-loopback-test;
179 };
180
181 uartlite2: uartlite2@d00 {
182 compatible = "ns16550a";
183 reg = <0xd00 0x100>;
184
185 clock-frequency = <50000000>;
186
187 interrupt-parent = <&gic>;
188 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
189
190 reg-shift = <2>;
191 reg-io-width = <4>;
192
193 pinctrl-names = "default";
194 pinctrl-0 = <&uart2_pins>;
195
196 status = "disabled";
197 };
198
199 uartlite3: uartlite3@e00 {
200 compatible = "ns16550a";
201 reg = <0xe00 0x100>;
202
203 clock-frequency = <50000000>;
204
205 interrupt-parent = <&gic>;
206 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
207
208 reg-shift = <2>;
209 reg-io-width = <4>;
210
211 pinctrl-names = "default";
212 pinctrl-0 = <&uart3_pins>;
213
214 status = "disabled";
215 };
216
217 spi0: spi@b00 {
218 status = "disabled";
219
220 compatible = "ralink,mt7621-spi";
221 reg = <0xb00 0x100>;
222
223 clocks = <&pll MT7621_CLK_BUS>;
224
225 resets = <&rstctrl 18>;
226 reset-names = "spi";
227
228 #address-cells = <1>;
229 #size-cells = <0>;
230
231 pinctrl-names = "default";
232 pinctrl-0 = <&spi_pins>;
233 };
234
235 gdma: gdma@2800 {
236 compatible = "ralink,rt3883-gdma";
237 reg = <0x2800 0x800>;
238
239 resets = <&rstctrl 14>;
240 reset-names = "dma";
241
242 interrupt-parent = <&gic>;
243 interrupts = <0 13 4>;
244
245 #dma-cells = <1>;
246 #dma-channels = <16>;
247 #dma-requests = <16>;
248
249 status = "disabled";
250 };
251
252 hsdma: hsdma@7000 {
253 compatible = "mediatek,mt7621-hsdma";
254 reg = <0x7000 0x1000>;
255
256 resets = <&rstctrl 5>;
257 reset-names = "hsdma";
258
259 interrupt-parent = <&gic>;
260 interrupts = <0 11 4>;
261
262 #dma-cells = <1>;
263 #dma-channels = <1>;
264 #dma-requests = <1>;
265
266 status = "disabled";
267 };
268 };
269
270 pinctrl: pinctrl {
271 compatible = "ralink,rt2880-pinmux";
272 pinctrl-names = "default";
273 pinctrl-0 = <&state_default>;
274
275 state_default: pinctrl0 {
276 };
277
278 i2c_pins: i2c_pins {
279 i2c_pins {
280 ralink,group = "i2c";
281 ralink,function = "i2c";
282 };
283 };
284
285 spi_pins: spi_pins {
286 spi_pins {
287 ralink,group = "spi";
288 ralink,function = "spi";
289 };
290 };
291
292 uart1_pins: uart1 {
293 uart1 {
294 ralink,group = "uart1";
295 ralink,function = "uart1";
296 };
297 };
298
299 uart2_pins: uart2 {
300 uart2 {
301 ralink,group = "uart2";
302 ralink,function = "uart2";
303 };
304 };
305
306 uart3_pins: uart3 {
307 uart3 {
308 ralink,group = "uart3";
309 ralink,function = "uart3";
310 };
311 };
312
313 rgmii1_pins: rgmii1 {
314 rgmii1 {
315 ralink,group = "rgmii1";
316 ralink,function = "rgmii1";
317 };
318 };
319
320 rgmii2_pins: rgmii2 {
321 rgmii2 {
322 ralink,group = "rgmii2";
323 ralink,function = "rgmii2";
324 };
325 };
326
327 mdio_pins: mdio {
328 mdio {
329 ralink,group = "mdio";
330 ralink,function = "mdio";
331 };
332 };
333
334 pcie_pins: pcie {
335 pcie {
336 ralink,group = "pcie";
337 ralink,function = "pcie rst";
338 };
339 };
340
341 nand_pins: nand {
342 spi-nand {
343 ralink,group = "spi";
344 ralink,function = "nand1";
345 };
346
347 sdhci-nand {
348 ralink,group = "sdhci";
349 ralink,function = "nand2";
350 };
351 };
352
353 sdhci_pins: sdhci {
354 sdhci {
355 ralink,group = "sdhci";
356 ralink,function = "sdhci";
357 };
358 };
359 };
360
361 rstctrl: rstctrl {
362 compatible = "ralink,rt2880-reset";
363 #reset-cells = <1>;
364 };
365
366 clkctrl: clkctrl {
367 compatible = "ralink,rt2880-clock";
368 #clock-cells = <1>;
369 };
370
371 sdhci: sdhci@1E130000 {
372 status = "disabled";
373
374 compatible = "ralink,mt7620-sdhci";
375 reg = <0x1E130000 0x4000>;
376
377 interrupt-parent = <&gic>;
378 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
379
380 pinctrl-names = "default";
381 pinctrl-0 = <&sdhci_pins>;
382 };
383
384 xhci: xhci@1E1C0000 {
385 #address-cells = <1>;
386 #size-cells = <0>;
387 status = "okay";
388
389 compatible = "mediatek,mt8173-xhci";
390 reg = <0x1e1c0000 0x1000
391 0x1e1d0700 0x0100>;
392 reg-names = "mac", "ippc";
393
394 clocks = <&sysclock>;
395 clock-names = "sys_ck";
396
397 interrupt-parent = <&gic>;
398 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
399
400 /*
401 * Port 1 of both hubs is one usb slot and referenced here.
402 * The binding doesn't allow to address individual hubs.
403 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
404 */
405 xhci_ehci_port1: port@1 {
406 reg = <1>;
407 #trigger-source-cells = <0>;
408 };
409
410 /*
411 * Only the second usb hub has a second port. That port serves
412 * ehci and ohci.
413 */
414 ehci_port2: port@2 {
415 reg = <2>;
416 #trigger-source-cells = <0>;
417 };
418 };
419
420 gic: interrupt-controller@1fbc0000 {
421 compatible = "mti,gic";
422 reg = <0x1fbc0000 0x2000>;
423
424 interrupt-controller;
425 #interrupt-cells = <3>;
426
427 mti,reserved-cpu-vectors = <7>;
428
429 timer {
430 compatible = "mti,gic-timer";
431 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
432 clocks = <&pll MT7621_CLK_CPU>;
433 };
434 };
435
436 nand: nand@1e003000 {
437 status = "disabled";
438
439 compatible = "mtk,mt7621-nand";
440 bank-width = <2>;
441 reg = <0x1e003000 0x800
442 0x1e003800 0x800>;
443 };
444
445 ethernet: ethernet@1e100000 {
446 compatible = "mediatek,mt7621-eth";
447 reg = <0x1e100000 0x10000>;
448
449 #address-cells = <1>;
450 #size-cells = <1>;
451
452 resets = <&rstctrl 6 &rstctrl 23>;
453 reset-names = "fe", "eth";
454
455 interrupt-parent = <&gic>;
456 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
457
458 mediatek,switch = <&gsw>;
459
460 mdio-bus {
461 #address-cells = <1>;
462 #size-cells = <0>;
463
464 phy1f: ethernet-phy@1f {
465 reg = <0x1f>;
466 phy-mode = "rgmii";
467 };
468 };
469
470 hnat: hnat@0 {
471 compatible = "mediatek,mt7623-hnat";
472 reg = <0 0x10000>;
473 mtketh-ppd = "eth0";
474 mtketh-lan = "eth0";
475 mtketh-wan = "eth0";
476 resets = <&rstctrl 0>;
477 reset-names = "mtketh";
478 };
479 };
480
481 gsw: gsw@1e110000 {
482 compatible = "mediatek,mt7621-gsw";
483 reg = <0x1e110000 0x8000>;
484 interrupt-parent = <&gic>;
485 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
486 };
487
488 pcie: pcie@1e140000 {
489 compatible = "mediatek,mt7621-pci";
490 reg = <0x1e140000 0x100
491 0x1e142000 0x100>;
492
493 #address-cells = <3>;
494 #size-cells = <2>;
495
496 pinctrl-names = "default";
497 pinctrl-0 = <&pcie_pins>;
498
499 device_type = "pci";
500
501 bus-range = <0 255>;
502 ranges = <
503 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
504 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
505 >;
506
507 interrupt-parent = <&gic>;
508 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
509 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
510 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
511
512 status = "disabled";
513
514 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
515 reset-names = "pcie0", "pcie1", "pcie2";
516 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
517 clock-names = "pcie0", "pcie1", "pcie2";
518
519 pcie0: pcie@0,0 {
520 reg = <0x0000 0 0 0 0>;
521
522 #address-cells = <3>;
523 #size-cells = <2>;
524
525 ranges;
526 };
527
528 pcie1: pcie@1,0 {
529 reg = <0x0800 0 0 0 0>;
530
531 #address-cells = <3>;
532 #size-cells = <2>;
533
534 ranges;
535 };
536
537 pcie2: pcie@2,0 {
538 reg = <0x1000 0 0 0 0>;
539
540 #address-cells = <3>;
541 #size-cells = <2>;
542
543 ranges;
544 };
545 };
546 };