target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2 #include <dt-bindings/clock/mt7621-clk.h>
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "mediatek,mt7621-soc";
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         device_type = "cpu";
  15                         compatible = "mips,mips1004Kc";
  16                         reg = <0>;
  17                 };
  18
  19                 cpu@1 {
  20                         device_type = "cpu";
  21                         compatible = "mips,mips1004Kc";
  22                         reg = <1>;
  23                 };
  24         };
  25
  26         cpuintc: cpuintc {
  27                 #address-cells = <0>;
  28                 #interrupt-cells = <1>;
  29                 interrupt-controller;
  30                 compatible = "mti,cpu-interrupt-controller";
  31         };
  32
  33         aliases {
  34                 serial0 = &uartlite;
  35         };
  36
  37         pll: pll {
  38                 compatible = "mediatek,mt7621-pll", "syscon";
  39
  40                 #clock-cells = <1>;
  41                 clock-output-names = "cpu", "bus";
  42         };
  43
  44         sysclock: sysclock {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47
  48                 /* FIXME: there should be way to detect this */
  49                 clock-frequency = <50000000>;
  50         };
  51
  52
  53
  54         palmbus: palmbus@1E000000 {
  55                 compatible = "palmbus";
  56                 reg = <0x1E000000 0x100000>;
  57                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  58
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61
  62                 sysc: sysc@0 {
  63                         compatible = "mtk,mt7621-sysc";
  64                         reg = <0x0 0x100>;
  65                 };
  66
  67                 wdt: wdt@100 {
  68                         compatible = "mediatek,mt7621-wdt";
  69                         reg = <0x100 0x100>;
  70                 };
  71
  72                 gpio@600 {
  73                         #address-cells = <1>;
  74                         #size-cells = <0>;
  75
  76                         compatible = "mtk,mt7621-gpio";
  77                         reg = <0x600 0x100>;
  78
  79                         gpio0: bank@0 {
  80                                 reg = <0>;
  81                                 compatible = "mtk,mt7621-gpio-bank";
  82                                 gpio-controller;
  83                                 #gpio-cells = <2>;
  84                         };
  85
  86                         gpio1: bank@1 {
  87                                 reg = <1>;
  88                                 compatible = "mtk,mt7621-gpio-bank";
  89                                 gpio-controller;
  90                                 #gpio-cells = <2>;
  91                         };
  92
  93                         gpio2: bank@2 {
  94                                 reg = <2>;
  95                                 compatible = "mtk,mt7621-gpio-bank";
  96                                 gpio-controller;
  97                                 #gpio-cells = <2>;
  98                         };
  99                 };
 100
 101                 i2c: i2c@900 {
 102                         compatible = "mediatek,mt7621-i2c";
 103                         reg = <0x900 0x100>;
 104
 105                         clocks = <&sysclock>;
 106
 107                         resets = <&rstctrl 16>;
 108                         reset-names = "i2c";
 109
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112
 113                         status = "disabled";
 114
 115                         pinctrl-names = "default";
 116                         pinctrl-0 = <&i2c_pins>;
 117                 };
 118
 119                 i2s: i2s@a00 {
 120                         compatible = "mediatek,mt7621-i2s";
 121                         reg = <0xa00 0x100>;
 122
 123                         clocks = <&sysclock>;
 124
 125                         resets = <&rstctrl 17>;
 126                         reset-names = "i2s";
 127
 128                         interrupt-parent = <&gic>;
 129                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 130
 131                         txdma-req = <2>;
 132                         rxdma-req = <3>;
 133
 134                         dmas = <&gdma 4>,
 135                                 <&gdma 6>;
 136                         dma-names = "tx", "rx";
 137
 138                         status = "disabled";
 139                 };
 140
 141                 systick: systick@d00 {
 142                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 143                         reg = <0xd00 0x10>;
 144
 145                         resets = <&rstctrl 28>;
 146                         reset-names = "intc";
 147
 148                         interrupt-parent = <&gic>;
 149                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 150                 };
 151
 152                 memc: memc@5000 {
 153                         compatible = "mtk,mt7621-memc";
 154                         reg = <0x5000 0x1000>;
 155                 };
 156
 157                 cpc: cpc@1fbf0000 {
 158                         compatible = "mtk,mt7621-cpc";
 159                         reg = <0x1fbf0000 0x8000>;
 160                 };
 161
 162                 mc: mc@1fbf8000 {
 163                         compatible = "mtk,mt7621-mc";
 164                         reg = <0x1fbf8000 0x8000>;
 165                 };
 166
 167                 uartlite: uartlite@c00 {
 168                         compatible = "ns16550a";
 169                         reg = <0xc00 0x100>;
 170
 171                         clock-frequency = <50000000>;
 172
 173                         interrupt-parent = <&gic>;
 174                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 175
 176                         reg-shift = <2>;
 177                         reg-io-width = <4>;
 178                         no-loopback-test;
 179                 };
 180
 181                 spi0: spi@b00 {
 182                         status = "disabled";
 183
 184                         compatible = "ralink,mt7621-spi";
 185                         reg = <0xb00 0x100>;
 186
 187                         clocks = <&pll MT7621_CLK_BUS>;
 188
 189                         resets = <&rstctrl 18>;
 190                         reset-names = "spi";
 191
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194
 195                         pinctrl-names = "default";
 196                         pinctrl-0 = <&spi_pins>;
 197                 };
 198
 199                 gdma: gdma@2800 {
 200                         compatible = "ralink,rt3883-gdma";
 201                         reg = <0x2800 0x800>;
 202
 203                         resets = <&rstctrl 14>;
 204                         reset-names = "dma";
 205
 206                         interrupt-parent = <&gic>;
 207                         interrupts = <0 13 4>;
 208
 209                         #dma-cells = <1>;
 210                         #dma-channels = <16>;
 211                         #dma-requests = <16>;
 212
 213                         status = "disabled";
 214                 };
 215
 216                 hsdma: hsdma@7000 {
 217                         compatible = "mediatek,mt7621-hsdma";
 218                         reg = <0x7000 0x1000>;
 219
 220                         resets = <&rstctrl 5>;
 221                         reset-names = "hsdma";
 222
 223                         interrupt-parent = <&gic>;
 224                         interrupts = <0 11 4>;
 225
 226                         #dma-cells = <1>;
 227                         #dma-channels = <1>;
 228                         #dma-requests = <1>;
 229
 230                         status = "disabled";
 231                 };
 232         };
 233
 234         pinctrl: pinctrl {
 235                 compatible = "ralink,rt2880-pinmux";
 236                 pinctrl-names = "default";
 237                 pinctrl-0 = <&state_default>;
 238
 239                 state_default: pinctrl0 {
 240                 };
 241
 242                 i2c_pins: i2c_pins {
 243                         i2c_pins {
 244                                 ralink,group = "i2c";
 245                                 ralink,function = "i2c";
 246                         };
 247                 };
 248
 249                 spi_pins: spi_pins {
 250                         spi_pins {
 251                                 ralink,group = "spi";
 252                                 ralink,function = "spi";
 253                         };
 254                 };
 255
 256                 uart1_pins: uart1 {
 257                         uart1 {
 258                                 ralink,group = "uart1";
 259                                 ralink,function = "uart1";
 260                         };
 261                 };
 262
 263                 uart2_pins: uart2 {
 264                         uart2 {
 265                                 ralink,group = "uart2";
 266                                 ralink,function = "uart2";
 267                         };
 268                 };
 269
 270                 uart3_pins: uart3 {
 271                         uart3 {
 272                                 ralink,group = "uart3";
 273                                 ralink,function = "uart3";
 274                         };
 275                 };
 276
 277                 rgmii1_pins: rgmii1 {
 278                         rgmii1 {
 279                                 ralink,group = "rgmii1";
 280                                 ralink,function = "rgmii1";
 281                         };
 282                 };
 283
 284                 rgmii2_pins: rgmii2 {
 285                         rgmii2 {
 286                                 ralink,group = "rgmii2";
 287                                 ralink,function = "rgmii2";
 288                         };
 289                 };
 290
 291                 mdio_pins: mdio {
 292                         mdio {
 293                                 ralink,group = "mdio";
 294                                 ralink,function = "mdio";
 295                         };
 296                 };
 297
 298                 pcie_pins: pcie {
 299                         pcie {
 300                                 ralink,group = "pcie";
 301                                 ralink,function = "pcie rst";
 302                         };
 303                 };
 304
 305                 nand_pins: nand {
 306                         spi-nand {
 307                                 ralink,group = "spi";
 308                                 ralink,function = "nand1";
 309                         };
 310
 311                         sdhci-nand {
 312                                 ralink,group = "sdhci";
 313                                 ralink,function = "nand2";
 314                         };
 315                 };
 316
 317                 sdhci_pins: sdhci {
 318                         sdhci {
 319                                 ralink,group = "sdhci";
 320                                 ralink,function = "sdhci";
 321                         };
 322                 };
 323         };
 324
 325         rstctrl: rstctrl {
 326                 compatible = "ralink,rt2880-reset";
 327                 #reset-cells = <1>;
 328         };
 329
 330         clkctrl: clkctrl {
 331                 compatible = "ralink,rt2880-clock";
 332                 #clock-cells = <1>;
 333         };
 334
 335         sdhci: sdhci@1E130000 {
 336                 status = "disabled";
 337
 338                 compatible = "ralink,mt7620-sdhci";
 339                 reg = <0x1E130000 0x4000>;
 340
 341                 interrupt-parent = <&gic>;
 342                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 343
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&sdhci_pins>;
 346         };
 347
 348         xhci: xhci@1E1C0000 {
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 status = "okay";
 352
 353                 compatible = "mediatek,mt8173-xhci";
 354                 reg = <0x1e1c0000 0x1000
 355                        0x1e1d0700 0x0100>;
 356                 reg-names = "mac", "ippc";
 357
 358                 clocks = <&sysclock>;
 359                 clock-names = "sys_ck";
 360
 361                 interrupt-parent = <&gic>;
 362                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 363
 364                 /*
 365                  * Port 1 of both hubs is one usb slot and referenced here.
 366                  * The binding doesn't allow to address individual hubs.
 367                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 368                  */
 369                 xhci_ehci_port1: port@1 {
 370                         reg = <1>;
 371                         #trigger-source-cells = <0>;
 372                 };
 373
 374                 /*
 375                  * Only the second usb hub has a second port. That port serves
 376                  * ehci and ohci.
 377                  */
 378                 ehci_port2: port@2 {
 379                         reg = <2>;
 380                         #trigger-source-cells = <0>;
 381                 };
 382         };
 383
 384         gic: interrupt-controller@1fbc0000 {
 385                 compatible = "mti,gic";
 386                 reg = <0x1fbc0000 0x2000>;
 387
 388                 interrupt-controller;
 389                 #interrupt-cells = <3>;
 390
 391                 mti,reserved-cpu-vectors = <7>;
 392
 393                 timer {
 394                         compatible = "mti,gic-timer";
 395                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 396                         clocks = <&pll MT7621_CLK_CPU>;
 397                 };
 398         };
 399
 400         nand: nand@1e003000 {
 401                 status = "disabled";
 402
 403                 compatible = "mtk,mt7621-nand";
 404                 bank-width = <2>;
 405                 reg = <0x1e003000 0x800
 406                         0x1e003800 0x800>;
 407         };
 408
 409         ethernet: ethernet@1e100000 {
 410                 compatible = "mediatek,mt7621-eth";
 411                 reg = <0x1e100000 0x10000>;
 412
 413                 #address-cells = <1>;
 414                 #size-cells = <1>;
 415
 416                 resets = <&rstctrl 6 &rstctrl 23>;
 417                 reset-names = "fe", "eth";
 418
 419                 interrupt-parent = <&gic>;
 420                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 421
 422                 mediatek,switch = <&gsw>;
 423
 424                 mdio-bus {
 425                         #address-cells = <1>;
 426                         #size-cells = <0>;
 427
 428                         phy1f: ethernet-phy@1f {
 429                                 reg = <0x1f>;
 430                                 phy-mode = "rgmii";
 431                         };
 432                 };
 433
 434                 hnat: hnat@0 {
 435                         compatible = "mediatek,mt7623-hnat";
 436                         reg = <0 0x10000>;
 437                         mtketh-ppd = "eth0";
 438                         mtketh-lan = "eth0";
 439                         mtketh-wan = "eth0";
 440                         resets = <&rstctrl 0>;
 441                         reset-names = "mtketh";
 442                 };
 443         };
 444
 445         gsw: gsw@1e110000 {
 446                 compatible = "mediatek,mt7621-gsw";
 447                 reg = <0x1e110000 0x8000>;
 448                 interrupt-parent = <&gic>;
 449                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 450         };
 451
 452         pcie: pcie@1e140000 {
 453                 compatible = "mediatek,mt7621-pci";
 454                 reg = <0x1e140000 0x100
 455                         0x1e142000 0x100>;
 456
 457                 #address-cells = <3>;
 458                 #size-cells = <2>;
 459
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&pcie_pins>;
 462
 463                 device_type = "pci";
 464
 465                 bus-range = <0 255>;
 466                 ranges = <
 467                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 468                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 469                 >;
 470
 471                 interrupt-parent = <&gic>;
 472                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 473                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 474                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 475
 476                 status = "disabled";
 477
 478                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 479                 reset-names = "pcie0", "pcie1", "pcie2";
 480                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 481                 clock-names = "pcie0", "pcie1", "pcie2";
 482
 483                 pcie0: pcie@0,0 {
 484                         reg = <0x0000 0 0 0 0>;
 485
 486                         #address-cells = <3>;
 487                         #size-cells = <2>;
 488
 489                         ranges;
 490                 };
 491
 492                 pcie1: pcie@1,0 {
 493                         reg = <0x0800 0 0 0 0>;
 494
 495                         #address-cells = <3>;
 496                         #size-cells = <2>;
 497
 498                         ranges;
 499                 };
 500
 501                 pcie2: pcie@2,0 {
 502                         reg = <0x1000 0 0 0 0>;
 503
 504                         #address-cells = <3>;
 505                         #size-cells = <2>;
 506
 507                         ranges;
 508                 };
 509         };
 510 };