target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2 #include <dt-bindings/clock/mt7621-clk.h>
   3 #include <dt-bindings/gpio/gpio.h>
   4
   5 / {
   6         #address-cells = <1>;
   7         #size-cells = <1>;
   8         compatible = "mediatek,mt7621-soc";
   9
  10         cpus {
  11                 #address-cells = <1>;
  12                 #size-cells = <0>;
  13
  14                 cpu@0 {
  15                         device_type = "cpu";
  16                         compatible = "mips,mips1004Kc";
  17                         reg = <0>;
  18                 };
  19
  20                 cpu@1 {
  21                         device_type = "cpu";
  22                         compatible = "mips,mips1004Kc";
  23                         reg = <1>;
  24                 };
  25         };
  26
  27         cpuintc: cpuintc {
  28                 #address-cells = <0>;
  29                 #interrupt-cells = <1>;
  30                 interrupt-controller;
  31                 compatible = "mti,cpu-interrupt-controller";
  32         };
  33
  34         aliases {
  35                 serial0 = &uartlite;
  36         };
  37
  38         pll: pll {
  39                 compatible = "mediatek,mt7621-pll", "syscon";
  40
  41                 #clock-cells = <1>;
  42                 clock-output-names = "cpu", "bus";
  43         };
  44
  45         sysclock: sysclock {
  46                 #clock-cells = <0>;
  47                 compatible = "fixed-clock";
  48
  49                 /* FIXME: there should be way to detect this */
  50                 clock-frequency = <50000000>;
  51         };
  52
  53         palmbus: palmbus@1E000000 {
  54                 compatible = "palmbus";
  55                 reg = <0x1E000000 0x100000>;
  56                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  57
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60
  61                 sysc: sysc@0 {
  62                         compatible = "mtk,mt7621-sysc";
  63                         reg = <0x0 0x100>;
  64                 };
  65
  66                 wdt: wdt@100 {
  67                         compatible = "mediatek,mt7621-wdt";
  68                         reg = <0x100 0x100>;
  69                 };
  70
  71                 gpio: gpio@600 {
  72                         #gpio-cells = <2>;
  73                         #interrupt-cells = <2>;
  74                         compatible = "mediatek,mt7621-gpio";
  75                         gpio-controller;
  76                         interrupt-controller;
  77                         reg = <0x600 0x100>;
  78                         interrupt-parent = <&gic>;
  79                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  80                 };
  81
  82                 i2c: i2c@900 {
  83                         compatible = "mediatek,mt7621-i2c";
  84                         reg = <0x900 0x100>;
  85
  86                         clocks = <&sysclock>;
  87
  88                         resets = <&rstctrl 16>;
  89                         reset-names = "i2c";
  90
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93
  94                         status = "disabled";
  95
  96                         pinctrl-names = "default";
  97                         pinctrl-0 = <&i2c_pins>;
  98                 };
  99
 100                 i2s: i2s@a00 {
 101                         compatible = "mediatek,mt7621-i2s";
 102                         reg = <0xa00 0x100>;
 103
 104                         clocks = <&sysclock>;
 105
 106                         resets = <&rstctrl 17>;
 107                         reset-names = "i2s";
 108
 109                         interrupt-parent = <&gic>;
 110                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 111
 112                         txdma-req = <2>;
 113                         rxdma-req = <3>;
 114
 115                         dmas = <&gdma 4>,
 116                                 <&gdma 6>;
 117                         dma-names = "tx", "rx";
 118
 119                         status = "disabled";
 120                 };
 121
 122                 systick: systick@500 {
 123                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 124                         reg = <0x500 0x10>;
 125
 126                         resets = <&rstctrl 28>;
 127                         reset-names = "intc";
 128
 129                         interrupt-parent = <&gic>;
 130                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 131                 };
 132
 133                 memc: memc@5000 {
 134                         compatible = "mtk,mt7621-memc";
 135                         reg = <0x5000 0x1000>;
 136                 };
 137
 138                 cpc: cpc@1fbf0000 {
 139                         compatible = "mtk,mt7621-cpc";
 140                         reg = <0x1fbf0000 0x8000>;
 141                 };
 142
 143                 mc: mc@1fbf8000 {
 144                         compatible = "mtk,mt7621-mc";
 145                         reg = <0x1fbf8000 0x8000>;
 146                 };
 147
 148                 uartlite: uartlite@c00 {
 149                         compatible = "ns16550a";
 150                         reg = <0xc00 0x100>;
 151
 152                         clock-frequency = <50000000>;
 153
 154                         interrupt-parent = <&gic>;
 155                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 156
 157                         reg-shift = <2>;
 158                         reg-io-width = <4>;
 159                         no-loopback-test;
 160                 };
 161
 162                 uartlite2: uartlite2@d00 {
 163                         compatible = "ns16550a";
 164                         reg = <0xd00 0x100>;
 165
 166                         clock-frequency = <50000000>;
 167
 168                         interrupt-parent = <&gic>;
 169                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 170
 171                         reg-shift = <2>;
 172                         reg-io-width = <4>;
 173
 174                         pinctrl-names = "default";
 175                         pinctrl-0 = <&uart2_pins>;
 176
 177                         status = "disabled";
 178                 };
 179
 180                 uartlite3: uartlite3@e00 {
 181                         compatible = "ns16550a";
 182                         reg = <0xe00 0x100>;
 183
 184                         clock-frequency = <50000000>;
 185
 186                         interrupt-parent = <&gic>;
 187                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 188
 189                         reg-shift = <2>;
 190                         reg-io-width = <4>;
 191
 192                         pinctrl-names = "default";
 193                         pinctrl-0 = <&uart3_pins>;
 194
 195                         status = "disabled";
 196                 };
 197
 198                 spi0: spi@b00 {
 199                         status = "disabled";
 200
 201                         compatible = "ralink,mt7621-spi";
 202                         reg = <0xb00 0x100>;
 203
 204                         clocks = <&pll MT7621_CLK_BUS>;
 205
 206                         resets = <&rstctrl 18>;
 207                         reset-names = "spi";
 208
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211
 212                         pinctrl-names = "default";
 213                         pinctrl-0 = <&spi_pins>;
 214                 };
 215
 216                 gdma: gdma@2800 {
 217                         compatible = "ralink,rt3883-gdma";
 218                         reg = <0x2800 0x800>;
 219
 220                         resets = <&rstctrl 14>;
 221                         reset-names = "dma";
 222
 223                         interrupt-parent = <&gic>;
 224                         interrupts = <0 13 4>;
 225
 226                         #dma-cells = <1>;
 227                         #dma-channels = <16>;
 228                         #dma-requests = <16>;
 229
 230                         status = "disabled";
 231                 };
 232
 233                 hsdma: hsdma@7000 {
 234                         compatible = "mediatek,mt7621-hsdma";
 235                         reg = <0x7000 0x1000>;
 236
 237                         resets = <&rstctrl 5>;
 238                         reset-names = "hsdma";
 239
 240                         interrupt-parent = <&gic>;
 241                         interrupts = <0 11 4>;
 242
 243                         #dma-cells = <1>;
 244                         #dma-channels = <1>;
 245                         #dma-requests = <1>;
 246
 247                         status = "disabled";
 248                 };
 249         };
 250
 251         pinctrl: pinctrl {
 252                 compatible = "ralink,rt2880-pinmux";
 253                 pinctrl-names = "default";
 254                 pinctrl-0 = <&state_default>;
 255
 256                 state_default: pinctrl0 {
 257                 };
 258
 259                 i2c_pins: i2c_pins {
 260                         i2c_pins {
 261                                 groups = "i2c";
 262                                 function = "i2c";
 263                         };
 264                 };
 265
 266                 spi_pins: spi_pins {
 267                         spi_pins {
 268                                 groups = "spi";
 269                                 function = "spi";
 270                         };
 271                 };
 272
 273                 uart1_pins: uart1 {
 274                         uart1 {
 275                                 groups = "uart1";
 276                                 function = "uart1";
 277                         };
 278                 };
 279
 280                 uart2_pins: uart2 {
 281                         uart2 {
 282                                 groups = "uart2";
 283                                 function = "uart2";
 284                         };
 285                 };
 286
 287                 uart3_pins: uart3 {
 288                         uart3 {
 289                                 groups = "uart3";
 290                                 function = "uart3";
 291                         };
 292                 };
 293
 294                 rgmii1_pins: rgmii1 {
 295                         rgmii1 {
 296                                 groups = "rgmii1";
 297                                 function = "rgmii1";
 298                         };
 299                 };
 300
 301                 rgmii2_pins: rgmii2 {
 302                         rgmii2 {
 303                                 groups = "rgmii2";
 304                                 function = "rgmii2";
 305                         };
 306                 };
 307
 308                 mdio_pins: mdio {
 309                         mdio {
 310                                 groups = "mdio";
 311                                 function = "mdio";
 312                         };
 313                 };
 314
 315                 pcie_pins: pcie {
 316                         pcie {
 317                                 groups = "pcie";
 318                                 function = "gpio";
 319                         };
 320                 };
 321
 322                 nand_pins: nand {
 323                         spi-nand {
 324                                 groups = "spi";
 325                                 function = "nand1";
 326                         };
 327
 328                         sdhci-nand {
 329                                 groups = "sdhci";
 330                                 function = "nand2";
 331                         };
 332                 };
 333
 334                 sdhci_pins: sdhci {
 335                         sdhci {
 336                                 groups = "sdhci";
 337                                 function = "sdhci";
 338                         };
 339                 };
 340         };
 341
 342         rstctrl: rstctrl {
 343                 compatible = "ralink,rt2880-reset";
 344                 #reset-cells = <1>;
 345         };
 346
 347         clkctrl: clkctrl {
 348                 compatible = "ralink,rt2880-clock";
 349                 #clock-cells = <1>;
 350         };
 351
 352         sdhci: sdhci@1E130000 {
 353                 status = "disabled";
 354
 355                 compatible = "ralink,mt7620-sdhci";
 356                 reg = <0x1E130000 0x4000>;
 357
 358                 interrupt-parent = <&gic>;
 359                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 360
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&sdhci_pins>;
 363         };
 364
 365         xhci: xhci@1E1C0000 {
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 status = "okay";
 369
 370                 compatible = "mediatek,mt8173-xhci";
 371                 reg = <0x1e1c0000 0x1000
 372                        0x1e1d0700 0x0100>;
 373                 reg-names = "mac", "ippc";
 374
 375                 clocks = <&sysclock>;
 376                 clock-names = "sys_ck";
 377
 378                 interrupt-parent = <&gic>;
 379                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 380
 381                 /*
 382                  * Port 1 of both hubs is one usb slot and referenced here.
 383                  * The binding doesn't allow to address individual hubs.
 384                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 385                  */
 386                 xhci_ehci_port1: port@1 {
 387                         reg = <1>;
 388                         #trigger-source-cells = <0>;
 389                 };
 390
 391                 /*
 392                  * Only the second usb hub has a second port. That port serves
 393                  * ehci and ohci.
 394                  */
 395                 ehci_port2: port@2 {
 396                         reg = <2>;
 397                         #trigger-source-cells = <0>;
 398                 };
 399         };
 400
 401         gic: interrupt-controller@1fbc0000 {
 402                 compatible = "mti,gic";
 403                 reg = <0x1fbc0000 0x2000>;
 404
 405                 interrupt-controller;
 406                 #interrupt-cells = <3>;
 407
 408                 mti,reserved-cpu-vectors = <7>;
 409
 410                 timer {
 411                         compatible = "mti,gic-timer";
 412                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 413                         clocks = <&pll MT7621_CLK_CPU>;
 414                 };
 415         };
 416
 417         nand: nand@1e003000 {
 418                 status = "disabled";
 419
 420                 compatible = "mtk,mt7621-nand";
 421                 bank-width = <2>;
 422                 reg = <0x1e003000 0x800
 423                         0x1e003800 0x800>;
 424         };
 425
 426         ethsys: syscon@1e000000 {
 427                 compatible = "mediatek,mt7621-ethsys",
 428                              "syscon";
 429                 reg = <0x1e000000 0x1000>;
 430                 #clock-cells = <1>;
 431         };
 432
 433         ethernet: ethernet@1e100000 {
 434                 compatible = "mediatek,mt7621-eth";
 435                 reg = <0x1e100000 0x10000>;
 436
 437                 clocks = <&sysclock>;
 438                 clock-names = "ethif";
 439
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442
 443                 resets = <&rstctrl 6 &rstctrl 23>;
 444                 reset-names = "fe", "eth";
 445
 446                 interrupt-parent = <&gic>;
 447                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 448
 449                 mediatek,ethsys = <&ethsys>;
 450
 451                 gmac0: mac@0 {
 452                         compatible = "mediatek,eth-mac";
 453                         reg = <0>;
 454                         phy-mode = "rgmii";
 455
 456                         fixed-link {
 457                                 speed = <1000>;
 458                                 full-duplex;
 459                                 pause;
 460                         };
 461                 };
 462
 463                 gmac1: mac@1 {
 464                         compatible = "mediatek,eth-mac";
 465                         reg = <1>;
 466                         status = "disabled";
 467                         phy-mode = "rgmii-rxid";
 468                 };
 469
 470                 mdio: mdio-bus {
 471                         #address-cells = <1>;
 472                         #size-cells = <0>;
 473
 474                         switch0: switch@1f {
 475                                 compatible = "mediatek,mt7621";
 476                                 #address-cells = <1>;
 477                                 #size-cells = <0>;
 478                                 reg = <0x1f>;
 479                                 mediatek,mcm;
 480                                 resets = <&rstctrl 2>;
 481                                 reset-names = "mcm";
 482
 483                                 ports {
 484                                         #address-cells = <1>;
 485                                         #size-cells = <0>;
 486                                         reg = <0>;
 487
 488                                         port@0 {
 489                                                 status = "disabled";
 490                                                 reg = <0>;
 491                                                 label = "lan0";
 492                                         };
 493
 494                                         port@1 {
 495                                                 status = "disabled";
 496                                                 reg = <1>;
 497                                                 label = "lan1";
 498                                         };
 499
 500                                         port@2 {
 501                                                 status = "disabled";
 502                                                 reg = <2>;
 503                                                 label = "lan2";
 504                                         };
 505
 506                                         port@3 {
 507                                                 status = "disabled";
 508                                                 reg = <3>;
 509                                                 label = "lan3";
 510                                         };
 511
 512                                         port@4 {
 513                                                 status = "disabled";
 514                                                 reg = <4>;
 515                                                 label = "lan4";
 516                                         };
 517
 518                                         port@6 {
 519                                                 reg = <6>;
 520                                                 label = "cpu";
 521                                                 ethernet = <&gmac0>;
 522                                                 phy-mode = "rgmii";
 523
 524                                                 fixed-link {
 525                                                         speed = <1000>;
 526                                                         full-duplex;
 527                                                 };
 528                                         };
 529                                 };
 530                         };
 531                 };
 532         };
 533
 534         gsw: gsw@1e110000 {
 535                 compatible = "mediatek,mt7621-gsw";
 536                 reg = <0x1e110000 0x8000>;
 537                 interrupt-parent = <&gic>;
 538                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 539         };
 540
 541         pcie: pcie@1e140000 {
 542                 compatible = "mediatek,mt7621-pci";
 543                 reg = <0x1e140000 0x100     /* host-pci bridge registers */
 544                         0x1e142000 0x100    /* pcie port 0 RC control registers */
 545                         0x1e143000 0x100    /* pcie port 1 RC control registers */
 546                         0x1e144000 0x100>;  /* pcie port 2 RC control registers */
 547                 #address-cells = <3>;
 548                 #size-cells = <2>;
 549
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&pcie_pins>;
 552
 553                 device_type = "pci";
 554
 555                 bus-range = <0 255>;
 556                 ranges = <
 557                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 558                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 559                 >;
 560
 561                 #interrupt-cells = <1>;
 562                 interrupt-map-mask = <0xF0000 0 0 1>;
 563                 interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
 564                                 <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
 565                                 <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 566
 567                 status = "disabled";
 568
 569                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 570                 reset-names = "pcie0", "pcie1", "pcie2";
 571                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 572                 clock-names = "pcie0", "pcie1", "pcie2";
 573                 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
 574                 phy-names = "pcie-phy0", "pcie-phy2";
 575
 576                 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 577
 578                 pcie0: pcie@0,0 {
 579                         reg = <0x0000 0 0 0 0>;
 580                         #address-cells = <3>;
 581                         #size-cells = <2>;
 582                         ranges;
 583                         bus-range = <0x00 0xff>;
 584                 };
 585
 586                 pcie1: pcie@1,0 {
 587                         reg = <0x0800 0 0 0 0>;
 588                         #address-cells = <3>;
 589                         #size-cells = <2>;
 590                         ranges;
 591                         bus-range = <0x00 0xff>;
 592                 };
 593
 594                 pcie2: pcie@2,0 {
 595                         reg = <0x1000 0 0 0 0>;
 596                         #address-cells = <3>;
 597                         #size-cells = <2>;
 598                         ranges;
 599                         bus-range = <0x00 0xff>;
 600                 };
 601         };
 602
 603         pcie0_phy: pcie-phy@1e149000 {
 604                 compatible = "mediatek,mt7621-pci-phy";
 605                 reg = <0x1e149000 0x0700>;
 606                 #phy-cells = <1>;
 607         };
 608
 609         pcie2_phy: pcie-phy@1e14a000 {
 610                 compatible = "mediatek,mt7621-pci-phy";
 611                 reg = <0x1e14a000 0x0700>;
 612                 #phy-cells = <1>;
 613         };
 614 };