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Revert "ramips: improve interrupt mapping"
[openwrt/openwrt.git] / target / linux / ramips / files-4.14 / arch / mips / pci / pci-mt7621.c
1 /**************************************************************************
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
5 *
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 *
29 **************************************************************************
30 * May 2007 Bruce Chang
31 * Initial Release
32 *
33 * May 2009 Bruce Chang
34 * support RT2880/RT3883 PCIe
35 *
36 * May 2011 Bruce Chang
37 * support RT6855/MT7620 PCIe
38 *
39 **************************************************************************
40 */
41
42 #include <linux/types.h>
43 #include <linux/pci.h>
44 #include <linux/kernel.h>
45 #include <linux/slab.h>
46 #include <linux/version.h>
47 #include <asm/pci.h>
48 #include <asm/io.h>
49 #include <asm/mips-cm.h>
50 #include <linux/init.h>
51 #include <linux/module.h>
52 #include <linux/delay.h>
53 #include <linux/of.h>
54 #include <linux/of_pci.h>
55 #include <linux/of_irq.h>
56 #include <linux/platform_device.h>
57
58 #include <ralink_regs.h>
59
60 extern void pcie_phy_init(void);
61 extern void chk_phy_pll(void);
62
63 /*
64 * These functions and structures provide the BIOS scan and mapping of the PCI
65 * devices.
66 */
67
68 #define CONFIG_PCIE_PORT0
69 #define CONFIG_PCIE_PORT1
70 #define CONFIG_PCIE_PORT2
71 #define RALINK_PCIE0_CLK_EN (1<<24)
72 #define RALINK_PCIE1_CLK_EN (1<<25)
73 #define RALINK_PCIE2_CLK_EN (1<<26)
74
75 #define RALINK_PCI_CONFIG_ADDR 0x20
76 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
77 #define RALINK_INT_PCIE0 pcie_irq[0]
78 #define RALINK_INT_PCIE1 pcie_irq[1]
79 #define RALINK_INT_PCIE2 pcie_irq[2]
80 #define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
81 #define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
82 #define RALINK_PCIE0_RST (1<<24)
83 #define RALINK_PCIE1_RST (1<<25)
84 #define RALINK_PCIE2_RST (1<<26)
85 #define RALINK_SYSCTL_BASE 0xBE000000
86
87 #define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
88 #define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
89 #define RALINK_PCI_BASE 0xBE140000
90
91 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
92 #define RT6855_PCIE0_OFFSET 0x2000
93 #define RT6855_PCIE1_OFFSET 0x3000
94 #define RT6855_PCIE2_OFFSET 0x4000
95
96 #define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
97 #define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
98 #define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
99 #define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
100 #define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
101 #define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
102 #define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
103 #define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
104
105 #define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
106 #define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
107 #define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
108 #define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
109 #define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
110 #define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
111 #define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
112 #define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
113
114 #define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
115 #define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
116 #define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
117 #define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
118 #define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
119 #define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
120 #define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
121 #define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
122
123 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
124 #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
125
126
127 #define MV_WRITE(ofs, data) \
128 *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
129 #define MV_READ(ofs, data) \
130 *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
131 #define MV_READ_DATA(ofs) \
132 le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
133
134 #define MV_WRITE_16(ofs, data) \
135 *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
136 #define MV_READ_16(ofs, data) \
137 *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
138
139 #define MV_WRITE_8(ofs, data) \
140 *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
141 #define MV_READ_8(ofs, data) \
142 *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
143
144
145
146 #define RALINK_PCI_MM_MAP_BASE 0x60000000
147 #define RALINK_PCI_IO_MAP_BASE 0x1e160000
148
149 #define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
150 #define GPIO_PERST
151 #define ASSERT_SYSRST_PCIE(val) do { \
152 if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
153 RALINK_RSTCTRL |= val; \
154 else \
155 RALINK_RSTCTRL &= ~val; \
156 } while(0)
157 #define DEASSERT_SYSRST_PCIE(val) do { \
158 if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
159 RALINK_RSTCTRL &= ~val; \
160 else \
161 RALINK_RSTCTRL |= val; \
162 } while(0)
163 #define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
164 #define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
165 #define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
166 #define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
167 #define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
168 #define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
169 #define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
170 #define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
171 //RALINK_SYSCFG1 bit
172 #define RALINK_PCI_HOST_MODE_EN (1<<7)
173 #define RALINK_PCIE_RC_MODE_EN (1<<8)
174 //RALINK_RSTCTRL bit
175 #define RALINK_PCIE_RST (1<<23)
176 #define RALINK_PCI_RST (1<<24)
177 //RALINK_CLKCFG1 bit
178 #define RALINK_PCI_CLK_EN (1<<19)
179 #define RALINK_PCIE_CLK_EN (1<<21)
180 //RALINK_GPIOMODE bit
181 #define PCI_SLOTx2 (1<<11)
182 #define PCI_SLOTx1 (2<<11)
183 //MTK PCIE PLL bit
184 #define PDRV_SW_SET (1<<31)
185 #define LC_CKDRVPD_ (1<<19)
186
187 #define MEMORY_BASE 0x0
188 static int pcie_link_status = 0;
189
190 #define PCI_ACCESS_READ_1 0
191 #define PCI_ACCESS_READ_2 1
192 #define PCI_ACCESS_READ_4 2
193 #define PCI_ACCESS_WRITE_1 3
194 #define PCI_ACCESS_WRITE_2 4
195 #define PCI_ACCESS_WRITE_4 5
196
197 static int pcie_irq[3];
198
199 static int config_access(unsigned char access_type, struct pci_bus *bus,
200 unsigned int devfn, unsigned int where, u32 * data)
201 {
202 unsigned int slot = PCI_SLOT(devfn);
203 u8 func = PCI_FUNC(devfn);
204 uint32_t address_reg, data_reg;
205 unsigned int address;
206
207 address_reg = RALINK_PCI_CONFIG_ADDR;
208 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
209
210 address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
211 MV_WRITE(address_reg, address);
212
213 switch(access_type) {
214 case PCI_ACCESS_WRITE_1:
215 MV_WRITE_8(data_reg+(where&0x3), *data);
216 break;
217 case PCI_ACCESS_WRITE_2:
218 MV_WRITE_16(data_reg+(where&0x3), *data);
219 break;
220 case PCI_ACCESS_WRITE_4:
221 MV_WRITE(data_reg, *data);
222 break;
223 case PCI_ACCESS_READ_1:
224 MV_READ_8( data_reg+(where&0x3), data);
225 break;
226 case PCI_ACCESS_READ_2:
227 MV_READ_16(data_reg+(where&0x3), data);
228 break;
229 case PCI_ACCESS_READ_4:
230 MV_READ(data_reg, data);
231 break;
232 default:
233 printk("no specify access type\n");
234 break;
235 }
236 return 0;
237 }
238
239 static int
240 read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
241 {
242 return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
243 }
244
245 static int
246 read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
247 {
248 return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
249 }
250
251 static int
252 read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
253 {
254 return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
255 }
256
257 static int
258 write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
259 {
260 if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
261 return -1;
262
263 return PCIBIOS_SUCCESSFUL;
264 }
265
266 static int
267 write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
268 {
269 if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
270 return -1;
271
272 return PCIBIOS_SUCCESSFUL;
273 }
274
275 static int
276 write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
277 {
278 if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
279 return -1;
280
281 return PCIBIOS_SUCCESSFUL;
282 }
283
284
285 static int
286 pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
287 {
288 switch (size) {
289 case 1:
290 return read_config_byte(bus, devfn, where, (u8 *) val);
291 case 2:
292 return read_config_word(bus, devfn, where, (u16 *) val);
293 default:
294 return read_config_dword(bus, devfn, where, val);
295 }
296 }
297
298 static int
299 pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
300 {
301 switch (size) {
302 case 1:
303 return write_config_byte(bus, devfn, where, (u8) val);
304 case 2:
305 return write_config_word(bus, devfn, where, (u16) val);
306 default:
307 return write_config_dword(bus, devfn, where, val);
308 }
309 }
310
311 struct pci_ops mt7621_pci_ops= {
312 .read = pci_config_read,
313 .write = pci_config_write,
314 };
315
316 static struct resource mt7621_res_pci_mem1 = {
317 .name = "PCI MEM1",
318 .start = RALINK_PCI_MM_MAP_BASE,
319 .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
320 .flags = IORESOURCE_MEM,
321 };
322 static struct resource mt7621_res_pci_io1 = {
323 .name = "PCI I/O1",
324 .start = RALINK_PCI_IO_MAP_BASE,
325 .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
326 .flags = IORESOURCE_IO,
327 };
328
329 static struct pci_controller mt7621_controller = {
330 .pci_ops = &mt7621_pci_ops,
331 .mem_resource = &mt7621_res_pci_mem1,
332 .io_resource = &mt7621_res_pci_io1,
333 .mem_offset = 0x00000000UL,
334 .io_offset = 0x00000000UL,
335 .io_map_base = 0xa0000000,
336 };
337
338 static void
339 read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
340 {
341 unsigned int address_reg, data_reg, address;
342
343 address_reg = RALINK_PCI_CONFIG_ADDR;
344 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
345 address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
346 MV_WRITE(address_reg, address);
347 MV_READ(data_reg, val);
348 return;
349 }
350
351 static void
352 write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
353 {
354 unsigned int address_reg, data_reg, address;
355
356 address_reg = RALINK_PCI_CONFIG_ADDR;
357 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
358 address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
359 MV_WRITE(address_reg, address);
360 MV_WRITE(data_reg, val);
361 return;
362 }
363
364
365 int
366 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
367 {
368 u16 cmd;
369 u32 val;
370 int irq = 0;
371
372 if ((dev->bus->number == 0) && (slot == 0)) {
373 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
374 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
375 printk("BAR0 at slot 0 = %x\n", val);
376 printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
377 } else if((dev->bus->number == 0) && (slot == 0x1)) {
378 write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
379 read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
380 printk("BAR0 at slot 1 = %x\n", val);
381 printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
382 } else if((dev->bus->number == 0) && (slot == 0x2)) {
383 write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
384 read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
385 printk("BAR0 at slot 2 = %x\n", val);
386 printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
387 } else if ((dev->bus->number == 1) && (slot == 0x0)) {
388 switch (pcie_link_status) {
389 case 2:
390 case 6:
391 irq = RALINK_INT_PCIE1;
392 break;
393 case 4:
394 irq = RALINK_INT_PCIE2;
395 break;
396 default:
397 irq = RALINK_INT_PCIE0;
398 }
399 printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
400 } else if ((dev->bus->number == 2) && (slot == 0x0)) {
401 switch (pcie_link_status) {
402 case 5:
403 case 6:
404 irq = RALINK_INT_PCIE2;
405 break;
406 default:
407 irq = RALINK_INT_PCIE1;
408 }
409 printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
410 } else if ((dev->bus->number == 2) && (slot == 0x1)) {
411 switch (pcie_link_status) {
412 case 5:
413 case 6:
414 irq = RALINK_INT_PCIE2;
415 break;
416 default:
417 irq = RALINK_INT_PCIE1;
418 }
419 printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
420 } else if ((dev->bus->number ==3) && (slot == 0x0)) {
421 irq = RALINK_INT_PCIE2;
422 printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
423 } else if ((dev->bus->number ==3) && (slot == 0x1)) {
424 irq = RALINK_INT_PCIE2;
425 printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
426 } else if ((dev->bus->number ==3) && (slot == 0x2)) {
427 irq = RALINK_INT_PCIE2;
428 printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
429 } else {
430 printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
431 return 0;
432 }
433
434 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
435 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
436 pci_read_config_word(dev, PCI_COMMAND, &cmd);
437 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
438 pci_write_config_word(dev, PCI_COMMAND, cmd);
439 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
440 return irq;
441 }
442
443 void
444 set_pcie_phy(u32 *addr, int start_b, int bits, int val)
445 {
446 // printk("0x%p:", addr);
447 // printk(" %x", *addr);
448 *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
449 *(unsigned int *)(addr) |= val << start_b;
450 // printk(" -> %x\n", *addr);
451 }
452
453 void
454 bypass_pipe_rst(void)
455 {
456 #if defined (CONFIG_PCIE_PORT0)
457 /* PCIe Port 0 */
458 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
459 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
460 #endif
461 #if defined (CONFIG_PCIE_PORT1)
462 /* PCIe Port 1 */
463 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
464 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
465 #endif
466 #if defined (CONFIG_PCIE_PORT2)
467 /* PCIe Port 2 */
468 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
469 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
470 #endif
471 }
472
473 void
474 set_phy_for_ssc(void)
475 {
476 unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
477
478 reg = (reg >> 6) & 0x7;
479 #if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
480 /* Set PCIe Port0 & Port1 PHY to disable SSC */
481 /* Debug Xtal Type */
482 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
483 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
484 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
485 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
486 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
487 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
488 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
489 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
490 printk("***** Xtal 40MHz *****\n");
491 } else { // 25MHz | 20MHz Xtal
492 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
493 if (reg >= 6) {
494 printk("***** Xtal 25MHz *****\n");
495 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
496 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
497 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
498 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
499 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
500 } else {
501 printk("***** Xtal 20MHz *****\n");
502 }
503 }
504 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
505 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
506 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
507 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
508 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
509 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
510 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
511 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
512 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
513 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
514 }
515 /* Enable PHY and disable force mode */
516 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
517 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
518 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
519 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
520 #endif
521 #if defined (CONFIG_PCIE_PORT2)
522 /* Set PCIe Port2 PHY to disable SSC */
523 /* Debug Xtal Type */
524 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
525 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
526 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
527 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
528 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
529 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
530 } else { // 25MHz | 20MHz Xtal
531 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
532 if (reg >= 6) { // 25MHz Xtal
533 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
534 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
535 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
536 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
537 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
538 }
539 }
540 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
541 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
542 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
543 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
544 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
545 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
546 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
547 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
548 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
549 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
550 }
551 /* Enable PHY and disable force mode */
552 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
553 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
554 #endif
555 }
556
557 void setup_cm_memory_region(struct resource *mem_resource)
558 {
559 resource_size_t mask;
560 if (mips_cps_numiocu(0)) {
561 /* FIXME: hardware doesn't accept mask values with 1s after
562 0s (e.g. 0xffef), so it would be great to warn if that's
563 about to happen */
564 mask = ~(mem_resource->end - mem_resource->start);
565
566 write_gcr_reg1_base(mem_resource->start);
567 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
568 printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
569 read_gcr_reg1_base(),
570 read_gcr_reg1_mask());
571 }
572 }
573
574 static int mt7621_pci_probe(struct platform_device *pdev)
575 {
576 unsigned long val = 0;
577 int i;
578
579 for (i = 0; i < 3; i++)
580 pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
581
582 iomem_resource.start = 0;
583 iomem_resource.end= ~0;
584 ioport_resource.start= 0;
585 ioport_resource.end = ~0;
586
587 #if defined (CONFIG_PCIE_PORT0)
588 val = RALINK_PCIE0_RST;
589 #endif
590 #if defined (CONFIG_PCIE_PORT1)
591 val |= RALINK_PCIE1_RST;
592 #endif
593 #if defined (CONFIG_PCIE_PORT2)
594 val |= RALINK_PCIE2_RST;
595 #endif
596 ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
597 printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
598 #if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
599 *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
600 *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
601 mdelay(100);
602 *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
603 mdelay(100);
604 *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
605
606 mdelay(100);
607 #else
608 *(unsigned int *)(0xbe000060) &= ~0x00000c00;
609 #endif
610 #if defined (CONFIG_PCIE_PORT0)
611 val = RALINK_PCIE0_RST;
612 #endif
613 #if defined (CONFIG_PCIE_PORT1)
614 val |= RALINK_PCIE1_RST;
615 #endif
616 #if defined (CONFIG_PCIE_PORT2)
617 val |= RALINK_PCIE2_RST;
618 #endif
619 DEASSERT_SYSRST_PCIE(val);
620 printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
621
622 if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
623 bypass_pipe_rst();
624 set_phy_for_ssc();
625 printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
626
627 #if defined (CONFIG_PCIE_PORT0)
628 read_config(0, 0, 0, 0x70c, &val);
629 printk("Port 0 N_FTS = %x\n", (unsigned int)val);
630 #endif
631 #if defined (CONFIG_PCIE_PORT1)
632 read_config(0, 1, 0, 0x70c, &val);
633 printk("Port 1 N_FTS = %x\n", (unsigned int)val);
634 #endif
635 #if defined (CONFIG_PCIE_PORT2)
636 read_config(0, 2, 0, 0x70c, &val);
637 printk("Port 2 N_FTS = %x\n", (unsigned int)val);
638 #endif
639
640 RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
641 RALINK_SYSCFG1 &= ~(0x30);
642 RALINK_SYSCFG1 |= (2<<4);
643 RALINK_PCIE_CLK_GEN &= 0x7fffffff;
644 RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
645 RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
646 RALINK_PCIE_CLK_GEN |= 0x80000000;
647 mdelay(50);
648 RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
649
650
651 #if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
652 *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
653 mdelay(100);
654 #else
655 RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
656 #endif
657 mdelay(500);
658
659
660 mdelay(500);
661 #if defined (CONFIG_PCIE_PORT0)
662 if(( RALINK_PCI0_STATUS & 0x1) == 0)
663 {
664 printk("PCIE0 no card, disable it(RST&CLK)\n");
665 ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
666 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
667 pcie_link_status &= ~(1<<0);
668 } else {
669 pcie_link_status |= 1<<0;
670 RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
671 }
672 #endif
673 #if defined (CONFIG_PCIE_PORT1)
674 if(( RALINK_PCI1_STATUS & 0x1) == 0)
675 {
676 printk("PCIE1 no card, disable it(RST&CLK)\n");
677 ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
678 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
679 pcie_link_status &= ~(1<<1);
680 } else {
681 pcie_link_status |= 1<<1;
682 RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
683 }
684 #endif
685 #if defined (CONFIG_PCIE_PORT2)
686 if (( RALINK_PCI2_STATUS & 0x1) == 0) {
687 printk("PCIE2 no card, disable it(RST&CLK)\n");
688 ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
689 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
690 pcie_link_status &= ~(1<<2);
691 } else {
692 pcie_link_status |= 1<<2;
693 RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
694 }
695 #endif
696 if (pcie_link_status == 0)
697 return 0;
698
699 /*
700 pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
701 3'b000 x x x
702 3'b001 x x 0
703 3'b010 x 0 x
704 3'b011 x 1 0
705 3'b100 0 x x
706 3'b101 1 x 0
707 3'b110 1 0 x
708 3'b111 2 1 0
709 */
710 switch(pcie_link_status) {
711 case 2:
712 RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
713 RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
714 RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
715 break;
716 case 4:
717 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
718 RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
719 RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
720 RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
721 break;
722 case 5:
723 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
724 RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
725 RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
726 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
727 break;
728 case 6:
729 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
730 RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
731 RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
732 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
733 break;
734 }
735 printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
736 //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
737
738 /*
739 ioport_resource.start = mt7621_res_pci_io1.start;
740 ioport_resource.end = mt7621_res_pci_io1.end;
741 */
742
743 RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
744 RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
745
746 #if defined (CONFIG_PCIE_PORT0)
747 //PCIe0
748 if((pcie_link_status & 0x1) != 0) {
749 RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
750 RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
751 RALINK_PCI0_CLASS = 0x06040001;
752 printk("PCIE0 enabled\n");
753 }
754 #endif
755 #if defined (CONFIG_PCIE_PORT1)
756 //PCIe1
757 if ((pcie_link_status & 0x2) != 0) {
758 RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
759 RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
760 RALINK_PCI1_CLASS = 0x06040001;
761 printk("PCIE1 enabled\n");
762 }
763 #endif
764 #if defined (CONFIG_PCIE_PORT2)
765 //PCIe2
766 if ((pcie_link_status & 0x4) != 0) {
767 RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
768 RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
769 RALINK_PCI2_CLASS = 0x06040001;
770 printk("PCIE2 enabled\n");
771 }
772 #endif
773
774
775 switch(pcie_link_status) {
776 case 7:
777 read_config(0, 2, 0, 0x4, &val);
778 write_config(0, 2, 0, 0x4, val|0x4);
779 // write_config(0, 1, 0, 0x4, val|0x7);
780 read_config(0, 2, 0, 0x70c, &val);
781 val &= ~(0xff)<<8;
782 val |= 0x50<<8;
783 write_config(0, 2, 0, 0x70c, val);
784 case 3:
785 case 5:
786 case 6:
787 read_config(0, 1, 0, 0x4, &val);
788 write_config(0, 1, 0, 0x4, val|0x4);
789 // write_config(0, 1, 0, 0x4, val|0x7);
790 read_config(0, 1, 0, 0x70c, &val);
791 val &= ~(0xff)<<8;
792 val |= 0x50<<8;
793 write_config(0, 1, 0, 0x70c, val);
794 default:
795 read_config(0, 0, 0, 0x4, &val);
796 write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
797 // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
798 read_config(0, 0, 0, 0x70c, &val);
799 val &= ~(0xff)<<8;
800 val |= 0x50<<8;
801 write_config(0, 0, 0, 0x70c, val);
802 }
803
804 pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
805 setup_cm_memory_region(mt7621_controller.mem_resource);
806 register_pci_controller(&mt7621_controller);
807 return 0;
808
809 }
810
811 int pcibios_plat_dev_init(struct pci_dev *dev)
812 {
813 return 0;
814 }
815
816 static const struct of_device_id mt7621_pci_ids[] = {
817 { .compatible = "mediatek,mt7621-pci" },
818 {},
819 };
820 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
821
822 static struct platform_driver mt7621_pci_driver = {
823 .probe = mt7621_pci_probe,
824 .driver = {
825 .name = "mt7621-pci",
826 .of_match_table = of_match_ptr(mt7621_pci_ids),
827 },
828 };
829
830 static int __init mt7621_pci_init(void)
831 {
832 return platform_driver_register(&mt7621_pci_driver);
833 }
834
835 arch_initcall(mt7621_pci_init);
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