projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Revert "ramips: pci: sync with staging driver"
[openwrt/openwrt.git] / target / linux / ramips / files-4.14 / arch / mips / pci / pci-mt7621.c
1 /**************************************************************************
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
5 *
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 *
29 **************************************************************************
30 * May 2007 Bruce Chang
31 * Initial Release
32 *
33 * May 2009 Bruce Chang
34 * support RT2880/RT3883 PCIe
35 *
36 * May 2011 Bruce Chang
37 * support RT6855/MT7620 PCIe
38 *
39 **************************************************************************
40 */
41
42 #include <linux/types.h>
43 #include <linux/pci.h>
44 #include <linux/kernel.h>
45 #include <linux/slab.h>
46 #include <linux/version.h>
47 #include <asm/pci.h>
48 #include <asm/io.h>
49 #include <asm/mips-cm.h>
50 #include <linux/init.h>
51 #include <linux/module.h>
52 #include <linux/delay.h>
53 #include <linux/of.h>
54 #include <linux/of_pci.h>
55 #include <linux/of_irq.h>
56 #include <linux/platform_device.h>
57
58 #include <ralink_regs.h>
59
60 extern void pcie_phy_init(void);
61 extern void chk_phy_pll(void);
62
63 /*
64 * These functions and structures provide the BIOS scan and mapping of the PCI
65 * devices.
66 */
67
68 #define RALINK_PCIE0_CLK_EN (1<<24)
69 #define RALINK_PCIE1_CLK_EN (1<<25)
70 #define RALINK_PCIE2_CLK_EN (1<<26)
71
72 #define RALINK_PCI_CONFIG_ADDR 0x20
73 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
74 #define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
75 #define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
76 #define RALINK_PCIE0_RST (1<<24)
77 #define RALINK_PCIE1_RST (1<<25)
78 #define RALINK_PCIE2_RST (1<<26)
79 #define RALINK_SYSCTL_BASE 0xBE000000
80
81 #define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
82 #define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
83 #define RALINK_PCI_BASE 0xBE140000
84
85 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
86 #define RT6855_PCIE0_OFFSET 0x2000
87 #define RT6855_PCIE1_OFFSET 0x3000
88 #define RT6855_PCIE2_OFFSET 0x4000
89
90 #define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
91 #define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
92 #define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
93 #define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
94 #define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
95 #define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
96 #define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
97 #define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
98
99 #define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
100 #define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
101 #define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
102 #define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
103 #define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
104 #define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
105 #define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
106 #define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
107
108 #define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
109 #define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
110 #define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
111 #define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
112 #define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
113 #define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
114 #define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
115 #define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
116
117 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
118 #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
119
120
121 #define MV_WRITE(ofs, data) \
122 *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
123 #define MV_READ(ofs, data) \
124 *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
125 #define MV_READ_DATA(ofs) \
126 le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
127
128 #define MV_WRITE_16(ofs, data) \
129 *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
130 #define MV_READ_16(ofs, data) \
131 *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
132
133 #define MV_WRITE_8(ofs, data) \
134 *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
135 #define MV_READ_8(ofs, data) \
136 *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
137
138
139
140 #define RALINK_PCI_MM_MAP_BASE 0x60000000
141 #define RALINK_PCI_IO_MAP_BASE 0x1e160000
142
143 #define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
144
145 #define ASSERT_SYSRST_PCIE(val) do { \
146 if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
147 RALINK_RSTCTRL |= val; \
148 else \
149 RALINK_RSTCTRL &= ~val; \
150 } while(0)
151 #define DEASSERT_SYSRST_PCIE(val) do { \
152 if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
153 RALINK_RSTCTRL &= ~val; \
154 else \
155 RALINK_RSTCTRL |= val; \
156 } while(0)
157 #define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
158 #define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
159 #define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
160 #define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
161 #define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
162 #define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
163 #define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
164 #define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
165 //RALINK_SYSCFG1 bit
166 #define RALINK_PCI_HOST_MODE_EN (1<<7)
167 #define RALINK_PCIE_RC_MODE_EN (1<<8)
168 //RALINK_RSTCTRL bit
169 #define RALINK_PCIE_RST (1<<23)
170 #define RALINK_PCI_RST (1<<24)
171 //RALINK_CLKCFG1 bit
172 #define RALINK_PCI_CLK_EN (1<<19)
173 #define RALINK_PCIE_CLK_EN (1<<21)
174 //RALINK_GPIOMODE bit
175 #define PCI_SLOTx2 (1<<11)
176 #define PCI_SLOTx1 (2<<11)
177 //MTK PCIE PLL bit
178 #define PDRV_SW_SET (1<<31)
179 #define LC_CKDRVPD_ (1<<19)
180
181 #define MEMORY_BASE 0x0
182 static int pcie_link_status = 0;
183
184 #define PCI_ACCESS_READ_1 0
185 #define PCI_ACCESS_READ_2 1
186 #define PCI_ACCESS_READ_4 2
187 #define PCI_ACCESS_WRITE_1 3
188 #define PCI_ACCESS_WRITE_2 4
189 #define PCI_ACCESS_WRITE_4 5
190
191 static int pcie_irq[3];
192
193 static int config_access(unsigned char access_type, struct pci_bus *bus,
194 unsigned int devfn, unsigned int where, u32 * data)
195 {
196 unsigned int slot = PCI_SLOT(devfn);
197 u8 func = PCI_FUNC(devfn);
198 uint32_t address_reg, data_reg;
199 unsigned int address;
200
201 address_reg = RALINK_PCI_CONFIG_ADDR;
202 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
203
204 address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
205 MV_WRITE(address_reg, address);
206
207 switch(access_type) {
208 case PCI_ACCESS_WRITE_1:
209 MV_WRITE_8(data_reg+(where&0x3), *data);
210 break;
211 case PCI_ACCESS_WRITE_2:
212 MV_WRITE_16(data_reg+(where&0x3), *data);
213 break;
214 case PCI_ACCESS_WRITE_4:
215 MV_WRITE(data_reg, *data);
216 break;
217 case PCI_ACCESS_READ_1:
218 MV_READ_8( data_reg+(where&0x3), data);
219 break;
220 case PCI_ACCESS_READ_2:
221 MV_READ_16(data_reg+(where&0x3), data);
222 break;
223 case PCI_ACCESS_READ_4:
224 MV_READ(data_reg, data);
225 break;
226 default:
227 printk("no specify access type\n");
228 break;
229 }
230 return 0;
231 }
232
233 static int
234 read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
235 {
236 return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
237 }
238
239 static int
240 read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
241 {
242 return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
243 }
244
245 static int
246 read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
247 {
248 return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
249 }
250
251 static int
252 write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
253 {
254 if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
255 return -1;
256
257 return PCIBIOS_SUCCESSFUL;
258 }
259
260 static int
261 write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
262 {
263 if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
264 return -1;
265
266 return PCIBIOS_SUCCESSFUL;
267 }
268
269 static int
270 write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
271 {
272 if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
273 return -1;
274
275 return PCIBIOS_SUCCESSFUL;
276 }
277
278
279 static int
280 pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
281 {
282 switch (size) {
283 case 1:
284 return read_config_byte(bus, devfn, where, (u8 *) val);
285 case 2:
286 return read_config_word(bus, devfn, where, (u16 *) val);
287 default:
288 return read_config_dword(bus, devfn, where, val);
289 }
290 }
291
292 static int
293 pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
294 {
295 switch (size) {
296 case 1:
297 return write_config_byte(bus, devfn, where, (u8) val);
298 case 2:
299 return write_config_word(bus, devfn, where, (u16) val);
300 default:
301 return write_config_dword(bus, devfn, where, val);
302 }
303 }
304
305 struct pci_ops mt7621_pci_ops= {
306 .read = pci_config_read,
307 .write = pci_config_write,
308 };
309
310 static struct resource mt7621_res_pci_mem1;
311 static struct resource mt7621_res_pci_io1;
312
313 static struct pci_controller mt7621_controller = {
314 .pci_ops = &mt7621_pci_ops,
315 .mem_resource = &mt7621_res_pci_mem1,
316 .io_resource = &mt7621_res_pci_io1,
317 };
318
319 static void
320 read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
321 {
322 unsigned int address_reg, data_reg, address;
323
324 address_reg = RALINK_PCI_CONFIG_ADDR;
325 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
326 address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
327 MV_WRITE(address_reg, address);
328 MV_READ(data_reg, val);
329 return;
330 }
331
332 static void
333 write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
334 {
335 unsigned int address_reg, data_reg, address;
336
337 address_reg = RALINK_PCI_CONFIG_ADDR;
338 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
339 address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
340 MV_WRITE(address_reg, address);
341 MV_WRITE(data_reg, val);
342 return;
343 }
344
345
346 int
347 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
348 {
349 u16 cmd;
350 u32 val;
351 int irq;
352
353 if (dev->bus->number == 0) {
354 write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
355 read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
356 printk("BAR0 at slot %d = %x\n", slot, val);
357 }
358
359 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
360 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
361 pci_read_config_word(dev, PCI_COMMAND, &cmd);
362 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
363 pci_write_config_word(dev, PCI_COMMAND, cmd);
364
365 irq = of_irq_parse_and_map_pci(dev, slot, pin);
366
367 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
368 return irq;
369 }
370
371 void
372 set_pcie_phy(u32 *addr, int start_b, int bits, int val)
373 {
374 // printk("0x%p:", addr);
375 // printk(" %x", *addr);
376 *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
377 *(unsigned int *)(addr) |= val << start_b;
378 // printk(" -> %x\n", *addr);
379 }
380
381 void
382 bypass_pipe_rst(void)
383 {
384 /* PCIe Port 0 */
385 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
386 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
387 /* PCIe Port 1 */
388 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
389 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
390 /* PCIe Port 2 */
391 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
392 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
393 }
394
395 void
396 set_phy_for_ssc(void)
397 {
398 unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
399
400 reg = (reg >> 6) & 0x7;
401 /* Set PCIe Port0 & Port1 PHY to disable SSC */
402 /* Debug Xtal Type */
403 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
404 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
405 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
406 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
407 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
408 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
409 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
410 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
411 printk("***** Xtal 40MHz *****\n");
412 } else { // 25MHz | 20MHz Xtal
413 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
414 if (reg >= 6) {
415 printk("***** Xtal 25MHz *****\n");
416 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
417 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
418 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
419 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
420 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
421 } else {
422 printk("***** Xtal 20MHz *****\n");
423 }
424 }
425 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
426 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
427 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
428 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
429 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
430 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
431 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
432 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
433 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
434 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
435 }
436 /* Enable PHY and disable force mode */
437 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
438 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
439 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
440 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
441
442 /* Set PCIe Port2 PHY to disable SSC */
443 /* Debug Xtal Type */
444 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
445 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
446 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
447 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
448 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
449 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
450 } else { // 25MHz | 20MHz Xtal
451 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
452 if (reg >= 6) { // 25MHz Xtal
453 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
454 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
455 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
456 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
457 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
458 }
459 }
460 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
461 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
462 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
463 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
464 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
465 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
466 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
467 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
468 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
469 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
470 }
471 /* Enable PHY and disable force mode */
472 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
473 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
474 }
475
476 void setup_cm_memory_region(struct resource *mem_resource)
477 {
478 resource_size_t mask;
479 if (mips_cps_numiocu(0)) {
480 /* FIXME: hardware doesn't accept mask values with 1s after
481 0s (e.g. 0xffef), so it would be great to warn if that's
482 about to happen */
483 mask = ~(mem_resource->end - mem_resource->start);
484
485 write_gcr_reg1_base(mem_resource->start);
486 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
487 printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
488 read_gcr_reg1_base(),
489 read_gcr_reg1_mask());
490 }
491 }
492
493 static int mt7621_pci_probe(struct platform_device *pdev)
494 {
495 unsigned long val = 0;
496 int i;
497
498 for (i = 0; i < 3; i++)
499 pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
500
501 iomem_resource.start = 0;
502 iomem_resource.end= ~0;
503 ioport_resource.start= 0;
504 ioport_resource.end = ~0;
505
506 val = RALINK_PCIE0_RST;
507 val |= RALINK_PCIE1_RST;
508 val |= RALINK_PCIE2_RST;
509
510 ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
511 printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
512
513 *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
514 *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
515 mdelay(100);
516 *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
517 mdelay(100);
518 *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
519
520 mdelay(100);
521
522 val = RALINK_PCIE0_RST;
523 val |= RALINK_PCIE1_RST;
524 val |= RALINK_PCIE2_RST;
525
526 DEASSERT_SYSRST_PCIE(val);
527 printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
528
529 if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
530 bypass_pipe_rst();
531 set_phy_for_ssc();
532 printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
533
534 read_config(0, 0, 0, 0x70c, &val);
535 printk("Port 0 N_FTS = %x\n", (unsigned int)val);
536 read_config(0, 1, 0, 0x70c, &val);
537 printk("Port 1 N_FTS = %x\n", (unsigned int)val);
538 read_config(0, 2, 0, 0x70c, &val);
539 printk("Port 2 N_FTS = %x\n", (unsigned int)val);
540
541 RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
542 RALINK_SYSCFG1 &= ~(0x30);
543 RALINK_SYSCFG1 |= (2<<4);
544 RALINK_PCIE_CLK_GEN &= 0x7fffffff;
545 RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
546 RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
547 RALINK_PCIE_CLK_GEN |= 0x80000000;
548 mdelay(50);
549 RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
550
551 /* Use GPIO control instead of PERST_N */
552 *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
553 mdelay(1000);
554
555 if(( RALINK_PCI0_STATUS & 0x1) == 0)
556 {
557 printk("PCIE0 no card, disable it(RST&CLK)\n");
558 ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
559 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
560 pcie_link_status &= ~(1<<0);
561 } else {
562 pcie_link_status |= 1<<0;
563 RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
564 }
565 if(( RALINK_PCI1_STATUS & 0x1) == 0)
566 {
567 printk("PCIE1 no card, disable it(RST&CLK)\n");
568 ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
569 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
570 pcie_link_status &= ~(1<<1);
571 } else {
572 pcie_link_status |= 1<<1;
573 RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
574 }
575 if (( RALINK_PCI2_STATUS & 0x1) == 0) {
576 printk("PCIE2 no card, disable it(RST&CLK)\n");
577 ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
578 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
579 pcie_link_status &= ~(1<<2);
580 } else {
581 pcie_link_status |= 1<<2;
582 RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
583 }
584 if (pcie_link_status == 0)
585 return 0;
586
587 /*
588 pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
589 3'b000 x x x
590 3'b001 x x 0
591 3'b010 x 0 x
592 3'b011 x 1 0
593 3'b100 0 x x
594 3'b101 1 x 0
595 3'b110 1 0 x
596 3'b111 2 1 0
597 */
598 switch(pcie_link_status) {
599 case 2:
600 RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
601 RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
602 RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
603 break;
604 case 4:
605 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
606 RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
607 RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
608 RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
609 break;
610 case 5:
611 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
612 RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
613 RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
614 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
615 break;
616 case 6:
617 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
618 RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
619 RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
620 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
621 break;
622 }
623 printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
624 //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
625
626 /*
627 ioport_resource.start = mt7621_res_pci_io1.start;
628 ioport_resource.end = mt7621_res_pci_io1.end;
629 */
630
631 RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
632 RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
633
634 //PCIe0
635 if((pcie_link_status & 0x1) != 0) {
636 RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
637 RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
638 RALINK_PCI0_CLASS = 0x06040001;
639 printk("PCIE0 enabled\n");
640 }
641 //PCIe1
642 if ((pcie_link_status & 0x2) != 0) {
643 RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
644 RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
645 RALINK_PCI1_CLASS = 0x06040001;
646 printk("PCIE1 enabled\n");
647 }
648 //PCIe2
649 if ((pcie_link_status & 0x4) != 0) {
650 RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
651 RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
652 RALINK_PCI2_CLASS = 0x06040001;
653 printk("PCIE2 enabled\n");
654 }
655
656 switch(pcie_link_status) {
657 case 7:
658 read_config(0, 2, 0, 0x4, &val);
659 write_config(0, 2, 0, 0x4, val|0x4);
660 // write_config(0, 1, 0, 0x4, val|0x7);
661 read_config(0, 2, 0, 0x70c, &val);
662 val &= ~(0xff)<<8;
663 val |= 0x50<<8;
664 write_config(0, 2, 0, 0x70c, val);
665 case 3:
666 case 5:
667 case 6:
668 read_config(0, 1, 0, 0x4, &val);
669 write_config(0, 1, 0, 0x4, val|0x4);
670 // write_config(0, 1, 0, 0x4, val|0x7);
671 read_config(0, 1, 0, 0x70c, &val);
672 val &= ~(0xff)<<8;
673 val |= 0x50<<8;
674 write_config(0, 1, 0, 0x70c, val);
675 default:
676 read_config(0, 0, 0, 0x4, &val);
677 write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
678 // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
679 read_config(0, 0, 0, 0x70c, &val);
680 val &= ~(0xff)<<8;
681 val |= 0x50<<8;
682 write_config(0, 0, 0, 0x70c, val);
683 }
684
685 pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
686 setup_cm_memory_region(mt7621_controller.mem_resource);
687 register_pci_controller(&mt7621_controller);
688 return 0;
689
690 }
691
692 int pcibios_plat_dev_init(struct pci_dev *dev)
693 {
694 return 0;
695 }
696
697 static const struct of_device_id mt7621_pci_ids[] = {
698 { .compatible = "mediatek,mt7621-pci" },
699 {},
700 };
701 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
702
703 static struct platform_driver mt7621_pci_driver = {
704 .probe = mt7621_pci_probe,
705 .driver = {
706 .name = "mt7621-pci",
707 .of_match_table = of_match_ptr(mt7621_pci_ids),
708 },
709 };
710
711 static int __init mt7621_pci_init(void)
712 {
713 return platform_driver_register(&mt7621_pci_driver);
714 }
715
716 arch_initcall(mt7621_pci_init);
OpenWrt Source Repository