a3c50d0528bc305c60f8b53ef472e47d78595e40
[openwrt/openwrt.git] / target / linux / ramips / files-4.14 / drivers / mmc / host / mtk-mmc / mt6575_sd.h
1 /* Copyright Statement:
2 *
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly prohibited.
9 */
10 /* MediaTek Inc. (C) 2010. All rights reserved.
11 *
12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
30 *
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
34 */
35
36 #ifndef MT6575_SD_H
37 #define MT6575_SD_H
38
39 #include <linux/bitops.h>
40 #include <linux/mmc/host.h>
41
42 // #include <mach/mt6575_reg_base.h> /* --- by chhung */
43
44 /*--------------------------------------------------------------------------*/
45 /* Common Macro */
46 /*--------------------------------------------------------------------------*/
47 #define REG_ADDR(x) (base + OFFSET_##x)
48
49 /*--------------------------------------------------------------------------*/
50 /* Common Definition */
51 /*--------------------------------------------------------------------------*/
52 #define MSDC_FIFO_SZ (128)
53 #define MSDC_FIFO_THD (64) // (128)
54 #define MSDC_NUM (4)
55
56 #define MSDC_MS (0)
57 #define MSDC_SDMMC (1)
58
59 #define MSDC_MODE_UNKNOWN (0)
60 #define MSDC_MODE_PIO (1)
61 #define MSDC_MODE_DMA_BASIC (2)
62 #define MSDC_MODE_DMA_DESC (3)
63 #define MSDC_MODE_DMA_ENHANCED (4)
64 #define MSDC_MODE_MMC_STREAM (5)
65
66 #define MSDC_BUS_1BITS (0)
67 #define MSDC_BUS_4BITS (1)
68 #define MSDC_BUS_8BITS (2)
69
70 #define MSDC_BRUST_8B (3)
71 #define MSDC_BRUST_16B (4)
72 #define MSDC_BRUST_32B (5)
73 #define MSDC_BRUST_64B (6)
74
75 #define MSDC_PIN_PULL_NONE (0)
76 #define MSDC_PIN_PULL_DOWN (1)
77 #define MSDC_PIN_PULL_UP (2)
78 #define MSDC_PIN_KEEP (3)
79
80 #define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
81 #define MSDC_MIN_SCLK (260000)
82
83 #define MSDC_AUTOCMD12 (0x0001)
84 #define MSDC_AUTOCMD23 (0x0002)
85 #define MSDC_AUTOCMD19 (0x0003)
86
87 #define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
88 #define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
89
90 enum {
91 RESP_NONE = 0,
92 RESP_R1,
93 RESP_R2,
94 RESP_R3,
95 RESP_R4,
96 RESP_R5,
97 RESP_R6,
98 RESP_R7,
99 RESP_R1B
100 };
101
102 /*--------------------------------------------------------------------------*/
103 /* Register Offset */
104 /*--------------------------------------------------------------------------*/
105 #define OFFSET_MSDC_CFG (0x0)
106 #define OFFSET_MSDC_IOCON (0x04)
107 #define OFFSET_MSDC_PS (0x08)
108 #define OFFSET_MSDC_INT (0x0c)
109 #define OFFSET_MSDC_INTEN (0x10)
110 #define OFFSET_MSDC_FIFOCS (0x14)
111 #define OFFSET_MSDC_TXDATA (0x18)
112 #define OFFSET_MSDC_RXDATA (0x1c)
113 #define OFFSET_SDC_CFG (0x30)
114 #define OFFSET_SDC_CMD (0x34)
115 #define OFFSET_SDC_ARG (0x38)
116 #define OFFSET_SDC_STS (0x3c)
117 #define OFFSET_SDC_RESP0 (0x40)
118 #define OFFSET_SDC_RESP1 (0x44)
119 #define OFFSET_SDC_RESP2 (0x48)
120 #define OFFSET_SDC_RESP3 (0x4c)
121 #define OFFSET_SDC_BLK_NUM (0x50)
122 #define OFFSET_SDC_CSTS (0x58)
123 #define OFFSET_SDC_CSTS_EN (0x5c)
124 #define OFFSET_SDC_DCRC_STS (0x60)
125 #define OFFSET_EMMC_CFG0 (0x70)
126 #define OFFSET_EMMC_CFG1 (0x74)
127 #define OFFSET_EMMC_STS (0x78)
128 #define OFFSET_EMMC_IOCON (0x7c)
129 #define OFFSET_SDC_ACMD_RESP (0x80)
130 #define OFFSET_SDC_ACMD19_TRG (0x84)
131 #define OFFSET_SDC_ACMD19_STS (0x88)
132 #define OFFSET_MSDC_DMA_SA (0x90)
133 #define OFFSET_MSDC_DMA_CA (0x94)
134 #define OFFSET_MSDC_DMA_CTRL (0x98)
135 #define OFFSET_MSDC_DMA_CFG (0x9c)
136 #define OFFSET_MSDC_DBG_SEL (0xa0)
137 #define OFFSET_MSDC_DBG_OUT (0xa4)
138 #define OFFSET_MSDC_PATCH_BIT (0xb0)
139 #define OFFSET_MSDC_PATCH_BIT1 (0xb4)
140 #define OFFSET_MSDC_PAD_CTL0 (0xe0)
141 #define OFFSET_MSDC_PAD_CTL1 (0xe4)
142 #define OFFSET_MSDC_PAD_CTL2 (0xe8)
143 #define OFFSET_MSDC_PAD_TUNE (0xec)
144 #define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
145 #define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
146 #define OFFSET_MSDC_HW_DBG (0xf8)
147 #define OFFSET_MSDC_VERSION (0x100)
148 #define OFFSET_MSDC_ECO_VER (0x104)
149
150 /*--------------------------------------------------------------------------*/
151 /* Register Address */
152 /*--------------------------------------------------------------------------*/
153
154 /* common register */
155 #define MSDC_CFG REG_ADDR(MSDC_CFG)
156 #define MSDC_IOCON REG_ADDR(MSDC_IOCON)
157 #define MSDC_PS REG_ADDR(MSDC_PS)
158 #define MSDC_INT REG_ADDR(MSDC_INT)
159 #define MSDC_INTEN REG_ADDR(MSDC_INTEN)
160 #define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
161 #define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
162 #define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
163 #define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
164
165 /* sdmmc register */
166 #define SDC_CFG REG_ADDR(SDC_CFG)
167 #define SDC_CMD REG_ADDR(SDC_CMD)
168 #define SDC_ARG REG_ADDR(SDC_ARG)
169 #define SDC_STS REG_ADDR(SDC_STS)
170 #define SDC_RESP0 REG_ADDR(SDC_RESP0)
171 #define SDC_RESP1 REG_ADDR(SDC_RESP1)
172 #define SDC_RESP2 REG_ADDR(SDC_RESP2)
173 #define SDC_RESP3 REG_ADDR(SDC_RESP3)
174 #define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
175 #define SDC_CSTS REG_ADDR(SDC_CSTS)
176 #define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
177 #define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
178
179 /* emmc register*/
180 #define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
181 #define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
182 #define EMMC_STS REG_ADDR(EMMC_STS)
183 #define EMMC_IOCON REG_ADDR(EMMC_IOCON)
184
185 /* auto command register */
186 #define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
187 #define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
188 #define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
189
190 /* dma register */
191 #define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
192 #define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
193 #define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
194 #define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
195
196 /* pad ctrl register */
197 #define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
198 #define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
199 #define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
200
201 /* data read delay */
202 #define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
203 #define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
204
205 /* debug register */
206 #define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
207 #define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
208
209 /* misc register */
210 #define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
211 #define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
212 #define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
213 #define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
214 #define MSDC_VERSION REG_ADDR(MSDC_VERSION)
215 #define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
216
217 /*--------------------------------------------------------------------------*/
218 /* Register Mask */
219 /*--------------------------------------------------------------------------*/
220
221 /* MSDC_CFG mask */
222 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
223 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
224 #define MSDC_CFG_RST (0x1 << 2) /* RW */
225 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
226 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
227 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
228 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
229 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */
230 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
231 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
232
233 /* MSDC_IOCON mask */
234 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
235 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
236 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
237 #define MSDC_IOCON_WDSPL (0x1 << 8) /* RW */
238 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
239 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
240 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
241 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
242 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
243 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
244 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
245 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
246 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
247 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
248 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
249 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
250
251 /* MSDC_PS mask */
252 #define MSDC_PS_CDEN (0x1 << 0) /* RW */
253 #define MSDC_PS_CDSTS (0x1 << 1) /* R */
254 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
255 #define MSDC_PS_DAT (0xff << 16) /* R */
256 #define MSDC_PS_CMD (0x1 << 24) /* R */
257 #define MSDC_PS_WP (0x1UL << 31) /* R */
258
259 /* MSDC_INT mask */
260 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
261 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */
262 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
263 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
264 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
265 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
266 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
267 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
268 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
269 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
270 #define MSDC_INT_CSTA (0x1 << 11) /* R */
271 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
272 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
273 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
274 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
275 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
276
277 /* MSDC_INTEN mask */
278 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
279 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
280 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
281 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
282 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
283 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
284 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
285 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
286 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
287 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
288 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
289 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
290 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
291 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
292 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
293 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
294
295 /* MSDC_FIFOCS mask */
296 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
297 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
298 #define MSDC_FIFOCS_CLR (0x1UL << 31) /* RW */
299
300 /* SDC_CFG mask */
301 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
302 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
303 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
304 #define SDC_CFG_SDIO (0x1 << 19) /* RW */
305 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
306 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
307 #define SDC_CFG_DTOC (0xffUL << 24) /* RW */
308
309 /* SDC_CMD mask */
310 #define SDC_CMD_OPC (0x3f << 0) /* RW */
311 #define SDC_CMD_BRK (0x1 << 6) /* RW */
312 #define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
313 #define SDC_CMD_DTYP (0x3 << 11) /* RW */
314 #define SDC_CMD_DTYP (0x3 << 11) /* RW */
315 #define SDC_CMD_RW (0x1 << 13) /* RW */
316 #define SDC_CMD_STOP (0x1 << 14) /* RW */
317 #define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
318 #define SDC_CMD_BLKLEN (0xfff << 16) /* RW */
319 #define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
320 #define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
321
322 /* SDC_STS mask */
323 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
324 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
325 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
326
327 /* SDC_DCRC_STS mask */
328 #define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
329 #define SDC_DCRC_STS_POS (0xff << 0) /* RO */
330
331 /* EMMC_CFG0 mask */
332 #define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
333 #define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
334 #define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
335 #define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
336 #define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
337 #define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
338
339 /* EMMC_CFG1 mask */
340 #define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
341 #define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
342
343 /* EMMC_STS mask */
344 #define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
345 #define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
346 #define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
347 #define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
348 #define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
349 #define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
350 #define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
351
352 /* EMMC_IOCON mask */
353 #define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
354
355 /* SDC_ACMD19_TRG mask */
356 #define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
357
358 /* MSDC_DMA_CTRL mask */
359 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
360 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
361 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
362 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
363 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
364 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
365 #define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
366
367 /* MSDC_DMA_CFG mask */
368 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
369 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
370 #define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
371 #define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
372
373 /* MSDC_PATCH_BIT mask */
374 #define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
375 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
376 #define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
377 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
378 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
379 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
380 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
381 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
382 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
383 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
384 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
385 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
386
387 /* MSDC_PATCH_BIT1 mask */
388 #define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
389 #define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
390
391 /* MSDC_PAD_CTL0 mask */
392 #define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
393 #define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
394 #define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
395 #define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
396 #define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
397 #define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
398 #define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
399 #define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
400 #define MSDC_PAD_CTL0_CLKRDSEL (0xffUL << 24) /* RW */
401
402 /* MSDC_PAD_CTL1 mask */
403 #define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
404 #define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
405 #define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
406 #define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
407 #define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
408 #define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
409 #define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
410 #define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
411 #define MSDC_PAD_CTL1_CMDRDSEL (0xffUL << 24) /* RW */
412
413 /* MSDC_PAD_CTL2 mask */
414 #define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
415 #define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
416 #define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
417 #define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
418 #define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
419 #define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
420 #define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
421 #define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
422 #define MSDC_PAD_CTL2_DATRDSEL (0xffUL << 24) /* RW */
423
424 /* MSDC_PAD_TUNE mask */
425 #define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
426 #define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
427 #define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
428 #define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
429 #define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
430
431 /* MSDC_DAT_RDDLY0/1 mask */
432 #define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
433 #define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
434 #define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
435 #define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
436
437 #define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
438 #define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
439 #define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
440 #define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
441
442 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1F << 10)
443 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7)
444 #define MSDC_CKGEN_MSDC_CK_SEL (0x1 << 6)
445 #define CARD_READY_FOR_DATA (1 << 8)
446 #define CARD_CURRENT_STATE(x) ((x & 0x00001E00) >> 9)
447
448 /*--------------------------------------------------------------------------*/
449 /* Descriptor Structure */
450 /*--------------------------------------------------------------------------*/
451 struct gpd {
452 u32 hwo:1; /* could be changed by hw */
453 u32 bdp:1;
454 u32 rsv0:6;
455 u32 chksum:8;
456 u32 intr:1;
457 u32 rsv1:15;
458 void *next;
459 void *ptr;
460 u32 buflen:16;
461 u32 extlen:8;
462 u32 rsv2:8;
463 u32 arg;
464 u32 blknum;
465 u32 cmd;
466 };
467
468 struct bd {
469 u32 eol:1;
470 u32 rsv0:7;
471 u32 chksum:8;
472 u32 rsv1:1;
473 u32 blkpad:1;
474 u32 dwpad:1;
475 u32 rsv2:13;
476 void *next;
477 void *ptr;
478 u32 buflen:16;
479 u32 rsv3:16;
480 };
481
482 /*--------------------------------------------------------------------------*/
483 /* Register Debugging Structure */
484 /*--------------------------------------------------------------------------*/
485
486 struct msdc_cfg_reg {
487 u32 msdc:1;
488 u32 ckpwn:1;
489 u32 rst:1;
490 u32 pio:1;
491 u32 ckdrven:1;
492 u32 start18v:1;
493 u32 pass18v:1;
494 u32 ckstb:1;
495 u32 ckdiv:8;
496 u32 ckmod:2;
497 u32 pad:14;
498 };
499
500 struct msdc_iocon_reg {
501 u32 sdr104cksel:1;
502 u32 rsmpl:1;
503 u32 dsmpl:1;
504 u32 ddlysel:1;
505 u32 ddr50ckd:1;
506 u32 dsplsel:1;
507 u32 pad1:10;
508 u32 d0spl:1;
509 u32 d1spl:1;
510 u32 d2spl:1;
511 u32 d3spl:1;
512 u32 d4spl:1;
513 u32 d5spl:1;
514 u32 d6spl:1;
515 u32 d7spl:1;
516 u32 riscsz:1;
517 u32 pad2:7;
518 };
519
520 struct msdc_ps_reg {
521 u32 cden:1;
522 u32 cdsts:1;
523 u32 pad1:10;
524 u32 cddebounce:4;
525 u32 dat:8;
526 u32 cmd:1;
527 u32 pad2:6;
528 u32 wp:1;
529 };
530
531 struct msdc_int_reg {
532 u32 mmcirq:1;
533 u32 cdsc:1;
534 u32 pad1:1;
535 u32 atocmdrdy:1;
536 u32 atocmdtmo:1;
537 u32 atocmdcrc:1;
538 u32 dmaqempty:1;
539 u32 sdioirq:1;
540 u32 cmdrdy:1;
541 u32 cmdtmo:1;
542 u32 rspcrc:1;
543 u32 csta:1;
544 u32 xfercomp:1;
545 u32 dxferdone:1;
546 u32 dattmo:1;
547 u32 datcrc:1;
548 u32 atocmd19done:1;
549 u32 pad2:15;
550 };
551
552 struct msdc_inten_reg {
553 u32 mmcirq:1;
554 u32 cdsc:1;
555 u32 pad1:1;
556 u32 atocmdrdy:1;
557 u32 atocmdtmo:1;
558 u32 atocmdcrc:1;
559 u32 dmaqempty:1;
560 u32 sdioirq:1;
561 u32 cmdrdy:1;
562 u32 cmdtmo:1;
563 u32 rspcrc:1;
564 u32 csta:1;
565 u32 xfercomp:1;
566 u32 dxferdone:1;
567 u32 dattmo:1;
568 u32 datcrc:1;
569 u32 atocmd19done:1;
570 u32 pad2:15;
571 };
572
573 struct msdc_fifocs_reg {
574 u32 rxcnt:8;
575 u32 pad1:8;
576 u32 txcnt:8;
577 u32 pad2:7;
578 u32 clr:1;
579 };
580
581 struct msdc_txdat_reg {
582 u32 val;
583 };
584
585 struct msdc_rxdat_reg {
586 u32 val;
587 };
588
589 struct sdc_cfg_reg {
590 u32 sdiowkup:1;
591 u32 inswkup:1;
592 u32 pad1:14;
593 u32 buswidth:2;
594 u32 pad2:1;
595 u32 sdio:1;
596 u32 sdioide:1;
597 u32 intblkgap:1;
598 u32 pad4:2;
599 u32 dtoc:8;
600 };
601
602 struct sdc_cmd_reg {
603 u32 cmd:6;
604 u32 brk:1;
605 u32 rsptyp:3;
606 u32 pad1:1;
607 u32 dtype:2;
608 u32 rw:1;
609 u32 stop:1;
610 u32 goirq:1;
611 u32 blklen:12;
612 u32 atocmd:2;
613 u32 volswth:1;
614 u32 pad2:1;
615 };
616
617 struct sdc_arg_reg {
618 u32 arg;
619 };
620
621 struct sdc_sts_reg {
622 u32 sdcbusy:1;
623 u32 cmdbusy:1;
624 u32 pad:29;
625 u32 swrcmpl:1;
626 };
627
628 struct sdc_resp0_reg {
629 u32 val;
630 };
631
632 struct sdc_resp1_reg {
633 u32 val;
634 };
635
636 struct sdc_resp2_reg {
637 u32 val;
638 };
639
640 struct sdc_resp3_reg {
641 u32 val;
642 };
643
644 struct sdc_blknum_reg {
645 u32 num;
646 };
647
648 struct sdc_csts_reg {
649 u32 sts;
650 };
651
652 struct sdc_cstsen_reg {
653 u32 sts;
654 };
655
656 struct sdc_datcrcsts_reg {
657 u32 datcrcsts:8;
658 u32 ddrcrcsts:4;
659 u32 pad:20;
660 };
661
662 struct emmc_cfg0_reg {
663 u32 bootstart:1;
664 u32 bootstop:1;
665 u32 bootmode:1;
666 u32 pad1:9;
667 u32 bootwaidly:3;
668 u32 bootsupp:1;
669 u32 pad2:16;
670 };
671
672 struct emmc_cfg1_reg {
673 u32 bootcrctmc:16;
674 u32 pad:4;
675 u32 bootacktmc:12;
676 };
677
678 struct emmc_sts_reg {
679 u32 bootcrcerr:1;
680 u32 bootackerr:1;
681 u32 bootdattmo:1;
682 u32 bootacktmo:1;
683 u32 bootupstate:1;
684 u32 bootackrcv:1;
685 u32 bootdatrcv:1;
686 u32 pad:25;
687 };
688
689 struct emmc_iocon_reg {
690 u32 bootrst:1;
691 u32 pad:31;
692 };
693
694 struct msdc_acmd_resp_reg {
695 u32 val;
696 };
697
698 struct msdc_acmd19_trg_reg {
699 u32 tunesel:4;
700 u32 pad:28;
701 };
702
703 struct msdc_acmd19_sts_reg {
704 u32 val;
705 };
706
707 struct msdc_dma_sa_reg {
708 u32 addr;
709 };
710
711 struct msdc_dma_ca_reg {
712 u32 addr;
713 };
714
715 struct msdc_dma_ctrl_reg {
716 u32 start:1;
717 u32 stop:1;
718 u32 resume:1;
719 u32 pad1:5;
720 u32 mode:1;
721 u32 pad2:1;
722 u32 lastbuf:1;
723 u32 pad3:1;
724 u32 brustsz:3;
725 u32 pad4:1;
726 u32 xfersz:16;
727 };
728
729 struct msdc_dma_cfg_reg {
730 u32 status:1;
731 u32 decsen:1;
732 u32 pad1:2;
733 u32 bdcsen:1;
734 u32 gpdcsen:1;
735 u32 pad2:26;
736 };
737
738 struct msdc_dbg_sel_reg {
739 u32 sel:16;
740 u32 pad2:16;
741 };
742
743 struct msdc_dbg_out_reg {
744 u32 val;
745 };
746
747 struct msdc_pad_ctl0_reg {
748 u32 clkdrvn:3;
749 u32 rsv0:1;
750 u32 clkdrvp:3;
751 u32 rsv1:1;
752 u32 clksr:1;
753 u32 rsv2:7;
754 u32 clkpd:1;
755 u32 clkpu:1;
756 u32 clksmt:1;
757 u32 clkies:1;
758 u32 clktdsel:4;
759 u32 clkrdsel:8;
760 };
761
762 struct msdc_pad_ctl1_reg {
763 u32 cmddrvn:3;
764 u32 rsv0:1;
765 u32 cmddrvp:3;
766 u32 rsv1:1;
767 u32 cmdsr:1;
768 u32 rsv2:7;
769 u32 cmdpd:1;
770 u32 cmdpu:1;
771 u32 cmdsmt:1;
772 u32 cmdies:1;
773 u32 cmdtdsel:4;
774 u32 cmdrdsel:8;
775 };
776
777 struct msdc_pad_ctl2_reg {
778 u32 datdrvn:3;
779 u32 rsv0:1;
780 u32 datdrvp:3;
781 u32 rsv1:1;
782 u32 datsr:1;
783 u32 rsv2:7;
784 u32 datpd:1;
785 u32 datpu:1;
786 u32 datsmt:1;
787 u32 daties:1;
788 u32 dattdsel:4;
789 u32 datrdsel:8;
790 };
791
792 struct msdc_pad_tune_reg {
793 u32 wrrxdly:3;
794 u32 pad1:5;
795 u32 rdrxdly:8;
796 u32 pad2:16;
797 };
798
799 struct msdc_dat_rddly0 {
800 u32 dat0:5;
801 u32 rsv0:3;
802 u32 dat1:5;
803 u32 rsv1:3;
804 u32 dat2:5;
805 u32 rsv2:3;
806 u32 dat3:5;
807 u32 rsv3:3;
808 };
809
810 struct msdc_dat_rddly1 {
811 u32 dat4:5;
812 u32 rsv4:3;
813 u32 dat5:5;
814 u32 rsv5:3;
815 u32 dat6:5;
816 u32 rsv6:3;
817 u32 dat7:5;
818 u32 rsv7:3;
819 };
820
821 struct msdc_hw_dbg_reg {
822 u32 dbg0sel:8;
823 u32 dbg1sel:6;
824 u32 pad1:2;
825 u32 dbg2sel:6;
826 u32 pad2:2;
827 u32 dbg3sel:6;
828 u32 pad3:2;
829 };
830
831 struct msdc_version_reg {
832 u32 val;
833 };
834
835 struct msdc_eco_ver_reg {
836 u32 val;
837 };
838
839 struct msdc_regs {
840 struct msdc_cfg_reg msdc_cfg; /* base+0x00h */
841 struct msdc_iocon_reg msdc_iocon; /* base+0x04h */
842 struct msdc_ps_reg msdc_ps; /* base+0x08h */
843 struct msdc_int_reg msdc_int; /* base+0x0ch */
844 struct msdc_inten_reg msdc_inten; /* base+0x10h */
845 struct msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
846 struct msdc_txdat_reg msdc_txdat; /* base+0x18h */
847 struct msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
848 u32 rsv1[4];
849 struct sdc_cfg_reg sdc_cfg; /* base+0x30h */
850 struct sdc_cmd_reg sdc_cmd; /* base+0x34h */
851 struct sdc_arg_reg sdc_arg; /* base+0x38h */
852 struct sdc_sts_reg sdc_sts; /* base+0x3ch */
853 struct sdc_resp0_reg sdc_resp0; /* base+0x40h */
854 struct sdc_resp1_reg sdc_resp1; /* base+0x44h */
855 struct sdc_resp2_reg sdc_resp2; /* base+0x48h */
856 struct sdc_resp3_reg sdc_resp3; /* base+0x4ch */
857 struct sdc_blknum_reg sdc_blknum; /* base+0x50h */
858 u32 rsv2[1];
859 struct sdc_csts_reg sdc_csts; /* base+0x58h */
860 struct sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
861 struct sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
862 u32 rsv3[3];
863 struct emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
864 struct emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
865 struct emmc_sts_reg emmc_sts; /* base+0x78h */
866 struct emmc_iocon_reg emmc_iocon; /* base+0x7ch */
867 struct msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
868 struct msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
869 struct msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
870 u32 rsv4[1];
871 struct msdc_dma_sa_reg dma_sa; /* base+0x90h */
872 struct msdc_dma_ca_reg dma_ca; /* base+0x94h */
873 struct msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
874 struct msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
875 struct msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
876 struct msdc_dbg_out_reg dbg_out; /* base+0xa4h */
877 u32 rsv5[2];
878 u32 patch0; /* base+0xb0h */
879 u32 patch1; /* base+0xb4h */
880 u32 rsv6[10];
881 struct msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
882 struct msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
883 struct msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
884 struct msdc_pad_tune_reg pad_tune; /* base+0xech */
885 struct msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
886 struct msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
887 struct msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
888 u32 rsv7[1];
889 struct msdc_version_reg version; /* base+0x100h */
890 struct msdc_eco_ver_reg eco_ver; /* base+0x104h */
891 };
892
893 struct msdc_dma {
894 u32 sglen; /* size of scatter list */
895 struct scatterlist *sg; /* I/O scatter list */
896 u8 mode; /* dma mode */
897
898 struct gpd *gpd; /* pointer to gpd array */
899 struct bd *bd; /* pointer to bd array */
900 dma_addr_t gpd_addr; /* the physical address of gpd array */
901 dma_addr_t bd_addr; /* the physical address of bd array */
902 };
903
904 struct msdc_host {
905 struct msdc_hw *hw;
906
907 struct mmc_host *mmc; /* mmc structure */
908 struct mmc_command *cmd;
909 struct mmc_data *data;
910 struct mmc_request *mrq;
911 int cmd_rsp;
912
913 int error;
914 spinlock_t lock; /* mutex */
915 struct semaphore sem;
916
917 u32 blksz; /* host block size */
918 void __iomem *base; /* host base address */
919 int id; /* host id */
920 int pwr_ref; /* core power reference count */
921
922 u32 xfer_size; /* total transferred size */
923
924 struct msdc_dma dma; /* dma channel */
925 u32 dma_xfer_size; /* dma transfer size in bytes */
926
927 u32 timeout_ns; /* data timeout ns */
928 u32 timeout_clks; /* data timeout clks */
929
930 int irq; /* host interrupt */
931
932 struct delayed_work card_delaywork;
933
934 struct completion cmd_done;
935 struct completion xfer_done;
936 struct pm_message pm_state;
937
938 u32 mclk; /* mmc subsystem clock */
939 u32 hclk; /* host clock speed */
940 u32 sclk; /* SD/MS clock speed */
941 u8 core_clkon; /* Host core clock on ? */
942 u8 card_clkon; /* Card clock on ? */
943 u8 core_power; /* core power */
944 u8 power_mode; /* host power mode */
945 u8 card_inserted; /* card inserted ? */
946 u8 suspend; /* host suspended ? */
947 u8 app_cmd; /* for app command */
948 u32 app_cmd_arg;
949 };
950
951 #define sdr_read8(reg) readb(reg)
952 #define sdr_read32(reg) readl(reg)
953 #define sdr_write8(reg, val) writeb(val, reg)
954 #define sdr_write32(reg, val) writel(val, reg)
955
956 static inline void sdr_set_bits(void __iomem *reg, u32 bs)
957 {
958 u32 val = readl(reg);
959
960 val |= bs;
961 writel(val, reg);
962 }
963
964 static inline void sdr_clr_bits(void __iomem *reg, u32 bs)
965 {
966 u32 val = readl(reg);
967
968 val &= ~bs;
969 writel(val, reg);
970 }
971
972 static inline void sdr_set_field(void __iomem *reg, u32 field, u32 val)
973 {
974 unsigned int tv = readl(reg);
975
976 tv &= ~field;
977 tv |= ((val) << (ffs((unsigned int)field) - 1));
978 writel(tv, reg);
979 }
980
981 static inline void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
982 {
983 unsigned int tv = readl(reg);
984 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
985 }
986
987 #endif