8bf17f629c2fa5f29f37eed0315a59c62f6046cf
[openwrt/openwrt.git] / target / linux / ramips / files-4.14 / drivers / net / ethernet / mediatek / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
31 #include <linux/io.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "mtk_eth_soc.h"
39 #include "mdio.h"
40 #include "ethtool.h"
41
42 #define MAX_RX_LENGTH 1536
43 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
44 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
45 #define DMA_DUMMY_DESC 0xffffffff
46 #define FE_DEFAULT_MSG_ENABLE \
47 (NETIF_MSG_DRV | \
48 NETIF_MSG_PROBE | \
49 NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_IFDOWN | \
52 NETIF_MSG_IFUP | \
53 NETIF_MSG_RX_ERR | \
54 NETIF_MSG_TX_ERR)
55
56 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
57 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
58 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
59 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
60
61 #define SYSC_REG_RSTCTRL 0x34
62
63 static int fe_msg_level = -1;
64 module_param_named(msg_level, fe_msg_level, int, 0);
65 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
66
67 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
68 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
69 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
70 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
71 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
72 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
73 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
74 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
79 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
80 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
81 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
82 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
83 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
84 };
85
86 static const u16 *fe_reg_table = fe_reg_table_default;
87
88 struct fe_work_t {
89 int bitnr;
90 void (*action)(struct fe_priv *);
91 };
92
93 static void __iomem *fe_base;
94
95 void fe_w32(u32 val, unsigned reg)
96 {
97 __raw_writel(val, fe_base + reg);
98 }
99
100 u32 fe_r32(unsigned reg)
101 {
102 return __raw_readl(fe_base + reg);
103 }
104
105 void fe_reg_w32(u32 val, enum fe_reg reg)
106 {
107 fe_w32(val, fe_reg_table[reg]);
108 }
109
110 u32 fe_reg_r32(enum fe_reg reg)
111 {
112 return fe_r32(fe_reg_table[reg]);
113 }
114
115 void fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg)
116 {
117 u32 val;
118
119 spin_lock(&eth->page_lock);
120 val = __raw_readl(fe_base + reg);
121 val &= ~clear;
122 val |= set;
123 __raw_writel(val, fe_base + reg);
124 spin_unlock(&eth->page_lock);
125 }
126
127 void fe_reset(u32 reset_bits)
128 {
129 u32 t;
130
131 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
132 t |= reset_bits;
133 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
134 usleep_range(10, 20);
135
136 t &= ~reset_bits;
137 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
138 usleep_range(10, 20);
139 }
140
141 static inline void fe_int_disable(u32 mask)
142 {
143 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
144 FE_REG_FE_INT_ENABLE);
145 /* flush write */
146 fe_reg_r32(FE_REG_FE_INT_ENABLE);
147 }
148
149 static inline void fe_int_enable(u32 mask)
150 {
151 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
152 FE_REG_FE_INT_ENABLE);
153 /* flush write */
154 fe_reg_r32(FE_REG_FE_INT_ENABLE);
155 }
156
157 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
158 {
159 unsigned long flags;
160
161 spin_lock_irqsave(&priv->page_lock, flags);
162 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
163 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
164 FE_GDMA1_MAC_ADRL);
165 spin_unlock_irqrestore(&priv->page_lock, flags);
166 }
167
168 static int fe_set_mac_address(struct net_device *dev, void *p)
169 {
170 int ret = eth_mac_addr(dev, p);
171
172 if (!ret) {
173 struct fe_priv *priv = netdev_priv(dev);
174
175 if (priv->soc->set_mac)
176 priv->soc->set_mac(priv, dev->dev_addr);
177 else
178 fe_hw_set_macaddr(priv, p);
179 }
180
181 return ret;
182 }
183
184 static inline int fe_max_frag_size(int mtu)
185 {
186 /* make sure buf_size will be at least MAX_RX_LENGTH */
187 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
188 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
189
190 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
191 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
192 }
193
194 static inline int fe_max_buf_size(int frag_size)
195 {
196 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
197 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
198
199 BUG_ON(buf_size < MAX_RX_LENGTH);
200 return buf_size;
201 }
202
203 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
204 {
205 rxd->rxd1 = dma_rxd->rxd1;
206 rxd->rxd2 = dma_rxd->rxd2;
207 rxd->rxd3 = dma_rxd->rxd3;
208 rxd->rxd4 = dma_rxd->rxd4;
209 }
210
211 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
212 {
213 dma_txd->txd1 = txd->txd1;
214 dma_txd->txd3 = txd->txd3;
215 dma_txd->txd4 = txd->txd4;
216 /* clean dma done flag last */
217 dma_txd->txd2 = txd->txd2;
218 }
219
220 static void fe_clean_rx(struct fe_priv *priv)
221 {
222 struct fe_rx_ring *ring = &priv->rx_ring;
223 struct page *page;
224 int i;
225
226 if (ring->rx_data) {
227 for (i = 0; i < ring->rx_ring_size; i++)
228 if (ring->rx_data[i]) {
229 if (ring->rx_dma && ring->rx_dma[i].rxd1)
230 dma_unmap_single(&priv->netdev->dev,
231 ring->rx_dma[i].rxd1,
232 ring->rx_buf_size,
233 DMA_FROM_DEVICE);
234 skb_free_frag(ring->rx_data[i]);
235 }
236
237 kfree(ring->rx_data);
238 ring->rx_data = NULL;
239 }
240
241 if (ring->rx_dma) {
242 dma_free_coherent(&priv->netdev->dev,
243 ring->rx_ring_size * sizeof(*ring->rx_dma),
244 ring->rx_dma,
245 ring->rx_phys);
246 ring->rx_dma = NULL;
247 }
248
249 if (!ring->frag_cache.va)
250 return;
251
252 page = virt_to_page(ring->frag_cache.va);
253 __page_frag_cache_drain(page, ring->frag_cache.pagecnt_bias);
254 memset(&ring->frag_cache, 0, sizeof(ring->frag_cache));
255 }
256
257 static int fe_alloc_rx(struct fe_priv *priv)
258 {
259 struct net_device *netdev = priv->netdev;
260 struct fe_rx_ring *ring = &priv->rx_ring;
261 int i, pad;
262
263 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
264 GFP_KERNEL);
265 if (!ring->rx_data)
266 goto no_rx_mem;
267
268 for (i = 0; i < ring->rx_ring_size; i++) {
269 ring->rx_data[i] = page_frag_alloc(&ring->frag_cache,
270 ring->frag_size,
271 GFP_KERNEL);
272 if (!ring->rx_data[i])
273 goto no_rx_mem;
274 }
275
276 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
277 ring->rx_ring_size * sizeof(*ring->rx_dma),
278 &ring->rx_phys,
279 GFP_ATOMIC | __GFP_ZERO);
280 if (!ring->rx_dma)
281 goto no_rx_mem;
282
283 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
284 pad = 0;
285 else
286 pad = NET_IP_ALIGN;
287 for (i = 0; i < ring->rx_ring_size; i++) {
288 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
289 ring->rx_data[i] + NET_SKB_PAD + pad,
290 ring->rx_buf_size,
291 DMA_FROM_DEVICE);
292 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
293 goto no_rx_mem;
294 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
295
296 if (priv->flags & FE_FLAG_RX_SG_DMA)
297 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
298 else
299 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
300 }
301 ring->rx_calc_idx = ring->rx_ring_size - 1;
302 /* make sure that all changes to the dma ring are flushed before we
303 * continue
304 */
305 wmb();
306
307 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
308 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
309 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
310 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
311
312 return 0;
313
314 no_rx_mem:
315 return -ENOMEM;
316 }
317
318 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
319 {
320 if (dma_unmap_len(tx_buf, dma_len0))
321 dma_unmap_page(dev,
322 dma_unmap_addr(tx_buf, dma_addr0),
323 dma_unmap_len(tx_buf, dma_len0),
324 DMA_TO_DEVICE);
325
326 if (dma_unmap_len(tx_buf, dma_len1))
327 dma_unmap_page(dev,
328 dma_unmap_addr(tx_buf, dma_addr1),
329 dma_unmap_len(tx_buf, dma_len1),
330 DMA_TO_DEVICE);
331
332 dma_unmap_len_set(tx_buf, dma_addr0, 0);
333 dma_unmap_len_set(tx_buf, dma_addr1, 0);
334 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
335 dev_kfree_skb_any(tx_buf->skb);
336 tx_buf->skb = NULL;
337 }
338
339 static void fe_clean_tx(struct fe_priv *priv)
340 {
341 int i;
342 struct device *dev = &priv->netdev->dev;
343 struct fe_tx_ring *ring = &priv->tx_ring;
344
345 if (ring->tx_buf) {
346 for (i = 0; i < ring->tx_ring_size; i++)
347 fe_txd_unmap(dev, &ring->tx_buf[i]);
348 kfree(ring->tx_buf);
349 ring->tx_buf = NULL;
350 }
351
352 if (ring->tx_dma) {
353 dma_free_coherent(dev,
354 ring->tx_ring_size * sizeof(*ring->tx_dma),
355 ring->tx_dma,
356 ring->tx_phys);
357 ring->tx_dma = NULL;
358 }
359
360 netdev_reset_queue(priv->netdev);
361 }
362
363 static int fe_alloc_tx(struct fe_priv *priv)
364 {
365 int i;
366 struct fe_tx_ring *ring = &priv->tx_ring;
367
368 ring->tx_free_idx = 0;
369 ring->tx_next_idx = 0;
370 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
371 MAX_SKB_FRAGS);
372
373 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
374 GFP_KERNEL);
375 if (!ring->tx_buf)
376 goto no_tx_mem;
377
378 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
379 ring->tx_ring_size * sizeof(*ring->tx_dma),
380 &ring->tx_phys,
381 GFP_ATOMIC | __GFP_ZERO);
382 if (!ring->tx_dma)
383 goto no_tx_mem;
384
385 for (i = 0; i < ring->tx_ring_size; i++) {
386 if (priv->soc->tx_dma)
387 priv->soc->tx_dma(&ring->tx_dma[i]);
388 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
389 }
390 /* make sure that all changes to the dma ring are flushed before we
391 * continue
392 */
393 wmb();
394
395 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
396 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
397 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
398 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
399
400 return 0;
401
402 no_tx_mem:
403 return -ENOMEM;
404 }
405
406 static int fe_init_dma(struct fe_priv *priv)
407 {
408 int err;
409
410 err = fe_alloc_tx(priv);
411 if (err)
412 return err;
413
414 err = fe_alloc_rx(priv);
415 if (err)
416 return err;
417
418 return 0;
419 }
420
421 static void fe_free_dma(struct fe_priv *priv)
422 {
423 fe_clean_tx(priv);
424 fe_clean_rx(priv);
425 }
426
427 void fe_stats_update(struct fe_priv *priv)
428 {
429 struct fe_hw_stats *hwstats = priv->hw_stats;
430 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
431 u64 stats;
432
433 u64_stats_update_begin(&hwstats->syncp);
434
435 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
436 hwstats->rx_bytes += fe_r32(base);
437 stats = fe_r32(base + 0x04);
438 if (stats)
439 hwstats->rx_bytes += (stats << 32);
440 hwstats->rx_packets += fe_r32(base + 0x08);
441 hwstats->rx_overflow += fe_r32(base + 0x10);
442 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
443 hwstats->rx_short_errors += fe_r32(base + 0x18);
444 hwstats->rx_long_errors += fe_r32(base + 0x1c);
445 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
446 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
447 hwstats->tx_skip += fe_r32(base + 0x28);
448 hwstats->tx_collisions += fe_r32(base + 0x2c);
449 hwstats->tx_bytes += fe_r32(base + 0x30);
450 stats = fe_r32(base + 0x34);
451 if (stats)
452 hwstats->tx_bytes += (stats << 32);
453 hwstats->tx_packets += fe_r32(base + 0x38);
454 } else {
455 hwstats->tx_bytes += fe_r32(base);
456 hwstats->tx_packets += fe_r32(base + 0x04);
457 hwstats->tx_skip += fe_r32(base + 0x08);
458 hwstats->tx_collisions += fe_r32(base + 0x0c);
459 hwstats->rx_bytes += fe_r32(base + 0x20);
460 hwstats->rx_packets += fe_r32(base + 0x24);
461 hwstats->rx_overflow += fe_r32(base + 0x28);
462 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
463 hwstats->rx_short_errors += fe_r32(base + 0x30);
464 hwstats->rx_long_errors += fe_r32(base + 0x34);
465 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
466 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
467 }
468
469 u64_stats_update_end(&hwstats->syncp);
470 }
471
472 static void fe_get_stats64(struct net_device *dev,
473 struct rtnl_link_stats64 *storage)
474 {
475 struct fe_priv *priv = netdev_priv(dev);
476 struct fe_hw_stats *hwstats = priv->hw_stats;
477 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
478 unsigned int start;
479
480 if (!base) {
481 netdev_stats_to_stats64(storage, &dev->stats);
482 return;
483 }
484
485 if (netif_running(dev) && netif_device_present(dev)) {
486 if (spin_trylock_bh(&hwstats->stats_lock)) {
487 fe_stats_update(priv);
488 spin_unlock_bh(&hwstats->stats_lock);
489 }
490 }
491
492 do {
493 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
494 storage->rx_packets = hwstats->rx_packets;
495 storage->tx_packets = hwstats->tx_packets;
496 storage->rx_bytes = hwstats->rx_bytes;
497 storage->tx_bytes = hwstats->tx_bytes;
498 storage->collisions = hwstats->tx_collisions;
499 storage->rx_length_errors = hwstats->rx_short_errors +
500 hwstats->rx_long_errors;
501 storage->rx_over_errors = hwstats->rx_overflow;
502 storage->rx_crc_errors = hwstats->rx_fcs_errors;
503 storage->rx_errors = hwstats->rx_checksum_errors;
504 storage->tx_aborted_errors = hwstats->tx_skip;
505 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
506
507 storage->tx_errors = priv->netdev->stats.tx_errors;
508 storage->rx_dropped = priv->netdev->stats.rx_dropped;
509 storage->tx_dropped = priv->netdev->stats.tx_dropped;
510 }
511
512 static int fe_vlan_rx_add_vid(struct net_device *dev,
513 __be16 proto, u16 vid)
514 {
515 struct fe_priv *priv = netdev_priv(dev);
516 u32 idx = (vid & 0xf);
517 u32 vlan_cfg;
518
519 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
520 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
521 return 0;
522
523 if (test_bit(idx, &priv->vlan_map)) {
524 netdev_warn(dev, "disable tx vlan offload\n");
525 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
526 netdev_update_features(dev);
527 } else {
528 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
529 ((idx >> 1) << 2));
530 if (idx & 0x1) {
531 vlan_cfg &= 0xffff;
532 vlan_cfg |= (vid << 16);
533 } else {
534 vlan_cfg &= 0xffff0000;
535 vlan_cfg |= vid;
536 }
537 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
538 ((idx >> 1) << 2));
539 set_bit(idx, &priv->vlan_map);
540 }
541
542 return 0;
543 }
544
545 static int fe_vlan_rx_kill_vid(struct net_device *dev,
546 __be16 proto, u16 vid)
547 {
548 struct fe_priv *priv = netdev_priv(dev);
549 u32 idx = (vid & 0xf);
550
551 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
552 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
553 return 0;
554
555 clear_bit(idx, &priv->vlan_map);
556
557 return 0;
558 }
559
560 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
561 {
562 barrier();
563 return (u32)(ring->tx_ring_size -
564 ((ring->tx_next_idx - ring->tx_free_idx) &
565 (ring->tx_ring_size - 1)));
566 }
567
568 static int fe_tx_dma_map_page(struct device *dev, struct fe_tx_buf *tx_buf,
569 struct fe_tx_dma *txd, int idx,
570 struct page *page, size_t offset, size_t size)
571 {
572 dma_addr_t mapped_addr;
573
574 mapped_addr = dma_map_page(dev, page, offset, size, DMA_TO_DEVICE);
575 if (unlikely(dma_mapping_error(dev, mapped_addr)))
576 return -EIO;
577
578 if (idx & 1) {
579 txd->txd3 = mapped_addr;
580 txd->txd2 |= TX_DMA_PLEN1(size);
581 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
582 dma_unmap_len_set(tx_buf, dma_len1, size);
583 } else {
584 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
585 txd->txd1 = mapped_addr;
586 txd->txd2 = TX_DMA_PLEN0(size);
587 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
588 dma_unmap_len_set(tx_buf, dma_len0, size);
589 }
590 return 0;
591 }
592
593 static int fe_tx_dma_map_skb(struct device *dev, struct fe_tx_buf *tx_buf,
594 struct fe_tx_dma *txd, int idx,
595 struct sk_buff *skb)
596 {
597 struct page *page = virt_to_page(skb->data);
598 size_t offset = offset_in_page(skb->data);
599 size_t size = skb_headlen(skb);
600
601 return fe_tx_dma_map_page(dev, tx_buf, txd, idx, page, offset, size);
602 }
603
604 static inline struct sk_buff *
605 fe_next_frag(struct sk_buff *head, struct sk_buff *skb)
606 {
607 if (skb != head)
608 return skb->next;
609
610 if (skb_has_frag_list(skb))
611 return skb_shinfo(skb)->frag_list;
612
613 return NULL;
614 }
615
616 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
617 int tx_num, struct fe_tx_ring *ring)
618 {
619 struct fe_priv *priv = netdev_priv(dev);
620 struct skb_frag_struct *frag;
621 struct fe_tx_dma txd, *ptxd;
622 struct fe_tx_buf *tx_buf;
623 struct sk_buff *head = skb;
624 unsigned int nr_frags;
625 u32 def_txd4;
626 int i, j, k, frag_size, frag_map_size, offset;
627
628 tx_buf = &ring->tx_buf[ring->tx_next_idx];
629 memset(tx_buf, 0, sizeof(*tx_buf));
630 memset(&txd, 0, sizeof(txd));
631
632 /* init tx descriptor */
633 if (priv->soc->tx_dma)
634 priv->soc->tx_dma(&txd);
635 else
636 txd.txd4 = TX_DMA_DESP4_DEF;
637 def_txd4 = txd.txd4;
638
639 /* TX Checksum offload */
640 if (skb->ip_summed == CHECKSUM_PARTIAL)
641 txd.txd4 |= TX_DMA_CHKSUM;
642
643 /* VLAN header offload */
644 if (skb_vlan_tag_present(skb)) {
645 u16 tag = skb_vlan_tag_get(skb);
646
647 if (IS_ENABLED(CONFIG_SOC_MT7621))
648 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
649 else
650 txd.txd4 |= TX_DMA_INS_VLAN |
651 ((tag >> VLAN_PRIO_SHIFT) << 4) |
652 (tag & 0xF);
653 }
654
655 /* TSO: fill MSS info in tcp checksum field */
656 if (skb_is_gso(skb)) {
657 if (skb_cow_head(skb, 0)) {
658 netif_warn(priv, tx_err, dev,
659 "GSO expand head fail.\n");
660 goto err_out;
661 }
662 if (skb_shinfo(skb)->gso_type &
663 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
664 txd.txd4 |= TX_DMA_TSO;
665 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
666 }
667 }
668
669 k = 0;
670 j = ring->tx_next_idx;
671
672 next_frag:
673 if (skb_headlen(skb)) {
674 if (fe_tx_dma_map_skb(&dev->dev, tx_buf, &txd, k++, skb))
675 goto err_dma;
676 }
677
678 /* TX SG offload */
679 nr_frags = skb_shinfo(skb)->nr_frags;
680 for (i = 0; i < nr_frags; i++) {
681 struct page *page;
682
683 frag = &skb_shinfo(skb)->frags[i];
684 frag_size = skb_frag_size(frag);
685 offset = frag->page_offset;
686 page = skb_frag_page(frag);
687
688 while (frag_size > 0) {
689 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
690 if (!(k & 0x1)) {
691 fe_set_txd(&txd, &ring->tx_dma[j]);
692 memset(&txd, 0, sizeof(txd));
693 txd.txd4 = def_txd4;
694 j = NEXT_TX_DESP_IDX(j);
695 tx_buf = &ring->tx_buf[j];
696 }
697
698 if (fe_tx_dma_map_page(&dev->dev, tx_buf, &txd, k++,
699 page, offset, frag_map_size))
700 goto err_dma;
701
702 frag_size -= frag_map_size;
703 offset += frag_map_size;
704 }
705 }
706
707 skb = fe_next_frag(head, skb);
708 if (skb) {
709 if (!(k & 0x1)) {
710 fe_set_txd(&txd, &ring->tx_dma[j]);
711 memset(&txd, 0, sizeof(txd));
712 txd.txd4 = def_txd4;
713 j = NEXT_TX_DESP_IDX(j);
714 tx_buf = &ring->tx_buf[j];
715 }
716 goto next_frag;
717 }
718
719 /* set last segment */
720 if (k & 0x1)
721 txd.txd2 |= TX_DMA_LS0;
722 else
723 txd.txd2 |= TX_DMA_LS1;
724 fe_set_txd(&txd, &ring->tx_dma[j]);
725
726 /* store skb to cleanup */
727 tx_buf->skb = head;
728
729 netdev_sent_queue(dev, head->len);
730 skb_tx_timestamp(head);
731
732 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
733 /* make sure that all changes to the dma ring are flushed before we
734 * continue
735 */
736 wmb();
737 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
738 netif_stop_queue(dev);
739 smp_mb();
740 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
741 netif_wake_queue(dev);
742 }
743
744 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !head->xmit_more)
745 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
746
747 return 0;
748
749 err_dma:
750 j = ring->tx_next_idx;
751 for (i = 0; i < tx_num; i++) {
752 ptxd = &ring->tx_dma[j];
753 tx_buf = &ring->tx_buf[j];
754
755 /* unmap dma */
756 fe_txd_unmap(&dev->dev, tx_buf);
757
758 ptxd->txd2 = TX_DMA_DESP2_DEF;
759 j = NEXT_TX_DESP_IDX(j);
760 }
761 /* make sure that all changes to the dma ring are flushed before we
762 * continue
763 */
764 wmb();
765
766 err_out:
767 return -1;
768 }
769
770 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
771 {
772 unsigned int len;
773 int ret;
774
775 ret = 0;
776 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
777 if ((priv->flags & FE_FLAG_PADDING_64B) &&
778 !(priv->flags & FE_FLAG_PADDING_BUG))
779 return ret;
780
781 if (skb_vlan_tag_present(skb))
782 len = ETH_ZLEN;
783 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
784 len = VLAN_ETH_ZLEN;
785 else if (!(priv->flags & FE_FLAG_PADDING_64B))
786 len = ETH_ZLEN;
787 else
788 return ret;
789
790 if (skb->len < len) {
791 ret = skb_pad(skb, len - skb->len);
792 if (ret < 0)
793 return ret;
794 skb->len = len;
795 skb_set_tail_pointer(skb, len);
796 }
797 }
798
799 return ret;
800 }
801
802 static inline int fe_cal_txd_req(struct sk_buff *skb)
803 {
804 struct sk_buff *head = skb;
805 int i, nfrags = 0;
806 struct skb_frag_struct *frag;
807
808 next_frag:
809 nfrags++;
810 if (skb_is_gso(skb)) {
811 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
812 frag = &skb_shinfo(skb)->frags[i];
813 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
814 }
815 } else {
816 nfrags += skb_shinfo(skb)->nr_frags;
817 }
818
819 skb = fe_next_frag(head, skb);
820 if (skb)
821 goto next_frag;
822
823 return DIV_ROUND_UP(nfrags, 2);
824 }
825
826 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
827 {
828 struct fe_priv *priv = netdev_priv(dev);
829 struct fe_tx_ring *ring = &priv->tx_ring;
830 struct net_device_stats *stats = &dev->stats;
831 int tx_num;
832 int len = skb->len;
833
834 if (fe_skb_padto(skb, priv)) {
835 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
836 return NETDEV_TX_OK;
837 }
838
839 tx_num = fe_cal_txd_req(skb);
840 if (unlikely(fe_empty_txd(ring) <= tx_num)) {
841 netif_stop_queue(dev);
842 netif_err(priv, tx_queued, dev,
843 "Tx Ring full when queue awake!\n");
844 return NETDEV_TX_BUSY;
845 }
846
847 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
848 stats->tx_dropped++;
849 } else {
850 stats->tx_packets++;
851 stats->tx_bytes += len;
852 }
853
854 return NETDEV_TX_OK;
855 }
856
857 static int fe_poll_rx(struct napi_struct *napi, int budget,
858 struct fe_priv *priv, u32 rx_intr)
859 {
860 struct net_device *netdev = priv->netdev;
861 struct net_device_stats *stats = &netdev->stats;
862 struct fe_soc_data *soc = priv->soc;
863 struct fe_rx_ring *ring = &priv->rx_ring;
864 int idx = ring->rx_calc_idx;
865 u32 checksum_bit;
866 struct sk_buff *skb;
867 u8 *data, *new_data;
868 struct fe_rx_dma *rxd, trxd;
869 int done = 0, pad;
870
871 if (netdev->features & NETIF_F_RXCSUM)
872 checksum_bit = soc->checksum_bit;
873 else
874 checksum_bit = 0;
875
876 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
877 pad = 0;
878 else
879 pad = NET_IP_ALIGN;
880
881 while (done < budget) {
882 unsigned int pktlen;
883 dma_addr_t dma_addr;
884
885 idx = NEXT_RX_DESP_IDX(idx);
886 rxd = &ring->rx_dma[idx];
887 data = ring->rx_data[idx];
888
889 fe_get_rxd(&trxd, rxd);
890 if (!(trxd.rxd2 & RX_DMA_DONE))
891 break;
892
893 /* alloc new buffer */
894 new_data = page_frag_alloc(&ring->frag_cache, ring->frag_size,
895 GFP_ATOMIC);
896 if (unlikely(!new_data)) {
897 stats->rx_dropped++;
898 goto release_desc;
899 }
900 dma_addr = dma_map_single(&netdev->dev,
901 new_data + NET_SKB_PAD + pad,
902 ring->rx_buf_size,
903 DMA_FROM_DEVICE);
904 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
905 skb_free_frag(new_data);
906 goto release_desc;
907 }
908
909 /* receive data */
910 skb = build_skb(data, ring->frag_size);
911 if (unlikely(!skb)) {
912 skb_free_frag(new_data);
913 goto release_desc;
914 }
915 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
916
917 dma_unmap_single(&netdev->dev, trxd.rxd1,
918 ring->rx_buf_size, DMA_FROM_DEVICE);
919 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
920 skb->dev = netdev;
921 skb_put(skb, pktlen);
922 if (trxd.rxd4 & checksum_bit)
923 skb->ip_summed = CHECKSUM_UNNECESSARY;
924 else
925 skb_checksum_none_assert(skb);
926 skb->protocol = eth_type_trans(skb, netdev);
927
928 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
929 if (mtk_offload_check_rx(priv, skb, trxd.rxd4) == 0) {
930 #endif
931 stats->rx_packets++;
932 stats->rx_bytes += pktlen;
933
934 napi_gro_receive(napi, skb);
935 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
936 } else {
937 dev_kfree_skb(skb);
938 }
939 #endif
940 ring->rx_data[idx] = new_data;
941 rxd->rxd1 = (unsigned int)dma_addr;
942
943 release_desc:
944 if (priv->flags & FE_FLAG_RX_SG_DMA)
945 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
946 else
947 rxd->rxd2 = RX_DMA_LSO;
948
949 ring->rx_calc_idx = idx;
950 /* make sure that all changes to the dma ring are flushed before
951 * we continue
952 */
953 wmb();
954 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
955 done++;
956 }
957
958 if (done < budget)
959 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
960
961 return done;
962 }
963
964 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
965 int *tx_again)
966 {
967 struct net_device *netdev = priv->netdev;
968 struct device *dev = &netdev->dev;
969 unsigned int bytes_compl = 0;
970 struct sk_buff *skb;
971 struct fe_tx_buf *tx_buf;
972 int done = 0;
973 u32 idx, hwidx;
974 struct fe_tx_ring *ring = &priv->tx_ring;
975
976 idx = ring->tx_free_idx;
977 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
978
979 while ((idx != hwidx) && budget) {
980 tx_buf = &ring->tx_buf[idx];
981 skb = tx_buf->skb;
982
983 if (!skb)
984 break;
985
986 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
987 bytes_compl += skb->len;
988 done++;
989 budget--;
990 }
991 fe_txd_unmap(dev, tx_buf);
992 idx = NEXT_TX_DESP_IDX(idx);
993 }
994 ring->tx_free_idx = idx;
995
996 if (idx == hwidx) {
997 /* read hw index again make sure no new tx packet */
998 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
999 if (idx == hwidx)
1000 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
1001 else
1002 *tx_again = 1;
1003 } else {
1004 *tx_again = 1;
1005 }
1006
1007 if (done) {
1008 netdev_completed_queue(netdev, done, bytes_compl);
1009 smp_mb();
1010 if (unlikely(netif_queue_stopped(netdev) &&
1011 (fe_empty_txd(ring) > ring->tx_thresh)))
1012 netif_wake_queue(netdev);
1013 }
1014
1015 return done;
1016 }
1017
1018 static int fe_poll(struct napi_struct *napi, int budget)
1019 {
1020 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
1021 struct fe_hw_stats *hwstat = priv->hw_stats;
1022 int tx_done, rx_done, tx_again;
1023 u32 status, fe_status, status_reg, mask;
1024 u32 tx_intr, rx_intr, status_intr;
1025
1026 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1027 fe_status = status;
1028 tx_intr = priv->soc->tx_int;
1029 rx_intr = priv->soc->rx_int;
1030 status_intr = priv->soc->status_int;
1031 tx_done = 0;
1032 rx_done = 0;
1033 tx_again = 0;
1034
1035 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
1036 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
1037 status_reg = FE_REG_FE_INT_STATUS2;
1038 } else {
1039 status_reg = FE_REG_FE_INT_STATUS;
1040 }
1041
1042 if (status & tx_intr)
1043 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
1044
1045 if (status & rx_intr)
1046 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
1047
1048 if (unlikely(fe_status & status_intr)) {
1049 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
1050 fe_stats_update(priv);
1051 spin_unlock(&hwstat->stats_lock);
1052 }
1053 fe_reg_w32(status_intr, status_reg);
1054 }
1055
1056 if (unlikely(netif_msg_intr(priv))) {
1057 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
1058 netdev_info(priv->netdev,
1059 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1060 tx_done, rx_done, status, mask);
1061 }
1062
1063 if (!tx_again && (rx_done < budget)) {
1064 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1065 if (status & (tx_intr | rx_intr)) {
1066 /* let napi poll again */
1067 rx_done = budget;
1068 goto poll_again;
1069 }
1070
1071 napi_complete_done(napi, rx_done);
1072 fe_int_enable(tx_intr | rx_intr);
1073 } else {
1074 rx_done = budget;
1075 }
1076
1077 poll_again:
1078 return rx_done;
1079 }
1080
1081 static void fe_tx_timeout(struct net_device *dev)
1082 {
1083 struct fe_priv *priv = netdev_priv(dev);
1084 struct fe_tx_ring *ring = &priv->tx_ring;
1085
1086 priv->netdev->stats.tx_errors++;
1087 netif_err(priv, tx_err, dev,
1088 "transmit timed out\n");
1089 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1090 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1091 netif_info(priv, drv, dev, "tx_ring=%d, "
1092 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1093 0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1094 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1095 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1096 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1097 ring->tx_free_idx,
1098 ring->tx_next_idx);
1099 netif_info(priv, drv, dev,
1100 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1101 0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1102 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1103 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1104 fe_reg_r32(FE_REG_RX_DRX_IDX0));
1105
1106 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1107 schedule_work(&priv->pending_work);
1108 }
1109
1110 static irqreturn_t fe_handle_irq(int irq, void *dev)
1111 {
1112 struct fe_priv *priv = netdev_priv(dev);
1113 u32 status, int_mask;
1114
1115 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1116
1117 if (unlikely(!status))
1118 return IRQ_NONE;
1119
1120 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1121 if (likely(status & int_mask)) {
1122 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1123 fe_int_disable(int_mask);
1124 __napi_schedule(&priv->rx_napi);
1125 }
1126 } else {
1127 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1128 }
1129
1130 return IRQ_HANDLED;
1131 }
1132
1133 #ifdef CONFIG_NET_POLL_CONTROLLER
1134 static void fe_poll_controller(struct net_device *dev)
1135 {
1136 struct fe_priv *priv = netdev_priv(dev);
1137 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1138
1139 fe_int_disable(int_mask);
1140 fe_handle_irq(dev->irq, dev);
1141 fe_int_enable(int_mask);
1142 }
1143 #endif
1144
1145 int fe_set_clock_cycle(struct fe_priv *priv)
1146 {
1147 unsigned long sysclk = priv->sysclk;
1148
1149 sysclk /= FE_US_CYC_CNT_DIVISOR;
1150 sysclk <<= FE_US_CYC_CNT_SHIFT;
1151
1152 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1153 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1154 sysclk,
1155 FE_FE_GLO_CFG);
1156 return 0;
1157 }
1158
1159 void fe_fwd_config(struct fe_priv *priv)
1160 {
1161 u32 fwd_cfg;
1162
1163 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1164
1165 /* disable jumbo frame */
1166 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1167 fwd_cfg &= ~FE_GDM1_JMB_EN;
1168
1169 /* set unicast/multicast/broadcast frame to cpu */
1170 fwd_cfg &= ~0xffff;
1171
1172 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1173 }
1174
1175 static void fe_rxcsum_config(bool enable)
1176 {
1177 if (enable)
1178 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1179 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1180 FE_GDMA1_FWD_CFG);
1181 else
1182 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1183 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1184 FE_GDMA1_FWD_CFG);
1185 }
1186
1187 static void fe_txcsum_config(bool enable)
1188 {
1189 if (enable)
1190 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1191 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1192 FE_CDMA_CSG_CFG);
1193 else
1194 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1195 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1196 FE_CDMA_CSG_CFG);
1197 }
1198
1199 void fe_csum_config(struct fe_priv *priv)
1200 {
1201 struct net_device *dev = priv_netdev(priv);
1202
1203 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1204 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1205 }
1206
1207 static int fe_hw_init(struct net_device *dev)
1208 {
1209 struct fe_priv *priv = netdev_priv(dev);
1210 int i, err;
1211
1212 err = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0,
1213 dev_name(priv->dev), dev);
1214 if (err)
1215 return err;
1216
1217 if (priv->soc->set_mac)
1218 priv->soc->set_mac(priv, dev->dev_addr);
1219 else
1220 fe_hw_set_macaddr(priv, dev->dev_addr);
1221
1222 /* disable delay interrupt */
1223 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1224
1225 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1226
1227 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1228 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1229 for (i = 0; i < 16; i += 2)
1230 fe_w32(((i + 1) << 16) + i,
1231 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1232 (i * 2));
1233
1234 if (priv->soc->fwd_config(priv))
1235 netdev_err(dev, "unable to get clock\n");
1236
1237 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1238 fe_reg_w32(1, FE_REG_FE_RST_GL);
1239 fe_reg_w32(0, FE_REG_FE_RST_GL);
1240 }
1241
1242 return 0;
1243 }
1244
1245 static int fe_open(struct net_device *dev)
1246 {
1247 struct fe_priv *priv = netdev_priv(dev);
1248 unsigned long flags;
1249 u32 val;
1250 int err;
1251
1252 err = fe_init_dma(priv);
1253 if (err) {
1254 fe_free_dma(priv);
1255 return err;
1256 }
1257
1258 spin_lock_irqsave(&priv->page_lock, flags);
1259
1260 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1261 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1262 val |= FE_RX_2B_OFFSET;
1263 val |= priv->soc->pdma_glo_cfg;
1264 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1265
1266 spin_unlock_irqrestore(&priv->page_lock, flags);
1267
1268 if (priv->phy)
1269 priv->phy->start(priv);
1270
1271 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1272 netif_carrier_on(dev);
1273
1274 napi_enable(&priv->rx_napi);
1275 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1276 netif_start_queue(dev);
1277 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1278 mtk_ppe_probe(priv);
1279 #endif
1280
1281 return 0;
1282 }
1283
1284 static int fe_stop(struct net_device *dev)
1285 {
1286 struct fe_priv *priv = netdev_priv(dev);
1287 unsigned long flags;
1288 int i;
1289
1290 netif_tx_disable(dev);
1291 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1292 napi_disable(&priv->rx_napi);
1293
1294 if (priv->phy)
1295 priv->phy->stop(priv);
1296
1297 spin_lock_irqsave(&priv->page_lock, flags);
1298
1299 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1300 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1301 FE_REG_PDMA_GLO_CFG);
1302 spin_unlock_irqrestore(&priv->page_lock, flags);
1303
1304 /* wait dma stop */
1305 for (i = 0; i < 10; i++) {
1306 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1307 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1308 msleep(20);
1309 continue;
1310 }
1311 break;
1312 }
1313
1314 fe_free_dma(priv);
1315
1316 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1317 mtk_ppe_remove(priv);
1318 #endif
1319
1320 return 0;
1321 }
1322
1323 static int __init fe_init(struct net_device *dev)
1324 {
1325 struct fe_priv *priv = netdev_priv(dev);
1326 struct device_node *port;
1327 const char *mac_addr;
1328 int err;
1329
1330 priv->soc->reset_fe();
1331
1332 if (priv->soc->switch_init)
1333 if (priv->soc->switch_init(priv)) {
1334 netdev_err(dev, "failed to initialize switch core\n");
1335 return -ENODEV;
1336 }
1337
1338 mac_addr = of_get_mac_address(priv->dev->of_node);
1339 if (mac_addr)
1340 ether_addr_copy(dev->dev_addr, mac_addr);
1341
1342 /* If the mac address is invalid, use random mac address */
1343 if (!is_valid_ether_addr(dev->dev_addr)) {
1344 random_ether_addr(dev->dev_addr);
1345 dev_err(priv->dev, "generated random MAC address %pM\n",
1346 dev->dev_addr);
1347 }
1348
1349 err = fe_mdio_init(priv);
1350 if (err)
1351 return err;
1352
1353 if (priv->soc->port_init)
1354 for_each_child_of_node(priv->dev->of_node, port)
1355 if (of_device_is_compatible(port, "mediatek,eth-port") &&
1356 of_device_is_available(port))
1357 priv->soc->port_init(priv, port);
1358
1359 if (priv->phy) {
1360 err = priv->phy->connect(priv);
1361 if (err)
1362 goto err_phy_disconnect;
1363 }
1364
1365 err = fe_hw_init(dev);
1366 if (err)
1367 goto err_phy_disconnect;
1368
1369 if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1370 priv->soc->switch_config(priv);
1371
1372 return 0;
1373
1374 err_phy_disconnect:
1375 if (priv->phy)
1376 priv->phy->disconnect(priv);
1377 fe_mdio_cleanup(priv);
1378
1379 return err;
1380 }
1381
1382 static void fe_uninit(struct net_device *dev)
1383 {
1384 struct fe_priv *priv = netdev_priv(dev);
1385
1386 if (priv->phy)
1387 priv->phy->disconnect(priv);
1388 fe_mdio_cleanup(priv);
1389
1390 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1391 free_irq(dev->irq, dev);
1392 }
1393
1394 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1395 {
1396 struct fe_priv *priv = netdev_priv(dev);
1397
1398 if (!priv->phy_dev)
1399 return -ENODEV;
1400
1401 switch (cmd) {
1402 case SIOCETHTOOL:
1403 return phy_ethtool_ioctl(priv->phy_dev,
1404 (void *) ifr->ifr_data);
1405 case SIOCGMIIPHY:
1406 case SIOCGMIIREG:
1407 case SIOCSMIIREG:
1408 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1409 default:
1410 break;
1411 }
1412
1413 return -EOPNOTSUPP;
1414 }
1415
1416 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1417 {
1418 struct fe_priv *priv = netdev_priv(dev);
1419 int frag_size, old_mtu;
1420 u32 fwd_cfg;
1421
1422 old_mtu = dev->mtu;
1423 dev->mtu = new_mtu;
1424
1425 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1426 return 0;
1427
1428 /* return early if the buffer sizes will not change */
1429 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1430 return 0;
1431 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1432 return 0;
1433
1434 if (new_mtu <= ETH_DATA_LEN)
1435 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1436 else
1437 priv->rx_ring.frag_size = PAGE_SIZE;
1438 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1439
1440 if (!netif_running(dev))
1441 return 0;
1442
1443 fe_stop(dev);
1444 if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
1445 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1446 if (new_mtu <= ETH_DATA_LEN) {
1447 fwd_cfg &= ~FE_GDM1_JMB_EN;
1448 } else {
1449 frag_size = fe_max_frag_size(new_mtu);
1450 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1451 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1452 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1453 }
1454 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1455 }
1456
1457 return fe_open(dev);
1458 }
1459
1460 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1461 static int
1462 fe_flow_offload(enum flow_offload_type type, struct flow_offload *flow,
1463 struct flow_offload_hw_path *src,
1464 struct flow_offload_hw_path *dest)
1465 {
1466 struct fe_priv *priv;
1467
1468 if (src->dev != dest->dev)
1469 return -EINVAL;
1470
1471 priv = netdev_priv(src->dev);
1472
1473 return mtk_flow_offload(priv, type, flow, src, dest);
1474 }
1475 #endif
1476
1477 static const struct net_device_ops fe_netdev_ops = {
1478 .ndo_init = fe_init,
1479 .ndo_uninit = fe_uninit,
1480 .ndo_open = fe_open,
1481 .ndo_stop = fe_stop,
1482 .ndo_start_xmit = fe_start_xmit,
1483 .ndo_set_mac_address = fe_set_mac_address,
1484 .ndo_validate_addr = eth_validate_addr,
1485 .ndo_do_ioctl = fe_do_ioctl,
1486 .ndo_change_mtu = fe_change_mtu,
1487 .ndo_tx_timeout = fe_tx_timeout,
1488 .ndo_get_stats64 = fe_get_stats64,
1489 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1490 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1491 #ifdef CONFIG_NET_POLL_CONTROLLER
1492 .ndo_poll_controller = fe_poll_controller,
1493 #endif
1494 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1495 .ndo_flow_offload = fe_flow_offload,
1496 #endif
1497 };
1498
1499 static void fe_reset_pending(struct fe_priv *priv)
1500 {
1501 struct net_device *dev = priv->netdev;
1502 int err;
1503
1504 rtnl_lock();
1505 fe_stop(dev);
1506
1507 err = fe_open(dev);
1508 if (err) {
1509 netif_alert(priv, ifup, dev,
1510 "Driver up/down cycle failed, closing device.\n");
1511 dev_close(dev);
1512 }
1513 rtnl_unlock();
1514 }
1515
1516 static const struct fe_work_t fe_work[] = {
1517 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1518 };
1519
1520 static void fe_pending_work(struct work_struct *work)
1521 {
1522 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1523 int i;
1524 bool pending;
1525
1526 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1527 pending = test_and_clear_bit(fe_work[i].bitnr,
1528 priv->pending_flags);
1529 if (pending)
1530 fe_work[i].action(priv);
1531 }
1532 }
1533
1534 static int fe_probe(struct platform_device *pdev)
1535 {
1536 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537 const struct of_device_id *match;
1538 struct fe_soc_data *soc;
1539 struct net_device *netdev;
1540 struct fe_priv *priv;
1541 struct clk *sysclk;
1542 int err, napi_weight;
1543
1544 device_reset(&pdev->dev);
1545
1546 match = of_match_device(of_fe_match, &pdev->dev);
1547 soc = (struct fe_soc_data *)match->data;
1548
1549 if (soc->reg_table)
1550 fe_reg_table = soc->reg_table;
1551 else
1552 soc->reg_table = fe_reg_table;
1553
1554 fe_base = devm_ioremap_resource(&pdev->dev, res);
1555 if (IS_ERR(fe_base)) {
1556 err = -EADDRNOTAVAIL;
1557 goto err_out;
1558 }
1559
1560 netdev = alloc_etherdev(sizeof(*priv));
1561 if (!netdev) {
1562 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1563 err = -ENOMEM;
1564 goto err_iounmap;
1565 }
1566
1567 SET_NETDEV_DEV(netdev, &pdev->dev);
1568 netdev->netdev_ops = &fe_netdev_ops;
1569 netdev->base_addr = (unsigned long)fe_base;
1570
1571 netdev->irq = platform_get_irq(pdev, 0);
1572 if (netdev->irq < 0) {
1573 dev_err(&pdev->dev, "no IRQ resource found\n");
1574 err = -ENXIO;
1575 goto err_free_dev;
1576 }
1577
1578 if (soc->init_data)
1579 soc->init_data(soc, netdev);
1580 netdev->vlan_features = netdev->hw_features & ~NETIF_F_HW_VLAN_CTAG_TX;
1581 netdev->features |= netdev->hw_features;
1582
1583 if (IS_ENABLED(CONFIG_SOC_MT7621))
1584 netdev->max_mtu = 2048;
1585
1586 /* fake rx vlan filter func. to support tx vlan offload func */
1587 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1588 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1589
1590 priv = netdev_priv(netdev);
1591 spin_lock_init(&priv->page_lock);
1592 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1593 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1594 if (!priv->hw_stats) {
1595 err = -ENOMEM;
1596 goto err_free_dev;
1597 }
1598 spin_lock_init(&priv->hw_stats->stats_lock);
1599 }
1600
1601 sysclk = devm_clk_get(&pdev->dev, NULL);
1602 if (!IS_ERR(sysclk)) {
1603 priv->sysclk = clk_get_rate(sysclk);
1604 } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
1605 dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
1606 err = -ENXIO;
1607 goto err_free_dev;
1608 }
1609
1610 priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
1611 if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
1612 dev_err(&pdev->dev, "failed to read switch phandle\n");
1613 err = -ENODEV;
1614 goto err_free_dev;
1615 }
1616
1617 priv->netdev = netdev;
1618 priv->dev = &pdev->dev;
1619 priv->soc = soc;
1620 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1621 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1622 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1623 priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
1624 priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1625 INIT_WORK(&priv->pending_work, fe_pending_work);
1626 u64_stats_init(&priv->hw_stats->syncp);
1627
1628 napi_weight = 16;
1629 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1630 napi_weight *= 4;
1631 priv->tx_ring.tx_ring_size *= 4;
1632 priv->rx_ring.rx_ring_size *= 4;
1633 }
1634 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1635 fe_set_ethtool_ops(netdev);
1636
1637 err = register_netdev(netdev);
1638 if (err) {
1639 dev_err(&pdev->dev, "error bringing up device\n");
1640 goto err_free_dev;
1641 }
1642
1643 platform_set_drvdata(pdev, netdev);
1644
1645 netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
1646 netdev->base_addr, netdev->irq);
1647
1648 return 0;
1649
1650 err_free_dev:
1651 free_netdev(netdev);
1652 err_iounmap:
1653 devm_iounmap(&pdev->dev, fe_base);
1654 err_out:
1655 return err;
1656 }
1657
1658 static int fe_remove(struct platform_device *pdev)
1659 {
1660 struct net_device *dev = platform_get_drvdata(pdev);
1661 struct fe_priv *priv = netdev_priv(dev);
1662
1663 netif_napi_del(&priv->rx_napi);
1664 kfree(priv->hw_stats);
1665
1666 cancel_work_sync(&priv->pending_work);
1667
1668 unregister_netdev(dev);
1669 free_netdev(dev);
1670 platform_set_drvdata(pdev, NULL);
1671
1672 return 0;
1673 }
1674
1675 static struct platform_driver fe_driver = {
1676 .probe = fe_probe,
1677 .remove = fe_remove,
1678 .driver = {
1679 .name = "mtk_soc_eth",
1680 .owner = THIS_MODULE,
1681 .of_match_table = of_fe_match,
1682 },
1683 };
1684
1685 module_platform_driver(fe_driver);
1686
1687 MODULE_LICENSE("GPL");
1688 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1689 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1690 MODULE_VERSION(MTK_FE_DRV_VERSION);