ramips: mt7621: fix mtu setting with kernel 4.14
[openwrt/openwrt.git] / target / linux / ramips / files-4.14 / drivers / net / ethernet / mediatek / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
31 #include <linux/io.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "mtk_eth_soc.h"
39 #include "mdio.h"
40 #include "ethtool.h"
41
42 #define MAX_RX_LENGTH 1536
43 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
44 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
45 #define DMA_DUMMY_DESC 0xffffffff
46 #define FE_DEFAULT_MSG_ENABLE \
47 (NETIF_MSG_DRV | \
48 NETIF_MSG_PROBE | \
49 NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_IFDOWN | \
52 NETIF_MSG_IFUP | \
53 NETIF_MSG_RX_ERR | \
54 NETIF_MSG_TX_ERR)
55
56 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
57 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
58 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
59 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
60
61 #define SYSC_REG_RSTCTRL 0x34
62
63 static int fe_msg_level = -1;
64 module_param_named(msg_level, fe_msg_level, int, 0);
65 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
66
67 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
68 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
69 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
70 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
71 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
72 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
73 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
74 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
79 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
80 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
81 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
82 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
83 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
84 };
85
86 static const u16 *fe_reg_table = fe_reg_table_default;
87
88 struct fe_work_t {
89 int bitnr;
90 void (*action)(struct fe_priv *);
91 };
92
93 static void __iomem *fe_base;
94
95 void fe_w32(u32 val, unsigned reg)
96 {
97 __raw_writel(val, fe_base + reg);
98 }
99
100 u32 fe_r32(unsigned reg)
101 {
102 return __raw_readl(fe_base + reg);
103 }
104
105 void fe_reg_w32(u32 val, enum fe_reg reg)
106 {
107 fe_w32(val, fe_reg_table[reg]);
108 }
109
110 u32 fe_reg_r32(enum fe_reg reg)
111 {
112 return fe_r32(fe_reg_table[reg]);
113 }
114
115 void fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg)
116 {
117 u32 val;
118
119 spin_lock(&eth->page_lock);
120 val = __raw_readl(fe_base + reg);
121 val &= ~clear;
122 val |= set;
123 __raw_writel(val, fe_base + reg);
124 spin_unlock(&eth->page_lock);
125 }
126
127 void fe_reset(u32 reset_bits)
128 {
129 u32 t;
130
131 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
132 t |= reset_bits;
133 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
134 usleep_range(10, 20);
135
136 t &= ~reset_bits;
137 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
138 usleep_range(10, 20);
139 }
140
141 static inline void fe_int_disable(u32 mask)
142 {
143 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
144 FE_REG_FE_INT_ENABLE);
145 /* flush write */
146 fe_reg_r32(FE_REG_FE_INT_ENABLE);
147 }
148
149 static inline void fe_int_enable(u32 mask)
150 {
151 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
152 FE_REG_FE_INT_ENABLE);
153 /* flush write */
154 fe_reg_r32(FE_REG_FE_INT_ENABLE);
155 }
156
157 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
158 {
159 unsigned long flags;
160
161 spin_lock_irqsave(&priv->page_lock, flags);
162 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
163 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
164 FE_GDMA1_MAC_ADRL);
165 spin_unlock_irqrestore(&priv->page_lock, flags);
166 }
167
168 static int fe_set_mac_address(struct net_device *dev, void *p)
169 {
170 int ret = eth_mac_addr(dev, p);
171
172 if (!ret) {
173 struct fe_priv *priv = netdev_priv(dev);
174
175 if (priv->soc->set_mac)
176 priv->soc->set_mac(priv, dev->dev_addr);
177 else
178 fe_hw_set_macaddr(priv, p);
179 }
180
181 return ret;
182 }
183
184 static inline int fe_max_frag_size(int mtu)
185 {
186 /* make sure buf_size will be at least MAX_RX_LENGTH */
187 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
188 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
189
190 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
191 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
192 }
193
194 static inline int fe_max_buf_size(int frag_size)
195 {
196 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
197 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
198
199 BUG_ON(buf_size < MAX_RX_LENGTH);
200 return buf_size;
201 }
202
203 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
204 {
205 rxd->rxd1 = dma_rxd->rxd1;
206 rxd->rxd2 = dma_rxd->rxd2;
207 rxd->rxd3 = dma_rxd->rxd3;
208 rxd->rxd4 = dma_rxd->rxd4;
209 }
210
211 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
212 {
213 dma_txd->txd1 = txd->txd1;
214 dma_txd->txd3 = txd->txd3;
215 dma_txd->txd4 = txd->txd4;
216 /* clean dma done flag last */
217 dma_txd->txd2 = txd->txd2;
218 }
219
220 static void fe_clean_rx(struct fe_priv *priv)
221 {
222 int i;
223 struct fe_rx_ring *ring = &priv->rx_ring;
224
225 if (ring->rx_data) {
226 for (i = 0; i < ring->rx_ring_size; i++)
227 if (ring->rx_data[i]) {
228 if (ring->rx_dma && ring->rx_dma[i].rxd1)
229 dma_unmap_single(&priv->netdev->dev,
230 ring->rx_dma[i].rxd1,
231 ring->rx_buf_size,
232 DMA_FROM_DEVICE);
233 put_page(virt_to_head_page(ring->rx_data[i]));
234 }
235
236 kfree(ring->rx_data);
237 ring->rx_data = NULL;
238 }
239
240 if (ring->rx_dma) {
241 dma_free_coherent(&priv->netdev->dev,
242 ring->rx_ring_size * sizeof(*ring->rx_dma),
243 ring->rx_dma,
244 ring->rx_phys);
245 ring->rx_dma = NULL;
246 }
247 }
248
249 static int fe_alloc_rx(struct fe_priv *priv)
250 {
251 struct net_device *netdev = priv->netdev;
252 struct fe_rx_ring *ring = &priv->rx_ring;
253 int i, pad;
254
255 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
256 GFP_KERNEL);
257 if (!ring->rx_data)
258 goto no_rx_mem;
259
260 for (i = 0; i < ring->rx_ring_size; i++) {
261 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
262 if (!ring->rx_data[i])
263 goto no_rx_mem;
264 }
265
266 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
267 ring->rx_ring_size * sizeof(*ring->rx_dma),
268 &ring->rx_phys,
269 GFP_ATOMIC | __GFP_ZERO);
270 if (!ring->rx_dma)
271 goto no_rx_mem;
272
273 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
274 pad = 0;
275 else
276 pad = NET_IP_ALIGN;
277 for (i = 0; i < ring->rx_ring_size; i++) {
278 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
279 ring->rx_data[i] + NET_SKB_PAD + pad,
280 ring->rx_buf_size,
281 DMA_FROM_DEVICE);
282 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
283 goto no_rx_mem;
284 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
285
286 if (priv->flags & FE_FLAG_RX_SG_DMA)
287 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
288 else
289 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
290 }
291 ring->rx_calc_idx = ring->rx_ring_size - 1;
292 /* make sure that all changes to the dma ring are flushed before we
293 * continue
294 */
295 wmb();
296
297 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
298 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
299 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
300 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
301
302 return 0;
303
304 no_rx_mem:
305 return -ENOMEM;
306 }
307
308 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
309 {
310 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
311 dma_unmap_single(dev,
312 dma_unmap_addr(tx_buf, dma_addr0),
313 dma_unmap_len(tx_buf, dma_len0),
314 DMA_TO_DEVICE);
315 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
316 dma_unmap_page(dev,
317 dma_unmap_addr(tx_buf, dma_addr0),
318 dma_unmap_len(tx_buf, dma_len0),
319 DMA_TO_DEVICE);
320 }
321 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
322 dma_unmap_page(dev,
323 dma_unmap_addr(tx_buf, dma_addr1),
324 dma_unmap_len(tx_buf, dma_len1),
325 DMA_TO_DEVICE);
326
327 tx_buf->flags = 0;
328 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
329 dev_kfree_skb_any(tx_buf->skb);
330 tx_buf->skb = NULL;
331 }
332
333 static void fe_clean_tx(struct fe_priv *priv)
334 {
335 int i;
336 struct device *dev = &priv->netdev->dev;
337 struct fe_tx_ring *ring = &priv->tx_ring;
338
339 if (ring->tx_buf) {
340 for (i = 0; i < ring->tx_ring_size; i++)
341 fe_txd_unmap(dev, &ring->tx_buf[i]);
342 kfree(ring->tx_buf);
343 ring->tx_buf = NULL;
344 }
345
346 if (ring->tx_dma) {
347 dma_free_coherent(dev,
348 ring->tx_ring_size * sizeof(*ring->tx_dma),
349 ring->tx_dma,
350 ring->tx_phys);
351 ring->tx_dma = NULL;
352 }
353
354 netdev_reset_queue(priv->netdev);
355 }
356
357 static int fe_alloc_tx(struct fe_priv *priv)
358 {
359 int i;
360 struct fe_tx_ring *ring = &priv->tx_ring;
361
362 ring->tx_free_idx = 0;
363 ring->tx_next_idx = 0;
364 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
365 MAX_SKB_FRAGS);
366
367 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
368 GFP_KERNEL);
369 if (!ring->tx_buf)
370 goto no_tx_mem;
371
372 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
373 ring->tx_ring_size * sizeof(*ring->tx_dma),
374 &ring->tx_phys,
375 GFP_ATOMIC | __GFP_ZERO);
376 if (!ring->tx_dma)
377 goto no_tx_mem;
378
379 for (i = 0; i < ring->tx_ring_size; i++) {
380 if (priv->soc->tx_dma)
381 priv->soc->tx_dma(&ring->tx_dma[i]);
382 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
383 }
384 /* make sure that all changes to the dma ring are flushed before we
385 * continue
386 */
387 wmb();
388
389 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
390 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
391 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
392 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
393
394 return 0;
395
396 no_tx_mem:
397 return -ENOMEM;
398 }
399
400 static int fe_init_dma(struct fe_priv *priv)
401 {
402 int err;
403
404 err = fe_alloc_tx(priv);
405 if (err)
406 return err;
407
408 err = fe_alloc_rx(priv);
409 if (err)
410 return err;
411
412 return 0;
413 }
414
415 static void fe_free_dma(struct fe_priv *priv)
416 {
417 fe_clean_tx(priv);
418 fe_clean_rx(priv);
419 }
420
421 void fe_stats_update(struct fe_priv *priv)
422 {
423 struct fe_hw_stats *hwstats = priv->hw_stats;
424 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
425 u64 stats;
426
427 u64_stats_update_begin(&hwstats->syncp);
428
429 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
430 hwstats->rx_bytes += fe_r32(base);
431 stats = fe_r32(base + 0x04);
432 if (stats)
433 hwstats->rx_bytes += (stats << 32);
434 hwstats->rx_packets += fe_r32(base + 0x08);
435 hwstats->rx_overflow += fe_r32(base + 0x10);
436 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
437 hwstats->rx_short_errors += fe_r32(base + 0x18);
438 hwstats->rx_long_errors += fe_r32(base + 0x1c);
439 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
440 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
441 hwstats->tx_skip += fe_r32(base + 0x28);
442 hwstats->tx_collisions += fe_r32(base + 0x2c);
443 hwstats->tx_bytes += fe_r32(base + 0x30);
444 stats = fe_r32(base + 0x34);
445 if (stats)
446 hwstats->tx_bytes += (stats << 32);
447 hwstats->tx_packets += fe_r32(base + 0x38);
448 } else {
449 hwstats->tx_bytes += fe_r32(base);
450 hwstats->tx_packets += fe_r32(base + 0x04);
451 hwstats->tx_skip += fe_r32(base + 0x08);
452 hwstats->tx_collisions += fe_r32(base + 0x0c);
453 hwstats->rx_bytes += fe_r32(base + 0x20);
454 hwstats->rx_packets += fe_r32(base + 0x24);
455 hwstats->rx_overflow += fe_r32(base + 0x28);
456 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
457 hwstats->rx_short_errors += fe_r32(base + 0x30);
458 hwstats->rx_long_errors += fe_r32(base + 0x34);
459 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
460 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
461 }
462
463 u64_stats_update_end(&hwstats->syncp);
464 }
465
466 static void fe_get_stats64(struct net_device *dev,
467 struct rtnl_link_stats64 *storage)
468 {
469 struct fe_priv *priv = netdev_priv(dev);
470 struct fe_hw_stats *hwstats = priv->hw_stats;
471 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
472 unsigned int start;
473
474 if (!base) {
475 netdev_stats_to_stats64(storage, &dev->stats);
476 return;
477 }
478
479 if (netif_running(dev) && netif_device_present(dev)) {
480 if (spin_trylock_bh(&hwstats->stats_lock)) {
481 fe_stats_update(priv);
482 spin_unlock_bh(&hwstats->stats_lock);
483 }
484 }
485
486 do {
487 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
488 storage->rx_packets = hwstats->rx_packets;
489 storage->tx_packets = hwstats->tx_packets;
490 storage->rx_bytes = hwstats->rx_bytes;
491 storage->tx_bytes = hwstats->tx_bytes;
492 storage->collisions = hwstats->tx_collisions;
493 storage->rx_length_errors = hwstats->rx_short_errors +
494 hwstats->rx_long_errors;
495 storage->rx_over_errors = hwstats->rx_overflow;
496 storage->rx_crc_errors = hwstats->rx_fcs_errors;
497 storage->rx_errors = hwstats->rx_checksum_errors;
498 storage->tx_aborted_errors = hwstats->tx_skip;
499 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
500
501 storage->tx_errors = priv->netdev->stats.tx_errors;
502 storage->rx_dropped = priv->netdev->stats.rx_dropped;
503 storage->tx_dropped = priv->netdev->stats.tx_dropped;
504 }
505
506 static int fe_vlan_rx_add_vid(struct net_device *dev,
507 __be16 proto, u16 vid)
508 {
509 struct fe_priv *priv = netdev_priv(dev);
510 u32 idx = (vid & 0xf);
511 u32 vlan_cfg;
512
513 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
514 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
515 return 0;
516
517 if (test_bit(idx, &priv->vlan_map)) {
518 netdev_warn(dev, "disable tx vlan offload\n");
519 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
520 netdev_update_features(dev);
521 } else {
522 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
523 ((idx >> 1) << 2));
524 if (idx & 0x1) {
525 vlan_cfg &= 0xffff;
526 vlan_cfg |= (vid << 16);
527 } else {
528 vlan_cfg &= 0xffff0000;
529 vlan_cfg |= vid;
530 }
531 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
532 ((idx >> 1) << 2));
533 set_bit(idx, &priv->vlan_map);
534 }
535
536 return 0;
537 }
538
539 static int fe_vlan_rx_kill_vid(struct net_device *dev,
540 __be16 proto, u16 vid)
541 {
542 struct fe_priv *priv = netdev_priv(dev);
543 u32 idx = (vid & 0xf);
544
545 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
546 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
547 return 0;
548
549 clear_bit(idx, &priv->vlan_map);
550
551 return 0;
552 }
553
554 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
555 {
556 barrier();
557 return (u32)(ring->tx_ring_size -
558 ((ring->tx_next_idx - ring->tx_free_idx) &
559 (ring->tx_ring_size - 1)));
560 }
561
562 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
563 int tx_num, struct fe_tx_ring *ring)
564 {
565 struct fe_priv *priv = netdev_priv(dev);
566 struct skb_frag_struct *frag;
567 struct fe_tx_dma txd, *ptxd;
568 struct fe_tx_buf *tx_buf;
569 dma_addr_t mapped_addr;
570 unsigned int nr_frags;
571 u32 def_txd4;
572 int i, j, k, frag_size, frag_map_size, offset;
573
574 tx_buf = &ring->tx_buf[ring->tx_next_idx];
575 memset(tx_buf, 0, sizeof(*tx_buf));
576 memset(&txd, 0, sizeof(txd));
577 nr_frags = skb_shinfo(skb)->nr_frags;
578
579 /* init tx descriptor */
580 if (priv->soc->tx_dma)
581 priv->soc->tx_dma(&txd);
582 else
583 txd.txd4 = TX_DMA_DESP4_DEF;
584 def_txd4 = txd.txd4;
585
586 /* TX Checksum offload */
587 if (skb->ip_summed == CHECKSUM_PARTIAL)
588 txd.txd4 |= TX_DMA_CHKSUM;
589
590 /* VLAN header offload */
591 if (skb_vlan_tag_present(skb)) {
592 u16 tag = skb_vlan_tag_get(skb);
593
594 if (IS_ENABLED(CONFIG_SOC_MT7621))
595 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
596 else
597 txd.txd4 |= TX_DMA_INS_VLAN |
598 ((tag >> VLAN_PRIO_SHIFT) << 4) |
599 (tag & 0xF);
600 }
601
602 /* TSO: fill MSS info in tcp checksum field */
603 if (skb_is_gso(skb)) {
604 if (skb_cow_head(skb, 0)) {
605 netif_warn(priv, tx_err, dev,
606 "GSO expand head fail.\n");
607 goto err_out;
608 }
609 if (skb_shinfo(skb)->gso_type &
610 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
611 txd.txd4 |= TX_DMA_TSO;
612 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
613 }
614 }
615
616 mapped_addr = dma_map_single(&dev->dev, skb->data,
617 skb_headlen(skb), DMA_TO_DEVICE);
618 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
619 goto err_out;
620 txd.txd1 = mapped_addr;
621 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
622
623 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
624 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
625 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
626
627 /* TX SG offload */
628 j = ring->tx_next_idx;
629 k = 0;
630 for (i = 0; i < nr_frags; i++) {
631 offset = 0;
632 frag = &skb_shinfo(skb)->frags[i];
633 frag_size = skb_frag_size(frag);
634
635 while (frag_size > 0) {
636 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
637 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
638 frag_map_size,
639 DMA_TO_DEVICE);
640 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
641 goto err_dma;
642
643 if (k & 0x1) {
644 j = NEXT_TX_DESP_IDX(j);
645 txd.txd1 = mapped_addr;
646 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
647 txd.txd4 = def_txd4;
648
649 tx_buf = &ring->tx_buf[j];
650 memset(tx_buf, 0, sizeof(*tx_buf));
651
652 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
653 dma_unmap_addr_set(tx_buf, dma_addr0,
654 mapped_addr);
655 dma_unmap_len_set(tx_buf, dma_len0,
656 frag_map_size);
657 } else {
658 txd.txd3 = mapped_addr;
659 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
660
661 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
662 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
663 dma_unmap_addr_set(tx_buf, dma_addr1,
664 mapped_addr);
665 dma_unmap_len_set(tx_buf, dma_len1,
666 frag_map_size);
667
668 if (!((i == (nr_frags - 1)) &&
669 (frag_map_size == frag_size))) {
670 fe_set_txd(&txd, &ring->tx_dma[j]);
671 memset(&txd, 0, sizeof(txd));
672 }
673 }
674 frag_size -= frag_map_size;
675 offset += frag_map_size;
676 k++;
677 }
678 }
679
680 /* set last segment */
681 if (k & 0x1)
682 txd.txd2 |= TX_DMA_LS1;
683 else
684 txd.txd2 |= TX_DMA_LS0;
685 fe_set_txd(&txd, &ring->tx_dma[j]);
686
687 /* store skb to cleanup */
688 tx_buf->skb = skb;
689
690 netdev_sent_queue(dev, skb->len);
691 skb_tx_timestamp(skb);
692
693 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
694 /* make sure that all changes to the dma ring are flushed before we
695 * continue
696 */
697 wmb();
698 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
699 netif_stop_queue(dev);
700 smp_mb();
701 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
702 netif_wake_queue(dev);
703 }
704
705 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
706 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
707
708 return 0;
709
710 err_dma:
711 j = ring->tx_next_idx;
712 for (i = 0; i < tx_num; i++) {
713 ptxd = &ring->tx_dma[j];
714 tx_buf = &ring->tx_buf[j];
715
716 /* unmap dma */
717 fe_txd_unmap(&dev->dev, tx_buf);
718
719 ptxd->txd2 = TX_DMA_DESP2_DEF;
720 j = NEXT_TX_DESP_IDX(j);
721 }
722 /* make sure that all changes to the dma ring are flushed before we
723 * continue
724 */
725 wmb();
726
727 err_out:
728 return -1;
729 }
730
731 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
732 {
733 unsigned int len;
734 int ret;
735
736 ret = 0;
737 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
738 if ((priv->flags & FE_FLAG_PADDING_64B) &&
739 !(priv->flags & FE_FLAG_PADDING_BUG))
740 return ret;
741
742 if (skb_vlan_tag_present(skb))
743 len = ETH_ZLEN;
744 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
745 len = VLAN_ETH_ZLEN;
746 else if (!(priv->flags & FE_FLAG_PADDING_64B))
747 len = ETH_ZLEN;
748 else
749 return ret;
750
751 if (skb->len < len) {
752 ret = skb_pad(skb, len - skb->len);
753 if (ret < 0)
754 return ret;
755 skb->len = len;
756 skb_set_tail_pointer(skb, len);
757 }
758 }
759
760 return ret;
761 }
762
763 static inline int fe_cal_txd_req(struct sk_buff *skb)
764 {
765 int i, nfrags;
766 struct skb_frag_struct *frag;
767
768 nfrags = 1;
769 if (skb_is_gso(skb)) {
770 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
771 frag = &skb_shinfo(skb)->frags[i];
772 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
773 }
774 } else {
775 nfrags += skb_shinfo(skb)->nr_frags;
776 }
777
778 return DIV_ROUND_UP(nfrags, 2);
779 }
780
781 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
782 {
783 struct fe_priv *priv = netdev_priv(dev);
784 struct fe_tx_ring *ring = &priv->tx_ring;
785 struct net_device_stats *stats = &dev->stats;
786 int tx_num;
787 int len = skb->len;
788
789 if (fe_skb_padto(skb, priv)) {
790 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
791 return NETDEV_TX_OK;
792 }
793
794 tx_num = fe_cal_txd_req(skb);
795 if (unlikely(fe_empty_txd(ring) <= tx_num)) {
796 netif_stop_queue(dev);
797 netif_err(priv, tx_queued, dev,
798 "Tx Ring full when queue awake!\n");
799 return NETDEV_TX_BUSY;
800 }
801
802 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
803 stats->tx_dropped++;
804 } else {
805 stats->tx_packets++;
806 stats->tx_bytes += len;
807 }
808
809 return NETDEV_TX_OK;
810 }
811
812 static int fe_poll_rx(struct napi_struct *napi, int budget,
813 struct fe_priv *priv, u32 rx_intr)
814 {
815 struct net_device *netdev = priv->netdev;
816 struct net_device_stats *stats = &netdev->stats;
817 struct fe_soc_data *soc = priv->soc;
818 struct fe_rx_ring *ring = &priv->rx_ring;
819 int idx = ring->rx_calc_idx;
820 u32 checksum_bit;
821 struct sk_buff *skb;
822 u8 *data, *new_data;
823 struct fe_rx_dma *rxd, trxd;
824 int done = 0, pad;
825
826 if (netdev->features & NETIF_F_RXCSUM)
827 checksum_bit = soc->checksum_bit;
828 else
829 checksum_bit = 0;
830
831 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
832 pad = 0;
833 else
834 pad = NET_IP_ALIGN;
835
836 while (done < budget) {
837 unsigned int pktlen;
838 dma_addr_t dma_addr;
839
840 idx = NEXT_RX_DESP_IDX(idx);
841 rxd = &ring->rx_dma[idx];
842 data = ring->rx_data[idx];
843
844 fe_get_rxd(&trxd, rxd);
845 if (!(trxd.rxd2 & RX_DMA_DONE))
846 break;
847
848 /* alloc new buffer */
849 new_data = netdev_alloc_frag(ring->frag_size);
850 if (unlikely(!new_data)) {
851 stats->rx_dropped++;
852 goto release_desc;
853 }
854 dma_addr = dma_map_single(&netdev->dev,
855 new_data + NET_SKB_PAD + pad,
856 ring->rx_buf_size,
857 DMA_FROM_DEVICE);
858 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
859 put_page(virt_to_head_page(new_data));
860 goto release_desc;
861 }
862
863 /* receive data */
864 skb = build_skb(data, ring->frag_size);
865 if (unlikely(!skb)) {
866 put_page(virt_to_head_page(new_data));
867 goto release_desc;
868 }
869 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
870
871 dma_unmap_single(&netdev->dev, trxd.rxd1,
872 ring->rx_buf_size, DMA_FROM_DEVICE);
873 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
874 skb->dev = netdev;
875 skb_put(skb, pktlen);
876 if (trxd.rxd4 & checksum_bit)
877 skb->ip_summed = CHECKSUM_UNNECESSARY;
878 else
879 skb_checksum_none_assert(skb);
880 skb->protocol = eth_type_trans(skb, netdev);
881
882 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
883 if (mtk_offload_check_rx(priv, skb, trxd.rxd4) == 0) {
884 #endif
885 stats->rx_packets++;
886 stats->rx_bytes += pktlen;
887
888 napi_gro_receive(napi, skb);
889 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
890 } else {
891 dev_kfree_skb(skb);
892 }
893 #endif
894 ring->rx_data[idx] = new_data;
895 rxd->rxd1 = (unsigned int)dma_addr;
896
897 release_desc:
898 if (priv->flags & FE_FLAG_RX_SG_DMA)
899 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
900 else
901 rxd->rxd2 = RX_DMA_LSO;
902
903 ring->rx_calc_idx = idx;
904 /* make sure that all changes to the dma ring are flushed before
905 * we continue
906 */
907 wmb();
908 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
909 done++;
910 }
911
912 if (done < budget)
913 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
914
915 return done;
916 }
917
918 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
919 int *tx_again)
920 {
921 struct net_device *netdev = priv->netdev;
922 struct device *dev = &netdev->dev;
923 unsigned int bytes_compl = 0;
924 struct sk_buff *skb;
925 struct fe_tx_buf *tx_buf;
926 int done = 0;
927 u32 idx, hwidx;
928 struct fe_tx_ring *ring = &priv->tx_ring;
929
930 idx = ring->tx_free_idx;
931 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
932
933 while ((idx != hwidx) && budget) {
934 tx_buf = &ring->tx_buf[idx];
935 skb = tx_buf->skb;
936
937 if (!skb)
938 break;
939
940 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
941 bytes_compl += skb->len;
942 done++;
943 budget--;
944 }
945 fe_txd_unmap(dev, tx_buf);
946 idx = NEXT_TX_DESP_IDX(idx);
947 }
948 ring->tx_free_idx = idx;
949
950 if (idx == hwidx) {
951 /* read hw index again make sure no new tx packet */
952 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
953 if (idx == hwidx)
954 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
955 else
956 *tx_again = 1;
957 } else {
958 *tx_again = 1;
959 }
960
961 if (done) {
962 netdev_completed_queue(netdev, done, bytes_compl);
963 smp_mb();
964 if (unlikely(netif_queue_stopped(netdev) &&
965 (fe_empty_txd(ring) > ring->tx_thresh)))
966 netif_wake_queue(netdev);
967 }
968
969 return done;
970 }
971
972 static int fe_poll(struct napi_struct *napi, int budget)
973 {
974 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
975 struct fe_hw_stats *hwstat = priv->hw_stats;
976 int tx_done, rx_done, tx_again;
977 u32 status, fe_status, status_reg, mask;
978 u32 tx_intr, rx_intr, status_intr;
979
980 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
981 fe_status = status;
982 tx_intr = priv->soc->tx_int;
983 rx_intr = priv->soc->rx_int;
984 status_intr = priv->soc->status_int;
985 tx_done = 0;
986 rx_done = 0;
987 tx_again = 0;
988
989 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
990 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
991 status_reg = FE_REG_FE_INT_STATUS2;
992 } else {
993 status_reg = FE_REG_FE_INT_STATUS;
994 }
995
996 if (status & tx_intr)
997 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
998
999 if (status & rx_intr)
1000 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
1001
1002 if (unlikely(fe_status & status_intr)) {
1003 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
1004 fe_stats_update(priv);
1005 spin_unlock(&hwstat->stats_lock);
1006 }
1007 fe_reg_w32(status_intr, status_reg);
1008 }
1009
1010 if (unlikely(netif_msg_intr(priv))) {
1011 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
1012 netdev_info(priv->netdev,
1013 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1014 tx_done, rx_done, status, mask);
1015 }
1016
1017 if (!tx_again && (rx_done < budget)) {
1018 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1019 if (status & (tx_intr | rx_intr)) {
1020 /* let napi poll again */
1021 rx_done = budget;
1022 goto poll_again;
1023 }
1024
1025 napi_complete_done(napi, rx_done);
1026 fe_int_enable(tx_intr | rx_intr);
1027 } else {
1028 rx_done = budget;
1029 }
1030
1031 poll_again:
1032 return rx_done;
1033 }
1034
1035 static void fe_tx_timeout(struct net_device *dev)
1036 {
1037 struct fe_priv *priv = netdev_priv(dev);
1038 struct fe_tx_ring *ring = &priv->tx_ring;
1039
1040 priv->netdev->stats.tx_errors++;
1041 netif_err(priv, tx_err, dev,
1042 "transmit timed out\n");
1043 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1044 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1045 netif_info(priv, drv, dev, "tx_ring=%d, "
1046 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1047 0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1048 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1049 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1050 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1051 ring->tx_free_idx,
1052 ring->tx_next_idx);
1053 netif_info(priv, drv, dev,
1054 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1055 0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1056 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1057 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1058 fe_reg_r32(FE_REG_RX_DRX_IDX0));
1059
1060 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1061 schedule_work(&priv->pending_work);
1062 }
1063
1064 static irqreturn_t fe_handle_irq(int irq, void *dev)
1065 {
1066 struct fe_priv *priv = netdev_priv(dev);
1067 u32 status, int_mask;
1068
1069 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1070
1071 if (unlikely(!status))
1072 return IRQ_NONE;
1073
1074 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1075 if (likely(status & int_mask)) {
1076 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1077 fe_int_disable(int_mask);
1078 __napi_schedule(&priv->rx_napi);
1079 }
1080 } else {
1081 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1082 }
1083
1084 return IRQ_HANDLED;
1085 }
1086
1087 #ifdef CONFIG_NET_POLL_CONTROLLER
1088 static void fe_poll_controller(struct net_device *dev)
1089 {
1090 struct fe_priv *priv = netdev_priv(dev);
1091 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1092
1093 fe_int_disable(int_mask);
1094 fe_handle_irq(dev->irq, dev);
1095 fe_int_enable(int_mask);
1096 }
1097 #endif
1098
1099 int fe_set_clock_cycle(struct fe_priv *priv)
1100 {
1101 unsigned long sysclk = priv->sysclk;
1102
1103 sysclk /= FE_US_CYC_CNT_DIVISOR;
1104 sysclk <<= FE_US_CYC_CNT_SHIFT;
1105
1106 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1107 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1108 sysclk,
1109 FE_FE_GLO_CFG);
1110 return 0;
1111 }
1112
1113 void fe_fwd_config(struct fe_priv *priv)
1114 {
1115 u32 fwd_cfg;
1116
1117 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1118
1119 /* disable jumbo frame */
1120 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1121 fwd_cfg &= ~FE_GDM1_JMB_EN;
1122
1123 /* set unicast/multicast/broadcast frame to cpu */
1124 fwd_cfg &= ~0xffff;
1125
1126 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1127 }
1128
1129 static void fe_rxcsum_config(bool enable)
1130 {
1131 if (enable)
1132 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1133 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1134 FE_GDMA1_FWD_CFG);
1135 else
1136 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1137 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1138 FE_GDMA1_FWD_CFG);
1139 }
1140
1141 static void fe_txcsum_config(bool enable)
1142 {
1143 if (enable)
1144 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1145 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1146 FE_CDMA_CSG_CFG);
1147 else
1148 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1149 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1150 FE_CDMA_CSG_CFG);
1151 }
1152
1153 void fe_csum_config(struct fe_priv *priv)
1154 {
1155 struct net_device *dev = priv_netdev(priv);
1156
1157 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1158 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1159 }
1160
1161 static int fe_hw_init(struct net_device *dev)
1162 {
1163 struct fe_priv *priv = netdev_priv(dev);
1164 int i, err;
1165
1166 err = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0,
1167 dev_name(priv->dev), dev);
1168 if (err)
1169 return err;
1170
1171 if (priv->soc->set_mac)
1172 priv->soc->set_mac(priv, dev->dev_addr);
1173 else
1174 fe_hw_set_macaddr(priv, dev->dev_addr);
1175
1176 /* disable delay interrupt */
1177 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1178
1179 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1180
1181 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1182 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1183 for (i = 0; i < 16; i += 2)
1184 fe_w32(((i + 1) << 16) + i,
1185 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1186 (i * 2));
1187
1188 if (priv->soc->fwd_config(priv))
1189 netdev_err(dev, "unable to get clock\n");
1190
1191 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1192 fe_reg_w32(1, FE_REG_FE_RST_GL);
1193 fe_reg_w32(0, FE_REG_FE_RST_GL);
1194 }
1195
1196 return 0;
1197 }
1198
1199 static int fe_open(struct net_device *dev)
1200 {
1201 struct fe_priv *priv = netdev_priv(dev);
1202 unsigned long flags;
1203 u32 val;
1204 int err;
1205
1206 err = fe_init_dma(priv);
1207 if (err) {
1208 fe_free_dma(priv);
1209 return err;
1210 }
1211
1212 spin_lock_irqsave(&priv->page_lock, flags);
1213
1214 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1215 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1216 val |= FE_RX_2B_OFFSET;
1217 val |= priv->soc->pdma_glo_cfg;
1218 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1219
1220 spin_unlock_irqrestore(&priv->page_lock, flags);
1221
1222 if (priv->phy)
1223 priv->phy->start(priv);
1224
1225 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1226 netif_carrier_on(dev);
1227
1228 napi_enable(&priv->rx_napi);
1229 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1230 netif_start_queue(dev);
1231 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1232 mtk_ppe_probe(priv);
1233 #endif
1234
1235 return 0;
1236 }
1237
1238 static int fe_stop(struct net_device *dev)
1239 {
1240 struct fe_priv *priv = netdev_priv(dev);
1241 unsigned long flags;
1242 int i;
1243
1244 netif_tx_disable(dev);
1245 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1246 napi_disable(&priv->rx_napi);
1247
1248 if (priv->phy)
1249 priv->phy->stop(priv);
1250
1251 spin_lock_irqsave(&priv->page_lock, flags);
1252
1253 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1254 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1255 FE_REG_PDMA_GLO_CFG);
1256 spin_unlock_irqrestore(&priv->page_lock, flags);
1257
1258 /* wait dma stop */
1259 for (i = 0; i < 10; i++) {
1260 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1261 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1262 msleep(20);
1263 continue;
1264 }
1265 break;
1266 }
1267
1268 fe_free_dma(priv);
1269
1270 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1271 mtk_ppe_remove(priv);
1272 #endif
1273
1274 return 0;
1275 }
1276
1277 static int __init fe_init(struct net_device *dev)
1278 {
1279 struct fe_priv *priv = netdev_priv(dev);
1280 struct device_node *port;
1281 const char *mac_addr;
1282 int err;
1283
1284 priv->soc->reset_fe();
1285
1286 if (priv->soc->switch_init)
1287 if (priv->soc->switch_init(priv)) {
1288 netdev_err(dev, "failed to initialize switch core\n");
1289 return -ENODEV;
1290 }
1291
1292 mac_addr = of_get_mac_address(priv->dev->of_node);
1293 if (mac_addr)
1294 ether_addr_copy(dev->dev_addr, mac_addr);
1295
1296 /* If the mac address is invalid, use random mac address */
1297 if (!is_valid_ether_addr(dev->dev_addr)) {
1298 random_ether_addr(dev->dev_addr);
1299 dev_err(priv->dev, "generated random MAC address %pM\n",
1300 dev->dev_addr);
1301 }
1302
1303 err = fe_mdio_init(priv);
1304 if (err)
1305 return err;
1306
1307 if (priv->soc->port_init)
1308 for_each_child_of_node(priv->dev->of_node, port)
1309 if (of_device_is_compatible(port, "mediatek,eth-port") &&
1310 of_device_is_available(port))
1311 priv->soc->port_init(priv, port);
1312
1313 if (priv->phy) {
1314 err = priv->phy->connect(priv);
1315 if (err)
1316 goto err_phy_disconnect;
1317 }
1318
1319 err = fe_hw_init(dev);
1320 if (err)
1321 goto err_phy_disconnect;
1322
1323 if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1324 priv->soc->switch_config(priv);
1325
1326 return 0;
1327
1328 err_phy_disconnect:
1329 if (priv->phy)
1330 priv->phy->disconnect(priv);
1331 fe_mdio_cleanup(priv);
1332
1333 return err;
1334 }
1335
1336 static void fe_uninit(struct net_device *dev)
1337 {
1338 struct fe_priv *priv = netdev_priv(dev);
1339
1340 if (priv->phy)
1341 priv->phy->disconnect(priv);
1342 fe_mdio_cleanup(priv);
1343
1344 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1345 free_irq(dev->irq, dev);
1346 }
1347
1348 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1349 {
1350 struct fe_priv *priv = netdev_priv(dev);
1351
1352 if (!priv->phy_dev)
1353 return -ENODEV;
1354
1355 switch (cmd) {
1356 case SIOCETHTOOL:
1357 return phy_ethtool_ioctl(priv->phy_dev,
1358 (void *) ifr->ifr_data);
1359 case SIOCGMIIPHY:
1360 case SIOCGMIIREG:
1361 case SIOCSMIIREG:
1362 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1363 default:
1364 break;
1365 }
1366
1367 return -EOPNOTSUPP;
1368 }
1369
1370 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1371 {
1372 struct fe_priv *priv = netdev_priv(dev);
1373 int frag_size, old_mtu;
1374 u32 fwd_cfg;
1375
1376 old_mtu = dev->mtu;
1377 dev->mtu = new_mtu;
1378
1379 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1380 return 0;
1381
1382 /* return early if the buffer sizes will not change */
1383 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1384 return 0;
1385 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1386 return 0;
1387
1388 if (new_mtu <= ETH_DATA_LEN)
1389 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1390 else
1391 priv->rx_ring.frag_size = PAGE_SIZE;
1392 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1393
1394 if (!netif_running(dev))
1395 return 0;
1396
1397 fe_stop(dev);
1398 if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
1399 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1400 if (new_mtu <= ETH_DATA_LEN) {
1401 fwd_cfg &= ~FE_GDM1_JMB_EN;
1402 } else {
1403 frag_size = fe_max_frag_size(new_mtu);
1404 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1405 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1406 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1407 }
1408 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1409 }
1410
1411 return fe_open(dev);
1412 }
1413
1414 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1415 static int
1416 fe_flow_offload(enum flow_offload_type type, struct flow_offload *flow,
1417 struct flow_offload_hw_path *src,
1418 struct flow_offload_hw_path *dest)
1419 {
1420 struct fe_priv *priv;
1421
1422 if (src->dev != dest->dev)
1423 return -EINVAL;
1424
1425 priv = netdev_priv(src->dev);
1426
1427 return mtk_flow_offload(priv, type, flow, src, dest);
1428 }
1429 #endif
1430
1431 static const struct net_device_ops fe_netdev_ops = {
1432 .ndo_init = fe_init,
1433 .ndo_uninit = fe_uninit,
1434 .ndo_open = fe_open,
1435 .ndo_stop = fe_stop,
1436 .ndo_start_xmit = fe_start_xmit,
1437 .ndo_set_mac_address = fe_set_mac_address,
1438 .ndo_validate_addr = eth_validate_addr,
1439 .ndo_do_ioctl = fe_do_ioctl,
1440 .ndo_change_mtu = fe_change_mtu,
1441 .ndo_tx_timeout = fe_tx_timeout,
1442 .ndo_get_stats64 = fe_get_stats64,
1443 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1444 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1445 #ifdef CONFIG_NET_POLL_CONTROLLER
1446 .ndo_poll_controller = fe_poll_controller,
1447 #endif
1448 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1449 .ndo_flow_offload = fe_flow_offload,
1450 #endif
1451 };
1452
1453 static void fe_reset_pending(struct fe_priv *priv)
1454 {
1455 struct net_device *dev = priv->netdev;
1456 int err;
1457
1458 rtnl_lock();
1459 fe_stop(dev);
1460
1461 err = fe_open(dev);
1462 if (err) {
1463 netif_alert(priv, ifup, dev,
1464 "Driver up/down cycle failed, closing device.\n");
1465 dev_close(dev);
1466 }
1467 rtnl_unlock();
1468 }
1469
1470 static const struct fe_work_t fe_work[] = {
1471 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1472 };
1473
1474 static void fe_pending_work(struct work_struct *work)
1475 {
1476 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1477 int i;
1478 bool pending;
1479
1480 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1481 pending = test_and_clear_bit(fe_work[i].bitnr,
1482 priv->pending_flags);
1483 if (pending)
1484 fe_work[i].action(priv);
1485 }
1486 }
1487
1488 static int fe_probe(struct platform_device *pdev)
1489 {
1490 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1491 const struct of_device_id *match;
1492 struct fe_soc_data *soc;
1493 struct net_device *netdev;
1494 struct fe_priv *priv;
1495 struct clk *sysclk;
1496 int err, napi_weight;
1497
1498 device_reset(&pdev->dev);
1499
1500 match = of_match_device(of_fe_match, &pdev->dev);
1501 soc = (struct fe_soc_data *)match->data;
1502
1503 if (soc->reg_table)
1504 fe_reg_table = soc->reg_table;
1505 else
1506 soc->reg_table = fe_reg_table;
1507
1508 fe_base = devm_ioremap_resource(&pdev->dev, res);
1509 if (IS_ERR(fe_base)) {
1510 err = -EADDRNOTAVAIL;
1511 goto err_out;
1512 }
1513
1514 netdev = alloc_etherdev(sizeof(*priv));
1515 if (!netdev) {
1516 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1517 err = -ENOMEM;
1518 goto err_iounmap;
1519 }
1520
1521 SET_NETDEV_DEV(netdev, &pdev->dev);
1522 netdev->netdev_ops = &fe_netdev_ops;
1523 netdev->base_addr = (unsigned long)fe_base;
1524
1525 netdev->irq = platform_get_irq(pdev, 0);
1526 if (netdev->irq < 0) {
1527 dev_err(&pdev->dev, "no IRQ resource found\n");
1528 err = -ENXIO;
1529 goto err_free_dev;
1530 }
1531
1532 if (soc->init_data)
1533 soc->init_data(soc, netdev);
1534 netdev->vlan_features = netdev->hw_features & ~NETIF_F_HW_VLAN_CTAG_TX;
1535 netdev->features |= netdev->hw_features;
1536
1537 if (IS_ENABLED(CONFIG_SOC_MT7621))
1538 netdev->max_mtu = 2048;
1539
1540 /* fake rx vlan filter func. to support tx vlan offload func */
1541 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1542 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1543
1544 priv = netdev_priv(netdev);
1545 spin_lock_init(&priv->page_lock);
1546 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1547 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1548 if (!priv->hw_stats) {
1549 err = -ENOMEM;
1550 goto err_free_dev;
1551 }
1552 spin_lock_init(&priv->hw_stats->stats_lock);
1553 }
1554
1555 sysclk = devm_clk_get(&pdev->dev, NULL);
1556 if (!IS_ERR(sysclk)) {
1557 priv->sysclk = clk_get_rate(sysclk);
1558 } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
1559 dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
1560 err = -ENXIO;
1561 goto err_free_dev;
1562 }
1563
1564 priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
1565 if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
1566 dev_err(&pdev->dev, "failed to read switch phandle\n");
1567 err = -ENODEV;
1568 goto err_free_dev;
1569 }
1570
1571 priv->netdev = netdev;
1572 priv->dev = &pdev->dev;
1573 priv->soc = soc;
1574 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1575 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1576 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1577 priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
1578 priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1579 INIT_WORK(&priv->pending_work, fe_pending_work);
1580 u64_stats_init(&priv->hw_stats->syncp);
1581
1582 napi_weight = 16;
1583 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1584 napi_weight *= 4;
1585 priv->tx_ring.tx_ring_size *= 4;
1586 priv->rx_ring.rx_ring_size *= 4;
1587 }
1588 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1589 fe_set_ethtool_ops(netdev);
1590
1591 err = register_netdev(netdev);
1592 if (err) {
1593 dev_err(&pdev->dev, "error bringing up device\n");
1594 goto err_free_dev;
1595 }
1596
1597 platform_set_drvdata(pdev, netdev);
1598
1599 netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
1600 netdev->base_addr, netdev->irq);
1601
1602 return 0;
1603
1604 err_free_dev:
1605 free_netdev(netdev);
1606 err_iounmap:
1607 devm_iounmap(&pdev->dev, fe_base);
1608 err_out:
1609 return err;
1610 }
1611
1612 static int fe_remove(struct platform_device *pdev)
1613 {
1614 struct net_device *dev = platform_get_drvdata(pdev);
1615 struct fe_priv *priv = netdev_priv(dev);
1616
1617 netif_napi_del(&priv->rx_napi);
1618 kfree(priv->hw_stats);
1619
1620 cancel_work_sync(&priv->pending_work);
1621
1622 unregister_netdev(dev);
1623 free_netdev(dev);
1624 platform_set_drvdata(pdev, NULL);
1625
1626 return 0;
1627 }
1628
1629 static struct platform_driver fe_driver = {
1630 .probe = fe_probe,
1631 .remove = fe_remove,
1632 .driver = {
1633 .name = "mtk_soc_eth",
1634 .owner = THIS_MODULE,
1635 .of_match_table = of_fe_match,
1636 },
1637 };
1638
1639 module_platform_driver(fe_driver);
1640
1641 MODULE_LICENSE("GPL");
1642 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1643 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1644 MODULE_VERSION(MTK_FE_DRV_VERSION);