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ramips: mt7621: fix mtu setting with kernel 4.14
[openwrt/openwrt.git] / target / linux / ramips / files-4.14 / drivers / net / ethernet / mtk / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
31 #include <linux/io.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "mtk_eth_soc.h"
39 #include "mdio.h"
40 #include "ethtool.h"
41
42 #define MAX_RX_LENGTH 1536
43 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
44 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
45 #define DMA_DUMMY_DESC 0xffffffff
46 #define FE_DEFAULT_MSG_ENABLE \
47 (NETIF_MSG_DRV | \
48 NETIF_MSG_PROBE | \
49 NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_IFDOWN | \
52 NETIF_MSG_IFUP | \
53 NETIF_MSG_RX_ERR | \
54 NETIF_MSG_TX_ERR)
55
56 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
57 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
58 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
59 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
60
61 #define SYSC_REG_RSTCTRL 0x34
62
63 static int fe_msg_level = -1;
64 module_param_named(msg_level, fe_msg_level, int, 0);
65 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
66
67 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
68 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
69 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
70 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
71 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
72 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
73 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
74 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
79 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
80 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
81 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
82 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
83 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
84 };
85
86 static const u16 *fe_reg_table = fe_reg_table_default;
87
88 struct fe_work_t {
89 int bitnr;
90 void (*action)(struct fe_priv *);
91 };
92
93 static void __iomem *fe_base;
94
95 void fe_w32(u32 val, unsigned reg)
96 {
97 __raw_writel(val, fe_base + reg);
98 }
99
100 u32 fe_r32(unsigned reg)
101 {
102 return __raw_readl(fe_base + reg);
103 }
104
105 void fe_reg_w32(u32 val, enum fe_reg reg)
106 {
107 fe_w32(val, fe_reg_table[reg]);
108 }
109
110 u32 fe_reg_r32(enum fe_reg reg)
111 {
112 return fe_r32(fe_reg_table[reg]);
113 }
114
115 void fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg)
116 {
117 u32 val;
118
119 spin_lock(&eth->page_lock);
120 val = __raw_readl(fe_base + reg);
121 val &= ~clear;
122 val |= set;
123 __raw_writel(val, fe_base + reg);
124 spin_unlock(&eth->page_lock);
125 }
126
127 void fe_reset(u32 reset_bits)
128 {
129 u32 t;
130
131 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
132 t |= reset_bits;
133 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
134 usleep_range(10, 20);
135
136 t &= ~reset_bits;
137 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
138 usleep_range(10, 20);
139 }
140
141 static inline void fe_int_disable(u32 mask)
142 {
143 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
144 FE_REG_FE_INT_ENABLE);
145 /* flush write */
146 fe_reg_r32(FE_REG_FE_INT_ENABLE);
147 }
148
149 static inline void fe_int_enable(u32 mask)
150 {
151 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
152 FE_REG_FE_INT_ENABLE);
153 /* flush write */
154 fe_reg_r32(FE_REG_FE_INT_ENABLE);
155 }
156
157 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
158 {
159 unsigned long flags;
160
161 spin_lock_irqsave(&priv->page_lock, flags);
162 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
163 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
164 FE_GDMA1_MAC_ADRL);
165 spin_unlock_irqrestore(&priv->page_lock, flags);
166 }
167
168 static int fe_set_mac_address(struct net_device *dev, void *p)
169 {
170 int ret = eth_mac_addr(dev, p);
171
172 if (!ret) {
173 struct fe_priv *priv = netdev_priv(dev);
174
175 if (priv->soc->set_mac)
176 priv->soc->set_mac(priv, dev->dev_addr);
177 else
178 fe_hw_set_macaddr(priv, p);
179 }
180
181 return ret;
182 }
183
184 static inline int fe_max_frag_size(int mtu)
185 {
186 /* make sure buf_size will be at least MAX_RX_LENGTH */
187 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
188 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
189
190 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
191 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
192 }
193
194 static inline int fe_max_buf_size(int frag_size)
195 {
196 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
197 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
198
199 BUG_ON(buf_size < MAX_RX_LENGTH);
200 return buf_size;
201 }
202
203 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
204 {
205 rxd->rxd1 = dma_rxd->rxd1;
206 rxd->rxd2 = dma_rxd->rxd2;
207 rxd->rxd3 = dma_rxd->rxd3;
208 rxd->rxd4 = dma_rxd->rxd4;
209 }
210
211 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
212 {
213 dma_txd->txd1 = txd->txd1;
214 dma_txd->txd3 = txd->txd3;
215 dma_txd->txd4 = txd->txd4;
216 /* clean dma done flag last */
217 dma_txd->txd2 = txd->txd2;
218 }
219
220 static void fe_clean_rx(struct fe_priv *priv)
221 {
222 struct fe_rx_ring *ring = &priv->rx_ring;
223 struct page *page;
224 int i;
225
226 if (ring->rx_data) {
227 for (i = 0; i < ring->rx_ring_size; i++)
228 if (ring->rx_data[i]) {
229 if (ring->rx_dma && ring->rx_dma[i].rxd1)
230 dma_unmap_single(&priv->netdev->dev,
231 ring->rx_dma[i].rxd1,
232 ring->rx_buf_size,
233 DMA_FROM_DEVICE);
234 skb_free_frag(ring->rx_data[i]);
235 }
236
237 kfree(ring->rx_data);
238 ring->rx_data = NULL;
239 }
240
241 if (ring->rx_dma) {
242 dma_free_coherent(&priv->netdev->dev,
243 ring->rx_ring_size * sizeof(*ring->rx_dma),
244 ring->rx_dma,
245 ring->rx_phys);
246 ring->rx_dma = NULL;
247 }
248
249 if (!ring->frag_cache.va)
250 return;
251
252 page = virt_to_page(ring->frag_cache.va);
253 __page_frag_cache_drain(page, ring->frag_cache.pagecnt_bias);
254 memset(&ring->frag_cache, 0, sizeof(ring->frag_cache));
255 }
256
257 static int fe_alloc_rx(struct fe_priv *priv)
258 {
259 struct net_device *netdev = priv->netdev;
260 struct fe_rx_ring *ring = &priv->rx_ring;
261 int i, pad;
262
263 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
264 GFP_KERNEL);
265 if (!ring->rx_data)
266 goto no_rx_mem;
267
268 for (i = 0; i < ring->rx_ring_size; i++) {
269 ring->rx_data[i] = page_frag_alloc(&ring->frag_cache,
270 ring->frag_size,
271 GFP_KERNEL);
272 if (!ring->rx_data[i])
273 goto no_rx_mem;
274 }
275
276 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
277 ring->rx_ring_size * sizeof(*ring->rx_dma),
278 &ring->rx_phys,
279 GFP_ATOMIC | __GFP_ZERO);
280 if (!ring->rx_dma)
281 goto no_rx_mem;
282
283 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
284 pad = 0;
285 else
286 pad = NET_IP_ALIGN;
287 for (i = 0; i < ring->rx_ring_size; i++) {
288 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
289 ring->rx_data[i] + NET_SKB_PAD + pad,
290 ring->rx_buf_size,
291 DMA_FROM_DEVICE);
292 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
293 goto no_rx_mem;
294 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
295
296 if (priv->flags & FE_FLAG_RX_SG_DMA)
297 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
298 else
299 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
300 }
301 ring->rx_calc_idx = ring->rx_ring_size - 1;
302 /* make sure that all changes to the dma ring are flushed before we
303 * continue
304 */
305 wmb();
306
307 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
308 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
309 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
310 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
311
312 return 0;
313
314 no_rx_mem:
315 return -ENOMEM;
316 }
317
318 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
319 {
320 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
321 dma_unmap_single(dev,
322 dma_unmap_addr(tx_buf, dma_addr0),
323 dma_unmap_len(tx_buf, dma_len0),
324 DMA_TO_DEVICE);
325 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
326 dma_unmap_page(dev,
327 dma_unmap_addr(tx_buf, dma_addr0),
328 dma_unmap_len(tx_buf, dma_len0),
329 DMA_TO_DEVICE);
330 }
331 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
332 dma_unmap_page(dev,
333 dma_unmap_addr(tx_buf, dma_addr1),
334 dma_unmap_len(tx_buf, dma_len1),
335 DMA_TO_DEVICE);
336
337 tx_buf->flags = 0;
338 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
339 dev_kfree_skb_any(tx_buf->skb);
340 tx_buf->skb = NULL;
341 }
342
343 static void fe_clean_tx(struct fe_priv *priv)
344 {
345 int i;
346 struct device *dev = &priv->netdev->dev;
347 struct fe_tx_ring *ring = &priv->tx_ring;
348
349 if (ring->tx_buf) {
350 for (i = 0; i < ring->tx_ring_size; i++)
351 fe_txd_unmap(dev, &ring->tx_buf[i]);
352 kfree(ring->tx_buf);
353 ring->tx_buf = NULL;
354 }
355
356 if (ring->tx_dma) {
357 dma_free_coherent(dev,
358 ring->tx_ring_size * sizeof(*ring->tx_dma),
359 ring->tx_dma,
360 ring->tx_phys);
361 ring->tx_dma = NULL;
362 }
363
364 netdev_reset_queue(priv->netdev);
365 }
366
367 static int fe_alloc_tx(struct fe_priv *priv)
368 {
369 int i;
370 struct fe_tx_ring *ring = &priv->tx_ring;
371
372 ring->tx_free_idx = 0;
373 ring->tx_next_idx = 0;
374 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
375 MAX_SKB_FRAGS);
376
377 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
378 GFP_KERNEL);
379 if (!ring->tx_buf)
380 goto no_tx_mem;
381
382 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
383 ring->tx_ring_size * sizeof(*ring->tx_dma),
384 &ring->tx_phys,
385 GFP_ATOMIC | __GFP_ZERO);
386 if (!ring->tx_dma)
387 goto no_tx_mem;
388
389 for (i = 0; i < ring->tx_ring_size; i++) {
390 if (priv->soc->tx_dma)
391 priv->soc->tx_dma(&ring->tx_dma[i]);
392 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
393 }
394 /* make sure that all changes to the dma ring are flushed before we
395 * continue
396 */
397 wmb();
398
399 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
400 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
401 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
402 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
403
404 return 0;
405
406 no_tx_mem:
407 return -ENOMEM;
408 }
409
410 static int fe_init_dma(struct fe_priv *priv)
411 {
412 int err;
413
414 err = fe_alloc_tx(priv);
415 if (err)
416 return err;
417
418 err = fe_alloc_rx(priv);
419 if (err)
420 return err;
421
422 return 0;
423 }
424
425 static void fe_free_dma(struct fe_priv *priv)
426 {
427 fe_clean_tx(priv);
428 fe_clean_rx(priv);
429 }
430
431 void fe_stats_update(struct fe_priv *priv)
432 {
433 struct fe_hw_stats *hwstats = priv->hw_stats;
434 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
435 u64 stats;
436
437 u64_stats_update_begin(&hwstats->syncp);
438
439 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
440 hwstats->rx_bytes += fe_r32(base);
441 stats = fe_r32(base + 0x04);
442 if (stats)
443 hwstats->rx_bytes += (stats << 32);
444 hwstats->rx_packets += fe_r32(base + 0x08);
445 hwstats->rx_overflow += fe_r32(base + 0x10);
446 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
447 hwstats->rx_short_errors += fe_r32(base + 0x18);
448 hwstats->rx_long_errors += fe_r32(base + 0x1c);
449 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
450 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
451 hwstats->tx_skip += fe_r32(base + 0x28);
452 hwstats->tx_collisions += fe_r32(base + 0x2c);
453 hwstats->tx_bytes += fe_r32(base + 0x30);
454 stats = fe_r32(base + 0x34);
455 if (stats)
456 hwstats->tx_bytes += (stats << 32);
457 hwstats->tx_packets += fe_r32(base + 0x38);
458 } else {
459 hwstats->tx_bytes += fe_r32(base);
460 hwstats->tx_packets += fe_r32(base + 0x04);
461 hwstats->tx_skip += fe_r32(base + 0x08);
462 hwstats->tx_collisions += fe_r32(base + 0x0c);
463 hwstats->rx_bytes += fe_r32(base + 0x20);
464 hwstats->rx_packets += fe_r32(base + 0x24);
465 hwstats->rx_overflow += fe_r32(base + 0x28);
466 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
467 hwstats->rx_short_errors += fe_r32(base + 0x30);
468 hwstats->rx_long_errors += fe_r32(base + 0x34);
469 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
470 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
471 }
472
473 u64_stats_update_end(&hwstats->syncp);
474 }
475
476 static void fe_get_stats64(struct net_device *dev,
477 struct rtnl_link_stats64 *storage)
478 {
479 struct fe_priv *priv = netdev_priv(dev);
480 struct fe_hw_stats *hwstats = priv->hw_stats;
481 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
482 unsigned int start;
483
484 if (!base) {
485 netdev_stats_to_stats64(storage, &dev->stats);
486 return;
487 }
488
489 if (netif_running(dev) && netif_device_present(dev)) {
490 if (spin_trylock_bh(&hwstats->stats_lock)) {
491 fe_stats_update(priv);
492 spin_unlock_bh(&hwstats->stats_lock);
493 }
494 }
495
496 do {
497 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
498 storage->rx_packets = hwstats->rx_packets;
499 storage->tx_packets = hwstats->tx_packets;
500 storage->rx_bytes = hwstats->rx_bytes;
501 storage->tx_bytes = hwstats->tx_bytes;
502 storage->collisions = hwstats->tx_collisions;
503 storage->rx_length_errors = hwstats->rx_short_errors +
504 hwstats->rx_long_errors;
505 storage->rx_over_errors = hwstats->rx_overflow;
506 storage->rx_crc_errors = hwstats->rx_fcs_errors;
507 storage->rx_errors = hwstats->rx_checksum_errors;
508 storage->tx_aborted_errors = hwstats->tx_skip;
509 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
510
511 storage->tx_errors = priv->netdev->stats.tx_errors;
512 storage->rx_dropped = priv->netdev->stats.rx_dropped;
513 storage->tx_dropped = priv->netdev->stats.tx_dropped;
514 }
515
516 static int fe_vlan_rx_add_vid(struct net_device *dev,
517 __be16 proto, u16 vid)
518 {
519 struct fe_priv *priv = netdev_priv(dev);
520 u32 idx = (vid & 0xf);
521 u32 vlan_cfg;
522
523 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
524 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
525 return 0;
526
527 if (test_bit(idx, &priv->vlan_map)) {
528 netdev_warn(dev, "disable tx vlan offload\n");
529 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
530 netdev_update_features(dev);
531 } else {
532 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
533 ((idx >> 1) << 2));
534 if (idx & 0x1) {
535 vlan_cfg &= 0xffff;
536 vlan_cfg |= (vid << 16);
537 } else {
538 vlan_cfg &= 0xffff0000;
539 vlan_cfg |= vid;
540 }
541 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
542 ((idx >> 1) << 2));
543 set_bit(idx, &priv->vlan_map);
544 }
545
546 return 0;
547 }
548
549 static int fe_vlan_rx_kill_vid(struct net_device *dev,
550 __be16 proto, u16 vid)
551 {
552 struct fe_priv *priv = netdev_priv(dev);
553 u32 idx = (vid & 0xf);
554
555 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
556 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
557 return 0;
558
559 clear_bit(idx, &priv->vlan_map);
560
561 return 0;
562 }
563
564 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
565 {
566 barrier();
567 return (u32)(ring->tx_ring_size -
568 ((ring->tx_next_idx - ring->tx_free_idx) &
569 (ring->tx_ring_size - 1)));
570 }
571
572 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
573 int tx_num, struct fe_tx_ring *ring)
574 {
575 struct fe_priv *priv = netdev_priv(dev);
576 struct skb_frag_struct *frag;
577 struct fe_tx_dma txd, *ptxd;
578 struct fe_tx_buf *tx_buf;
579 dma_addr_t mapped_addr;
580 unsigned int nr_frags;
581 u32 def_txd4;
582 int i, j, k, frag_size, frag_map_size, offset;
583
584 tx_buf = &ring->tx_buf[ring->tx_next_idx];
585 memset(tx_buf, 0, sizeof(*tx_buf));
586 memset(&txd, 0, sizeof(txd));
587 nr_frags = skb_shinfo(skb)->nr_frags;
588
589 /* init tx descriptor */
590 if (priv->soc->tx_dma)
591 priv->soc->tx_dma(&txd);
592 else
593 txd.txd4 = TX_DMA_DESP4_DEF;
594 def_txd4 = txd.txd4;
595
596 /* TX Checksum offload */
597 if (skb->ip_summed == CHECKSUM_PARTIAL)
598 txd.txd4 |= TX_DMA_CHKSUM;
599
600 /* VLAN header offload */
601 if (skb_vlan_tag_present(skb)) {
602 u16 tag = skb_vlan_tag_get(skb);
603
604 if (IS_ENABLED(CONFIG_SOC_MT7621))
605 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
606 else
607 txd.txd4 |= TX_DMA_INS_VLAN |
608 ((tag >> VLAN_PRIO_SHIFT) << 4) |
609 (tag & 0xF);
610 }
611
612 /* TSO: fill MSS info in tcp checksum field */
613 if (skb_is_gso(skb)) {
614 if (skb_cow_head(skb, 0)) {
615 netif_warn(priv, tx_err, dev,
616 "GSO expand head fail.\n");
617 goto err_out;
618 }
619 if (skb_shinfo(skb)->gso_type &
620 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
621 txd.txd4 |= TX_DMA_TSO;
622 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
623 }
624 }
625
626 mapped_addr = dma_map_single(&dev->dev, skb->data,
627 skb_headlen(skb), DMA_TO_DEVICE);
628 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
629 goto err_out;
630 txd.txd1 = mapped_addr;
631 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
632
633 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
634 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
635 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
636
637 /* TX SG offload */
638 j = ring->tx_next_idx;
639 k = 0;
640 for (i = 0; i < nr_frags; i++) {
641 offset = 0;
642 frag = &skb_shinfo(skb)->frags[i];
643 frag_size = skb_frag_size(frag);
644
645 while (frag_size > 0) {
646 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
647 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
648 frag_map_size,
649 DMA_TO_DEVICE);
650 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
651 goto err_dma;
652
653 if (k & 0x1) {
654 j = NEXT_TX_DESP_IDX(j);
655 txd.txd1 = mapped_addr;
656 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
657 txd.txd4 = def_txd4;
658
659 tx_buf = &ring->tx_buf[j];
660 memset(tx_buf, 0, sizeof(*tx_buf));
661
662 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
663 dma_unmap_addr_set(tx_buf, dma_addr0,
664 mapped_addr);
665 dma_unmap_len_set(tx_buf, dma_len0,
666 frag_map_size);
667 } else {
668 txd.txd3 = mapped_addr;
669 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
670
671 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
672 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
673 dma_unmap_addr_set(tx_buf, dma_addr1,
674 mapped_addr);
675 dma_unmap_len_set(tx_buf, dma_len1,
676 frag_map_size);
677
678 if (!((i == (nr_frags - 1)) &&
679 (frag_map_size == frag_size))) {
680 fe_set_txd(&txd, &ring->tx_dma[j]);
681 memset(&txd, 0, sizeof(txd));
682 }
683 }
684 frag_size -= frag_map_size;
685 offset += frag_map_size;
686 k++;
687 }
688 }
689
690 /* set last segment */
691 if (k & 0x1)
692 txd.txd2 |= TX_DMA_LS1;
693 else
694 txd.txd2 |= TX_DMA_LS0;
695 fe_set_txd(&txd, &ring->tx_dma[j]);
696
697 /* store skb to cleanup */
698 tx_buf->skb = skb;
699
700 netdev_sent_queue(dev, skb->len);
701 skb_tx_timestamp(skb);
702
703 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
704 /* make sure that all changes to the dma ring are flushed before we
705 * continue
706 */
707 wmb();
708 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
709 netif_stop_queue(dev);
710 smp_mb();
711 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
712 netif_wake_queue(dev);
713 }
714
715 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
716 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
717
718 return 0;
719
720 err_dma:
721 j = ring->tx_next_idx;
722 for (i = 0; i < tx_num; i++) {
723 ptxd = &ring->tx_dma[j];
724 tx_buf = &ring->tx_buf[j];
725
726 /* unmap dma */
727 fe_txd_unmap(&dev->dev, tx_buf);
728
729 ptxd->txd2 = TX_DMA_DESP2_DEF;
730 j = NEXT_TX_DESP_IDX(j);
731 }
732 /* make sure that all changes to the dma ring are flushed before we
733 * continue
734 */
735 wmb();
736
737 err_out:
738 return -1;
739 }
740
741 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
742 {
743 unsigned int len;
744 int ret;
745
746 ret = 0;
747 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
748 if ((priv->flags & FE_FLAG_PADDING_64B) &&
749 !(priv->flags & FE_FLAG_PADDING_BUG))
750 return ret;
751
752 if (skb_vlan_tag_present(skb))
753 len = ETH_ZLEN;
754 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
755 len = VLAN_ETH_ZLEN;
756 else if (!(priv->flags & FE_FLAG_PADDING_64B))
757 len = ETH_ZLEN;
758 else
759 return ret;
760
761 if (skb->len < len) {
762 ret = skb_pad(skb, len - skb->len);
763 if (ret < 0)
764 return ret;
765 skb->len = len;
766 skb_set_tail_pointer(skb, len);
767 }
768 }
769
770 return ret;
771 }
772
773 static inline int fe_cal_txd_req(struct sk_buff *skb)
774 {
775 int i, nfrags;
776 struct skb_frag_struct *frag;
777
778 nfrags = 1;
779 if (skb_is_gso(skb)) {
780 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
781 frag = &skb_shinfo(skb)->frags[i];
782 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
783 }
784 } else {
785 nfrags += skb_shinfo(skb)->nr_frags;
786 }
787
788 return DIV_ROUND_UP(nfrags, 2);
789 }
790
791 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
792 {
793 struct fe_priv *priv = netdev_priv(dev);
794 struct fe_tx_ring *ring = &priv->tx_ring;
795 struct net_device_stats *stats = &dev->stats;
796 int tx_num;
797 int len = skb->len;
798
799 if (fe_skb_padto(skb, priv)) {
800 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
801 return NETDEV_TX_OK;
802 }
803
804 tx_num = fe_cal_txd_req(skb);
805 if (unlikely(fe_empty_txd(ring) <= tx_num)) {
806 netif_stop_queue(dev);
807 netif_err(priv, tx_queued, dev,
808 "Tx Ring full when queue awake!\n");
809 return NETDEV_TX_BUSY;
810 }
811
812 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
813 stats->tx_dropped++;
814 } else {
815 stats->tx_packets++;
816 stats->tx_bytes += len;
817 }
818
819 return NETDEV_TX_OK;
820 }
821
822 static int fe_poll_rx(struct napi_struct *napi, int budget,
823 struct fe_priv *priv, u32 rx_intr)
824 {
825 struct net_device *netdev = priv->netdev;
826 struct net_device_stats *stats = &netdev->stats;
827 struct fe_soc_data *soc = priv->soc;
828 struct fe_rx_ring *ring = &priv->rx_ring;
829 int idx = ring->rx_calc_idx;
830 u32 checksum_bit;
831 struct sk_buff *skb;
832 u8 *data, *new_data;
833 struct fe_rx_dma *rxd, trxd;
834 int done = 0, pad;
835
836 if (netdev->features & NETIF_F_RXCSUM)
837 checksum_bit = soc->checksum_bit;
838 else
839 checksum_bit = 0;
840
841 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
842 pad = 0;
843 else
844 pad = NET_IP_ALIGN;
845
846 while (done < budget) {
847 unsigned int pktlen;
848 dma_addr_t dma_addr;
849
850 idx = NEXT_RX_DESP_IDX(idx);
851 rxd = &ring->rx_dma[idx];
852 data = ring->rx_data[idx];
853
854 fe_get_rxd(&trxd, rxd);
855 if (!(trxd.rxd2 & RX_DMA_DONE))
856 break;
857
858 /* alloc new buffer */
859 new_data = page_frag_alloc(&ring->frag_cache, ring->frag_size,
860 GFP_ATOMIC);
861 if (unlikely(!new_data)) {
862 stats->rx_dropped++;
863 goto release_desc;
864 }
865 dma_addr = dma_map_single(&netdev->dev,
866 new_data + NET_SKB_PAD + pad,
867 ring->rx_buf_size,
868 DMA_FROM_DEVICE);
869 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
870 skb_free_frag(new_data);
871 goto release_desc;
872 }
873
874 /* receive data */
875 skb = build_skb(data, ring->frag_size);
876 if (unlikely(!skb)) {
877 skb_free_frag(new_data);
878 goto release_desc;
879 }
880 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
881
882 dma_unmap_single(&netdev->dev, trxd.rxd1,
883 ring->rx_buf_size, DMA_FROM_DEVICE);
884 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
885 skb->dev = netdev;
886 skb_put(skb, pktlen);
887 if (trxd.rxd4 & checksum_bit)
888 skb->ip_summed = CHECKSUM_UNNECESSARY;
889 else
890 skb_checksum_none_assert(skb);
891 skb->protocol = eth_type_trans(skb, netdev);
892
893 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
894 if (mtk_offload_check_rx(priv, skb, trxd.rxd4) == 0) {
895 #endif
896 stats->rx_packets++;
897 stats->rx_bytes += pktlen;
898
899 napi_gro_receive(napi, skb);
900 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
901 } else {
902 dev_kfree_skb(skb);
903 }
904 #endif
905 ring->rx_data[idx] = new_data;
906 rxd->rxd1 = (unsigned int)dma_addr;
907
908 release_desc:
909 if (priv->flags & FE_FLAG_RX_SG_DMA)
910 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
911 else
912 rxd->rxd2 = RX_DMA_LSO;
913
914 ring->rx_calc_idx = idx;
915 /* make sure that all changes to the dma ring are flushed before
916 * we continue
917 */
918 wmb();
919 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
920 done++;
921 }
922
923 if (done < budget)
924 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
925
926 return done;
927 }
928
929 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
930 int *tx_again)
931 {
932 struct net_device *netdev = priv->netdev;
933 struct device *dev = &netdev->dev;
934 unsigned int bytes_compl = 0;
935 struct sk_buff *skb;
936 struct fe_tx_buf *tx_buf;
937 int done = 0;
938 u32 idx, hwidx;
939 struct fe_tx_ring *ring = &priv->tx_ring;
940
941 idx = ring->tx_free_idx;
942 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
943
944 while ((idx != hwidx) && budget) {
945 tx_buf = &ring->tx_buf[idx];
946 skb = tx_buf->skb;
947
948 if (!skb)
949 break;
950
951 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
952 bytes_compl += skb->len;
953 done++;
954 budget--;
955 }
956 fe_txd_unmap(dev, tx_buf);
957 idx = NEXT_TX_DESP_IDX(idx);
958 }
959 ring->tx_free_idx = idx;
960
961 if (idx == hwidx) {
962 /* read hw index again make sure no new tx packet */
963 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
964 if (idx == hwidx)
965 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
966 else
967 *tx_again = 1;
968 } else {
969 *tx_again = 1;
970 }
971
972 if (done) {
973 netdev_completed_queue(netdev, done, bytes_compl);
974 smp_mb();
975 if (unlikely(netif_queue_stopped(netdev) &&
976 (fe_empty_txd(ring) > ring->tx_thresh)))
977 netif_wake_queue(netdev);
978 }
979
980 return done;
981 }
982
983 static int fe_poll(struct napi_struct *napi, int budget)
984 {
985 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
986 struct fe_hw_stats *hwstat = priv->hw_stats;
987 int tx_done, rx_done, tx_again;
988 u32 status, fe_status, status_reg, mask;
989 u32 tx_intr, rx_intr, status_intr;
990
991 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
992 fe_status = status;
993 tx_intr = priv->soc->tx_int;
994 rx_intr = priv->soc->rx_int;
995 status_intr = priv->soc->status_int;
996 tx_done = 0;
997 rx_done = 0;
998 tx_again = 0;
999
1000 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
1001 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
1002 status_reg = FE_REG_FE_INT_STATUS2;
1003 } else {
1004 status_reg = FE_REG_FE_INT_STATUS;
1005 }
1006
1007 if (status & tx_intr)
1008 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
1009
1010 if (status & rx_intr)
1011 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
1012
1013 if (unlikely(fe_status & status_intr)) {
1014 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
1015 fe_stats_update(priv);
1016 spin_unlock(&hwstat->stats_lock);
1017 }
1018 fe_reg_w32(status_intr, status_reg);
1019 }
1020
1021 if (unlikely(netif_msg_intr(priv))) {
1022 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
1023 netdev_info(priv->netdev,
1024 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1025 tx_done, rx_done, status, mask);
1026 }
1027
1028 if (!tx_again && (rx_done < budget)) {
1029 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1030 if (status & (tx_intr | rx_intr)) {
1031 /* let napi poll again */
1032 rx_done = budget;
1033 goto poll_again;
1034 }
1035
1036 napi_complete_done(napi, rx_done);
1037 fe_int_enable(tx_intr | rx_intr);
1038 } else {
1039 rx_done = budget;
1040 }
1041
1042 poll_again:
1043 return rx_done;
1044 }
1045
1046 static void fe_tx_timeout(struct net_device *dev)
1047 {
1048 struct fe_priv *priv = netdev_priv(dev);
1049 struct fe_tx_ring *ring = &priv->tx_ring;
1050
1051 priv->netdev->stats.tx_errors++;
1052 netif_err(priv, tx_err, dev,
1053 "transmit timed out\n");
1054 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1055 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1056 netif_info(priv, drv, dev, "tx_ring=%d, "
1057 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1058 0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1059 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1060 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1061 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1062 ring->tx_free_idx,
1063 ring->tx_next_idx);
1064 netif_info(priv, drv, dev,
1065 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1066 0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1067 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1068 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1069 fe_reg_r32(FE_REG_RX_DRX_IDX0));
1070
1071 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1072 schedule_work(&priv->pending_work);
1073 }
1074
1075 static irqreturn_t fe_handle_irq(int irq, void *dev)
1076 {
1077 struct fe_priv *priv = netdev_priv(dev);
1078 u32 status, int_mask;
1079
1080 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1081
1082 if (unlikely(!status))
1083 return IRQ_NONE;
1084
1085 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1086 if (likely(status & int_mask)) {
1087 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1088 fe_int_disable(int_mask);
1089 __napi_schedule(&priv->rx_napi);
1090 }
1091 } else {
1092 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1093 }
1094
1095 return IRQ_HANDLED;
1096 }
1097
1098 #ifdef CONFIG_NET_POLL_CONTROLLER
1099 static void fe_poll_controller(struct net_device *dev)
1100 {
1101 struct fe_priv *priv = netdev_priv(dev);
1102 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1103
1104 fe_int_disable(int_mask);
1105 fe_handle_irq(dev->irq, dev);
1106 fe_int_enable(int_mask);
1107 }
1108 #endif
1109
1110 int fe_set_clock_cycle(struct fe_priv *priv)
1111 {
1112 unsigned long sysclk = priv->sysclk;
1113
1114 sysclk /= FE_US_CYC_CNT_DIVISOR;
1115 sysclk <<= FE_US_CYC_CNT_SHIFT;
1116
1117 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1118 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1119 sysclk,
1120 FE_FE_GLO_CFG);
1121 return 0;
1122 }
1123
1124 void fe_fwd_config(struct fe_priv *priv)
1125 {
1126 u32 fwd_cfg;
1127
1128 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1129
1130 /* disable jumbo frame */
1131 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1132 fwd_cfg &= ~FE_GDM1_JMB_EN;
1133
1134 /* set unicast/multicast/broadcast frame to cpu */
1135 fwd_cfg &= ~0xffff;
1136
1137 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1138 }
1139
1140 static void fe_rxcsum_config(bool enable)
1141 {
1142 if (enable)
1143 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1144 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1145 FE_GDMA1_FWD_CFG);
1146 else
1147 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1148 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1149 FE_GDMA1_FWD_CFG);
1150 }
1151
1152 static void fe_txcsum_config(bool enable)
1153 {
1154 if (enable)
1155 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1156 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1157 FE_CDMA_CSG_CFG);
1158 else
1159 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1160 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1161 FE_CDMA_CSG_CFG);
1162 }
1163
1164 void fe_csum_config(struct fe_priv *priv)
1165 {
1166 struct net_device *dev = priv_netdev(priv);
1167
1168 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1169 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1170 }
1171
1172 static int fe_hw_init(struct net_device *dev)
1173 {
1174 struct fe_priv *priv = netdev_priv(dev);
1175 int i, err;
1176
1177 err = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0,
1178 dev_name(priv->dev), dev);
1179 if (err)
1180 return err;
1181
1182 if (priv->soc->set_mac)
1183 priv->soc->set_mac(priv, dev->dev_addr);
1184 else
1185 fe_hw_set_macaddr(priv, dev->dev_addr);
1186
1187 /* disable delay interrupt */
1188 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1189
1190 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1191
1192 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1193 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1194 for (i = 0; i < 16; i += 2)
1195 fe_w32(((i + 1) << 16) + i,
1196 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1197 (i * 2));
1198
1199 if (priv->soc->fwd_config(priv))
1200 netdev_err(dev, "unable to get clock\n");
1201
1202 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1203 fe_reg_w32(1, FE_REG_FE_RST_GL);
1204 fe_reg_w32(0, FE_REG_FE_RST_GL);
1205 }
1206
1207 return 0;
1208 }
1209
1210 static int fe_open(struct net_device *dev)
1211 {
1212 struct fe_priv *priv = netdev_priv(dev);
1213 unsigned long flags;
1214 u32 val;
1215 int err;
1216
1217 err = fe_init_dma(priv);
1218 if (err) {
1219 fe_free_dma(priv);
1220 return err;
1221 }
1222
1223 spin_lock_irqsave(&priv->page_lock, flags);
1224
1225 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1226 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1227 val |= FE_RX_2B_OFFSET;
1228 val |= priv->soc->pdma_glo_cfg;
1229 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1230
1231 spin_unlock_irqrestore(&priv->page_lock, flags);
1232
1233 if (priv->phy)
1234 priv->phy->start(priv);
1235
1236 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1237 netif_carrier_on(dev);
1238
1239 napi_enable(&priv->rx_napi);
1240 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1241 netif_start_queue(dev);
1242 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1243 mtk_ppe_probe(priv);
1244 #endif
1245
1246 return 0;
1247 }
1248
1249 static int fe_stop(struct net_device *dev)
1250 {
1251 struct fe_priv *priv = netdev_priv(dev);
1252 unsigned long flags;
1253 int i;
1254
1255 netif_tx_disable(dev);
1256 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1257 napi_disable(&priv->rx_napi);
1258
1259 if (priv->phy)
1260 priv->phy->stop(priv);
1261
1262 spin_lock_irqsave(&priv->page_lock, flags);
1263
1264 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1265 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1266 FE_REG_PDMA_GLO_CFG);
1267 spin_unlock_irqrestore(&priv->page_lock, flags);
1268
1269 /* wait dma stop */
1270 for (i = 0; i < 10; i++) {
1271 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1272 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1273 msleep(20);
1274 continue;
1275 }
1276 break;
1277 }
1278
1279 fe_free_dma(priv);
1280
1281 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1282 mtk_ppe_remove(priv);
1283 #endif
1284
1285 return 0;
1286 }
1287
1288 static int __init fe_init(struct net_device *dev)
1289 {
1290 struct fe_priv *priv = netdev_priv(dev);
1291 struct device_node *port;
1292 const char *mac_addr;
1293 int err;
1294
1295 priv->soc->reset_fe();
1296
1297 if (priv->soc->switch_init)
1298 if (priv->soc->switch_init(priv)) {
1299 netdev_err(dev, "failed to initialize switch core\n");
1300 return -ENODEV;
1301 }
1302
1303 mac_addr = of_get_mac_address(priv->dev->of_node);
1304 if (mac_addr)
1305 ether_addr_copy(dev->dev_addr, mac_addr);
1306
1307 /* If the mac address is invalid, use random mac address */
1308 if (!is_valid_ether_addr(dev->dev_addr)) {
1309 random_ether_addr(dev->dev_addr);
1310 dev_err(priv->dev, "generated random MAC address %pM\n",
1311 dev->dev_addr);
1312 }
1313
1314 err = fe_mdio_init(priv);
1315 if (err)
1316 return err;
1317
1318 if (priv->soc->port_init)
1319 for_each_child_of_node(priv->dev->of_node, port)
1320 if (of_device_is_compatible(port, "mediatek,eth-port") &&
1321 of_device_is_available(port))
1322 priv->soc->port_init(priv, port);
1323
1324 if (priv->phy) {
1325 err = priv->phy->connect(priv);
1326 if (err)
1327 goto err_phy_disconnect;
1328 }
1329
1330 err = fe_hw_init(dev);
1331 if (err)
1332 goto err_phy_disconnect;
1333
1334 if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1335 priv->soc->switch_config(priv);
1336
1337 return 0;
1338
1339 err_phy_disconnect:
1340 if (priv->phy)
1341 priv->phy->disconnect(priv);
1342 fe_mdio_cleanup(priv);
1343
1344 return err;
1345 }
1346
1347 static void fe_uninit(struct net_device *dev)
1348 {
1349 struct fe_priv *priv = netdev_priv(dev);
1350
1351 if (priv->phy)
1352 priv->phy->disconnect(priv);
1353 fe_mdio_cleanup(priv);
1354
1355 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1356 free_irq(dev->irq, dev);
1357 }
1358
1359 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1360 {
1361 struct fe_priv *priv = netdev_priv(dev);
1362
1363 if (!priv->phy_dev)
1364 return -ENODEV;
1365
1366 switch (cmd) {
1367 case SIOCETHTOOL:
1368 return phy_ethtool_ioctl(priv->phy_dev,
1369 (void *) ifr->ifr_data);
1370 case SIOCGMIIPHY:
1371 case SIOCGMIIREG:
1372 case SIOCSMIIREG:
1373 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1374 default:
1375 break;
1376 }
1377
1378 return -EOPNOTSUPP;
1379 }
1380
1381 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1382 {
1383 struct fe_priv *priv = netdev_priv(dev);
1384 int frag_size, old_mtu;
1385 u32 fwd_cfg;
1386
1387 old_mtu = dev->mtu;
1388 dev->mtu = new_mtu;
1389
1390 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1391 return 0;
1392
1393 /* return early if the buffer sizes will not change */
1394 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1395 return 0;
1396 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1397 return 0;
1398
1399 if (new_mtu <= ETH_DATA_LEN)
1400 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1401 else
1402 priv->rx_ring.frag_size = PAGE_SIZE;
1403 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1404
1405 if (!netif_running(dev))
1406 return 0;
1407
1408 fe_stop(dev);
1409 if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
1410 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1411 if (new_mtu <= ETH_DATA_LEN) {
1412 fwd_cfg &= ~FE_GDM1_JMB_EN;
1413 } else {
1414 frag_size = fe_max_frag_size(new_mtu);
1415 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1416 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1417 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1418 }
1419 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1420 }
1421
1422 return fe_open(dev);
1423 }
1424
1425 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1426 static int
1427 fe_flow_offload(enum flow_offload_type type, struct flow_offload *flow,
1428 struct flow_offload_hw_path *src,
1429 struct flow_offload_hw_path *dest)
1430 {
1431 struct fe_priv *priv;
1432
1433 if (src->dev != dest->dev)
1434 return -EINVAL;
1435
1436 priv = netdev_priv(src->dev);
1437
1438 return mtk_flow_offload(priv, type, flow, src, dest);
1439 }
1440 #endif
1441
1442 static const struct net_device_ops fe_netdev_ops = {
1443 .ndo_init = fe_init,
1444 .ndo_uninit = fe_uninit,
1445 .ndo_open = fe_open,
1446 .ndo_stop = fe_stop,
1447 .ndo_start_xmit = fe_start_xmit,
1448 .ndo_set_mac_address = fe_set_mac_address,
1449 .ndo_validate_addr = eth_validate_addr,
1450 .ndo_do_ioctl = fe_do_ioctl,
1451 .ndo_change_mtu = fe_change_mtu,
1452 .ndo_tx_timeout = fe_tx_timeout,
1453 .ndo_get_stats64 = fe_get_stats64,
1454 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1455 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1456 #ifdef CONFIG_NET_POLL_CONTROLLER
1457 .ndo_poll_controller = fe_poll_controller,
1458 #endif
1459 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1460 .ndo_flow_offload = fe_flow_offload,
1461 #endif
1462 };
1463
1464 static void fe_reset_pending(struct fe_priv *priv)
1465 {
1466 struct net_device *dev = priv->netdev;
1467 int err;
1468
1469 rtnl_lock();
1470 fe_stop(dev);
1471
1472 err = fe_open(dev);
1473 if (err) {
1474 netif_alert(priv, ifup, dev,
1475 "Driver up/down cycle failed, closing device.\n");
1476 dev_close(dev);
1477 }
1478 rtnl_unlock();
1479 }
1480
1481 static const struct fe_work_t fe_work[] = {
1482 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1483 };
1484
1485 static void fe_pending_work(struct work_struct *work)
1486 {
1487 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1488 int i;
1489 bool pending;
1490
1491 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1492 pending = test_and_clear_bit(fe_work[i].bitnr,
1493 priv->pending_flags);
1494 if (pending)
1495 fe_work[i].action(priv);
1496 }
1497 }
1498
1499 static int fe_probe(struct platform_device *pdev)
1500 {
1501 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1502 const struct of_device_id *match;
1503 struct fe_soc_data *soc;
1504 struct net_device *netdev;
1505 struct fe_priv *priv;
1506 struct clk *sysclk;
1507 int err, napi_weight;
1508
1509 device_reset(&pdev->dev);
1510
1511 match = of_match_device(of_fe_match, &pdev->dev);
1512 soc = (struct fe_soc_data *)match->data;
1513
1514 if (soc->reg_table)
1515 fe_reg_table = soc->reg_table;
1516 else
1517 soc->reg_table = fe_reg_table;
1518
1519 fe_base = devm_ioremap_resource(&pdev->dev, res);
1520 if (IS_ERR(fe_base)) {
1521 err = -EADDRNOTAVAIL;
1522 goto err_out;
1523 }
1524
1525 netdev = alloc_etherdev(sizeof(*priv));
1526 if (!netdev) {
1527 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1528 err = -ENOMEM;
1529 goto err_iounmap;
1530 }
1531
1532 SET_NETDEV_DEV(netdev, &pdev->dev);
1533 netdev->netdev_ops = &fe_netdev_ops;
1534 netdev->base_addr = (unsigned long)fe_base;
1535
1536 netdev->irq = platform_get_irq(pdev, 0);
1537 if (netdev->irq < 0) {
1538 dev_err(&pdev->dev, "no IRQ resource found\n");
1539 err = -ENXIO;
1540 goto err_free_dev;
1541 }
1542
1543 if (soc->init_data)
1544 soc->init_data(soc, netdev);
1545 netdev->vlan_features = netdev->hw_features & ~NETIF_F_HW_VLAN_CTAG_TX;
1546 netdev->features |= netdev->hw_features;
1547
1548 if (IS_ENABLED(CONFIG_SOC_MT7621))
1549 netdev->max_mtu = 2048;
1550
1551 /* fake rx vlan filter func. to support tx vlan offload func */
1552 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1553 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1554
1555 priv = netdev_priv(netdev);
1556 spin_lock_init(&priv->page_lock);
1557 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1558 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1559 if (!priv->hw_stats) {
1560 err = -ENOMEM;
1561 goto err_free_dev;
1562 }
1563 spin_lock_init(&priv->hw_stats->stats_lock);
1564 }
1565
1566 sysclk = devm_clk_get(&pdev->dev, NULL);
1567 if (!IS_ERR(sysclk)) {
1568 priv->sysclk = clk_get_rate(sysclk);
1569 } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
1570 dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
1571 err = -ENXIO;
1572 goto err_free_dev;
1573 }
1574
1575 priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
1576 if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
1577 dev_err(&pdev->dev, "failed to read switch phandle\n");
1578 err = -ENODEV;
1579 goto err_free_dev;
1580 }
1581
1582 priv->netdev = netdev;
1583 priv->dev = &pdev->dev;
1584 priv->soc = soc;
1585 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1586 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1587 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1588 priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
1589 priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1590 INIT_WORK(&priv->pending_work, fe_pending_work);
1591 u64_stats_init(&priv->hw_stats->syncp);
1592
1593 napi_weight = 16;
1594 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1595 napi_weight *= 4;
1596 priv->tx_ring.tx_ring_size *= 4;
1597 priv->rx_ring.rx_ring_size *= 4;
1598 }
1599 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1600 fe_set_ethtool_ops(netdev);
1601
1602 err = register_netdev(netdev);
1603 if (err) {
1604 dev_err(&pdev->dev, "error bringing up device\n");
1605 goto err_free_dev;
1606 }
1607
1608 platform_set_drvdata(pdev, netdev);
1609
1610 netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
1611 netdev->base_addr, netdev->irq);
1612
1613 return 0;
1614
1615 err_free_dev:
1616 free_netdev(netdev);
1617 err_iounmap:
1618 devm_iounmap(&pdev->dev, fe_base);
1619 err_out:
1620 return err;
1621 }
1622
1623 static int fe_remove(struct platform_device *pdev)
1624 {
1625 struct net_device *dev = platform_get_drvdata(pdev);
1626 struct fe_priv *priv = netdev_priv(dev);
1627
1628 netif_napi_del(&priv->rx_napi);
1629 kfree(priv->hw_stats);
1630
1631 cancel_work_sync(&priv->pending_work);
1632
1633 unregister_netdev(dev);
1634 free_netdev(dev);
1635 platform_set_drvdata(pdev, NULL);
1636
1637 return 0;
1638 }
1639
1640 static struct platform_driver fe_driver = {
1641 .probe = fe_probe,
1642 .remove = fe_remove,
1643 .driver = {
1644 .name = "mtk_soc_eth",
1645 .owner = THIS_MODULE,
1646 .of_match_table = of_fe_match,
1647 },
1648 };
1649
1650 module_platform_driver(fe_driver);
1651
1652 MODULE_LICENSE("GPL");
1653 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1654 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1655 MODULE_VERSION(MTK_FE_DRV_VERSION);
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