target/linux/ramips/files-4.14/drivers/net/ethernet/mtk/mtk_offload.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2018 John Crispin <john@phrozen.org>
  11  */
  12
  13 #include "mtk_offload.h"
  14
  15 #define INVALID 0
  16 #define UNBIND  1
  17 #define BIND    2
  18 #define FIN     3
  19
  20 #define IPV4_HNAPT                      0
  21 #define IPV4_HNAT                       1
  22
  23 static u32
  24 mtk_flow_hash_v4(struct flow_offload_tuple *tuple)
  25 {
  26         u32 ports = ntohs(tuple->src_port)  << 16 | ntohs(tuple->dst_port);
  27         u32 src = ntohl(tuple->dst_v4.s_addr);
  28         u32 dst = ntohl(tuple->src_v4.s_addr);
  29         u32 hash = (ports & src) | ((~ports) & dst);
  30         u32 hash_23_0 = hash & 0xffffff;
  31         u32 hash_31_24 = hash & 0xff000000;
  32
  33         hash = ports ^ src ^ dst ^ ((hash_23_0 << 8) | (hash_31_24 >> 24));
  34         hash = ((hash & 0xffff0000) >> 16 ) ^ (hash & 0xfffff);
  35         hash &= 0x7ff;
  36         hash *= 2;;
  37
  38         return hash;
  39 }
  40
  41 static int
  42 mtk_foe_prepare_v4(struct mtk_foe_entry *entry,
  43                    struct flow_offload_tuple *tuple,
  44                    struct flow_offload_tuple *dest_tuple,
  45                    struct flow_offload_hw_path *src,
  46                    struct flow_offload_hw_path *dest)
  47 {
  48         int is_mcast = !!is_multicast_ether_addr(dest->eth_dest);
  49
  50         if (tuple->l4proto == IPPROTO_UDP)
  51                 entry->ipv4_hnapt.bfib1.udp = 1;
  52
  53         entry->ipv4_hnapt.etype = htons(ETH_P_IP);
  54         entry->ipv4_hnapt.bfib1.pkt_type = IPV4_HNAPT;
  55         entry->ipv4_hnapt.iblk2.fqos = 0;
  56         entry->ipv4_hnapt.bfib1.ttl = 1;
  57         entry->ipv4_hnapt.bfib1.cah = 1;
  58         entry->ipv4_hnapt.bfib1.ka = 1;
  59         entry->ipv4_hnapt.iblk2.mcast = is_mcast;
  60         entry->ipv4_hnapt.iblk2.dscp = 0;
  61         entry->ipv4_hnapt.iblk2.port_mg = 0x3f;
  62         entry->ipv4_hnapt.iblk2.port_ag = 0x1f;
  63 #ifdef CONFIG_NET_MEDIATEK_HW_QOS
  64         entry->ipv4_hnapt.iblk2.qid = 1;
  65         entry->ipv4_hnapt.iblk2.fqos = 1;
  66 #endif
  67 #ifdef CONFIG_RALINK
  68         entry->ipv4_hnapt.iblk2.dp = 1;
  69         if ((dest->flags & FLOW_OFFLOAD_PATH_VLAN) && (dest->vlan_id > 1))
  70                 entry->ipv4_hnapt.iblk2.qid += 8;
  71 #else
  72         entry->ipv4_hnapt.iblk2.dp = (dest->dev->name[3] - '0') + 1;
  73 #endif
  74
  75         entry->ipv4_hnapt.sip = ntohl(tuple->src_v4.s_addr);
  76         entry->ipv4_hnapt.dip = ntohl(tuple->dst_v4.s_addr);
  77         entry->ipv4_hnapt.sport = ntohs(tuple->src_port);
  78         entry->ipv4_hnapt.dport = ntohs(tuple->dst_port);
  79
  80         entry->ipv4_hnapt.new_sip = ntohl(dest_tuple->dst_v4.s_addr);
  81         entry->ipv4_hnapt.new_dip = ntohl(dest_tuple->src_v4.s_addr);
  82         entry->ipv4_hnapt.new_sport = ntohs(dest_tuple->dst_port);
  83         entry->ipv4_hnapt.new_dport = ntohs(dest_tuple->src_port);
  84
  85         entry->bfib1.state = BIND;
  86
  87         if (dest->flags & FLOW_OFFLOAD_PATH_PPPOE) {
  88                 entry->bfib1.psn = 1;
  89                 entry->ipv4_hnapt.etype = htons(ETH_P_PPP_SES);
  90                 entry->ipv4_hnapt.pppoe_id = dest->pppoe_sid;
  91         }
  92
  93         if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) {
  94                 entry->ipv4_hnapt.vlan1 = dest->vlan_id;
  95                 entry->bfib1.vlan_layer = 1;
  96
  97                 switch (dest->vlan_proto) {
  98                 case htons(ETH_P_8021Q):
  99                         entry->ipv4_hnapt.bfib1.vpm = 1;
 100                         break;
 101                 case htons(ETH_P_8021AD):
 102                         entry->ipv4_hnapt.bfib1.vpm = 2;
 103                         break;
 104                 default:
 105                         return -EINVAL;
 106                 }
 107         }
 108
 109         return 0;
 110 }
 111
 112 static void
 113 mtk_foe_set_mac(struct mtk_foe_entry *entry, u8 *smac, u8 *dmac)
 114 {
 115         entry->ipv4_hnapt.dmac_hi = swab32(*((u32*) dmac));
 116         entry->ipv4_hnapt.dmac_lo = swab16(*((u16*) &dmac[4]));
 117         entry->ipv4_hnapt.smac_hi = swab32(*((u32*) smac));
 118         entry->ipv4_hnapt.smac_lo = swab16(*((u16*) &smac[4]));
 119 }
 120
 121 static void
 122 mtk_foe_write(struct mtk_eth *eth, u32 hash,
 123               struct mtk_foe_entry *entry)
 124 {
 125         struct mtk_foe_entry *table = (struct mtk_foe_entry *)eth->foe_table;
 126
 127         memcpy(&table[hash], entry, sizeof(*entry));
 128 }
 129
 130 int mtk_flow_offload(struct mtk_eth *eth,
 131                      enum flow_offload_type type,
 132                      struct flow_offload *flow,
 133                      struct flow_offload_hw_path *src,
 134                      struct flow_offload_hw_path *dest)
 135 {
 136         struct flow_offload_tuple *otuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple;
 137         struct flow_offload_tuple *rtuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple;
 138         u32 time_stamp = mtk_r32(eth, 0x0010) & (0x7fff);
 139         u32 ohash, rhash;
 140         struct mtk_foe_entry orig = {
 141                 .bfib1.time_stamp = time_stamp,
 142                 .bfib1.psn = 0,
 143         };
 144         struct mtk_foe_entry reply = {
 145                 .bfib1.time_stamp = time_stamp,
 146                 .bfib1.psn = 0,
 147         };
 148
 149         if (otuple->l4proto != IPPROTO_TCP && otuple->l4proto != IPPROTO_UDP)
 150                 return -EINVAL;
 151
 152         switch (otuple->l3proto) {
 153         case AF_INET:
 154                 if (mtk_foe_prepare_v4(&orig, otuple, rtuple, src, dest) ||
 155                     mtk_foe_prepare_v4(&reply, rtuple, otuple, dest, src))
 156                         return -EINVAL;
 157
 158                 ohash = mtk_flow_hash_v4(otuple);
 159                 rhash = mtk_flow_hash_v4(rtuple);
 160                 break;
 161
 162         case AF_INET6:
 163                 return -EINVAL;
 164
 165         default:
 166                 return -EINVAL;
 167         }
 168
 169         if (type == FLOW_OFFLOAD_DEL) {
 170                 orig.bfib1.state = INVALID;
 171                 reply.bfib1.state = INVALID;
 172                 flow = NULL;
 173                 goto write;
 174         }
 175
 176         mtk_foe_set_mac(&orig, dest->eth_src, dest->eth_dest);
 177         mtk_foe_set_mac(&reply, src->eth_src, src->eth_dest);
 178
 179 write:
 180         mtk_foe_write(eth, ohash, &orig);
 181         mtk_foe_write(eth, rhash, &reply);
 182         rcu_assign_pointer(eth->foe_flow_table[ohash], flow);
 183         rcu_assign_pointer(eth->foe_flow_table[rhash], flow);
 184
 185         if (type == FLOW_OFFLOAD_DEL)
 186                 synchronize_rcu();
 187
 188         return 0;
 189 }
 190
 191 #ifdef CONFIG_NET_MEDIATEK_HW_QOS
 192
 193 #define QDMA_TX_SCH_TX    0x1a14
 194
 195 static void mtk_ppe_scheduler(struct mtk_eth *eth, int id, u32 rate)
 196 {
 197         int exp = 0, shift = 0;
 198         u32 reg = mtk_r32(eth, QDMA_TX_SCH_TX);
 199         u32 val = 0;
 200
 201         if (rate)
 202                 val = BIT(11);
 203
 204         while (rate > 127) {
 205                 rate /= 10;
 206                 exp++;
 207         }
 208
 209         val |= (rate & 0x7f) << 4;
 210         val |= exp & 0xf;
 211         if (id)
 212                 shift = 16;
 213         reg &= ~(0xffff << shift);
 214         reg |= val << shift;
 215         mtk_w32(eth, val, QDMA_TX_SCH_TX);
 216 }
 217
 218 #define QTX_CFG(x)      (0x1800 + (x * 0x10))
 219 #define QTX_SCH(x)      (0x1804 + (x * 0x10))
 220
 221 static void mtk_ppe_queue(struct mtk_eth *eth, int id, int sched, int weight, int resv, u32 min_rate, u32 max_rate)
 222 {
 223         int max_exp = 0, min_exp = 0;
 224         u32 reg;
 225
 226         if (id >= 16)
 227                 return;
 228
 229         reg = mtk_r32(eth, QTX_SCH(id));
 230         reg &= 0x70000000;
 231
 232         if (sched)
 233                 reg |= BIT(31);
 234
 235         if (min_rate)
 236                 reg |= BIT(27);
 237
 238         if (max_rate)
 239                 reg |= BIT(11);
 240
 241         while (max_rate > 127) {
 242                 max_rate /= 10;
 243                 max_exp++;
 244         }
 245
 246         while (min_rate > 127) {
 247                 min_rate /= 10;
 248                 min_exp++;
 249         }
 250
 251         reg |= (min_rate & 0x7f) << 20;
 252         reg |= (min_exp & 0xf) << 16;
 253         reg |= (weight & 0xf) << 12;
 254         reg |= (max_rate & 0x7f) << 4;
 255         reg |= max_exp & 0xf;
 256         mtk_w32(eth, reg, QTX_SCH(id));
 257
 258         resv &= 0xff;
 259         reg = mtk_r32(eth, QTX_CFG(id));
 260         reg &= 0xffff0000;
 261         reg |= (resv << 8) | resv;
 262         mtk_w32(eth, reg, QTX_CFG(id));
 263 }
 264 #endif
 265
 266 static int mtk_init_foe_table(struct mtk_eth *eth)
 267 {
 268         if (eth->foe_table)
 269                 return 0;
 270
 271         eth->foe_flow_table = devm_kcalloc(eth->dev, MTK_PPE_ENTRY_CNT,
 272                                            sizeof(*eth->foe_flow_table),
 273                                            GFP_KERNEL);
 274         if (!eth->foe_flow_table)
 275                 return -EINVAL;
 276
 277         /* map the FOE table */
 278         eth->foe_table = dmam_alloc_coherent(eth->dev, MTK_PPE_TBL_SZ,
 279                                              &eth->foe_table_phys, GFP_KERNEL);
 280         if (!eth->foe_table) {
 281                 dev_err(eth->dev, "failed to allocate foe table\n");
 282                 kfree(eth->foe_flow_table);
 283                 return -ENOMEM;
 284         }
 285
 286
 287         return 0;
 288 }
 289
 290 static int mtk_ppe_start(struct mtk_eth *eth)
 291 {
 292         int ret;
 293
 294         ret = mtk_init_foe_table(eth);
 295         if (ret)
 296                 return ret;
 297
 298         /* tell the PPE about the tables base address */
 299         mtk_w32(eth, eth->foe_table_phys, MTK_REG_PPE_TB_BASE);
 300
 301         /* flush the table */
 302         memset(eth->foe_table, 0, MTK_PPE_TBL_SZ);
 303
 304         /* setup hashing */
 305         mtk_m32(eth,
 306                 MTK_PPE_TB_CFG_HASH_MODE_MASK | MTK_PPE_TB_CFG_TBL_SZ_MASK,
 307                 MTK_PPE_TB_CFG_HASH_MODE1 | MTK_PPE_TB_CFG_TBL_SZ_4K,
 308                 MTK_REG_PPE_TB_CFG);
 309
 310         /* set the default hashing seed */
 311         mtk_w32(eth, MTK_PPE_HASH_SEED, MTK_REG_PPE_HASH_SEED);
 312
 313         /* each foe entry is 64bytes and is setup by cpu forwarding*/
 314         mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_TB_CFG_ENTRY_SZ_MASK |
 315                 MTK_PPE_TB_CFG_SMA_MASK,
 316                 MTK_PPE_TB_CFG_ENTRY_SZ_64B |  MTK_PPE_TB_CFG_SMA_FWD_CPU,
 317                 MTK_REG_PPE_TB_CFG);
 318
 319         /* set ip proto */
 320         mtk_w32(eth, 0xFFFFFFFF, MTK_REG_PPE_IP_PROT_CHK);
 321
 322         /* setup caching */
 323         mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
 324         mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE, MTK_PPE_CAH_CTRL_EN,
 325                 MTK_REG_PPE_CAH_CTRL);
 326
 327         /* enable FOE */
 328         mtk_m32(eth, 0, MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
 329                 MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
 330                 MTK_PPE_FLOW_CFG_IPV4_GREK_EN,
 331                 MTK_REG_PPE_FLOW_CFG);
 332
 333         /* setup flow entry un/bind aging */
 334         mtk_m32(eth, 0,
 335                 MTK_PPE_TB_CFG_UNBD_AGE | MTK_PPE_TB_CFG_NTU_AGE |
 336                 MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
 337                 MTK_PPE_TB_CFG_TCP_AGE,
 338                 MTK_REG_PPE_TB_CFG);
 339
 340         mtk_m32(eth, MTK_PPE_UNB_AGE_MNP_MASK | MTK_PPE_UNB_AGE_DLTA_MASK,
 341                 MTK_PPE_UNB_AGE_MNP | MTK_PPE_UNB_AGE_DLTA,
 342                 MTK_REG_PPE_UNB_AGE);
 343         mtk_m32(eth, MTK_PPE_BND_AGE0_NTU_DLTA_MASK |
 344                 MTK_PPE_BND_AGE0_UDP_DLTA_MASK,
 345                 MTK_PPE_BND_AGE0_NTU_DLTA | MTK_PPE_BND_AGE0_UDP_DLTA,
 346                 MTK_REG_PPE_BND_AGE0);
 347         mtk_m32(eth, MTK_PPE_BND_AGE1_FIN_DLTA_MASK |
 348                 MTK_PPE_BND_AGE1_TCP_DLTA_MASK,
 349                 MTK_PPE_BND_AGE1_FIN_DLTA | MTK_PPE_BND_AGE1_TCP_DLTA,
 350                 MTK_REG_PPE_BND_AGE1);
 351
 352         /* setup flow entry keep alive */
 353         mtk_m32(eth, MTK_PPE_TB_CFG_KA_MASK, MTK_PPE_TB_CFG_KA,
 354                 MTK_REG_PPE_TB_CFG);
 355         mtk_w32(eth, MTK_PPE_KA_UDP | MTK_PPE_KA_TCP | MTK_PPE_KA_T, MTK_REG_PPE_KA);
 356
 357         /* setup flow entry rate limit */
 358         mtk_w32(eth, (0x3fff << 16) | 0x3fff, MTK_REG_PPE_BIND_LMT_0);
 359         mtk_w32(eth, MTK_PPE_NTU_KA | 0x3fff, MTK_REG_PPE_BIND_LMT_1);
 360         mtk_m32(eth, MTK_PPE_BNDR_RATE_MASK, 1, MTK_REG_PPE_BNDR);
 361
 362         /* enable the PPE */
 363         mtk_m32(eth, 0, MTK_PPE_GLO_CFG_EN, MTK_REG_PPE_GLO_CFG);
 364
 365 #ifdef CONFIG_RALINK
 366         /* set the default forwarding port to QDMA */
 367         mtk_w32(eth, 0x0, MTK_REG_PPE_DFT_CPORT);
 368 #else
 369         /* set the default forwarding port to QDMA */
 370         mtk_w32(eth, 0x55555555, MTK_REG_PPE_DFT_CPORT);
 371 #endif
 372
 373         /* allow packets with TTL=0 */
 374         mtk_m32(eth, MTK_PPE_GLO_CFG_TTL0_DROP, 0, MTK_REG_PPE_GLO_CFG);
 375
 376         /* send all traffic from gmac to the ppe */
 377         mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(0));
 378         mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(1));
 379
 380         dev_info(eth->dev, "PPE started\n");
 381
 382 #ifdef CONFIG_NET_MEDIATEK_HW_QOS
 383         mtk_ppe_scheduler(eth, 0, 500000);
 384         mtk_ppe_scheduler(eth, 1, 500000);
 385         mtk_ppe_queue(eth, 0, 0, 7, 32, 250000, 0);
 386         mtk_ppe_queue(eth, 1, 0, 7, 32, 250000, 0);
 387         mtk_ppe_queue(eth, 8, 1, 7, 32, 250000, 0);
 388         mtk_ppe_queue(eth, 9, 1, 7, 32, 250000, 0);
 389 #endif
 390
 391         return 0;
 392 }
 393
 394 static int mtk_ppe_busy_wait(struct mtk_eth *eth)
 395 {
 396         unsigned long t_start = jiffies;
 397         u32 r = 0;
 398
 399         while (1) {
 400                 r = mtk_r32(eth, MTK_REG_PPE_GLO_CFG);
 401                 if (!(r & MTK_PPE_GLO_CFG_BUSY))
 402                         return 0;
 403                 if (time_after(jiffies, t_start + HZ))
 404                         break;
 405                 usleep_range(10, 20);
 406         }
 407
 408         dev_err(eth->dev, "ppe: table busy timeout - resetting\n");
 409         reset_control_reset(eth->rst_ppe);
 410
 411         return -ETIMEDOUT;
 412 }
 413
 414 static int mtk_ppe_stop(struct mtk_eth *eth)
 415 {
 416         u32 r1 = 0, r2 = 0;
 417         int i;
 418
 419         /* discard all traffic while we disable the PPE */
 420         mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(0));
 421         mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(1));
 422
 423         if (mtk_ppe_busy_wait(eth))
 424                 return -ETIMEDOUT;
 425
 426         /* invalidate all flow table entries */
 427         for (i = 0; i < MTK_PPE_ENTRY_CNT; i++)
 428                 eth->foe_table[i].bfib1.state = FOE_STATE_INVALID;
 429
 430         /* disable caching */
 431         mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
 432         mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_CAH_CTRL_EN, 0,
 433                 MTK_REG_PPE_CAH_CTRL);
 434
 435         /* flush cache has to be ahead of hnat diable --*/
 436         mtk_m32(eth, MTK_PPE_GLO_CFG_EN, 0, MTK_REG_PPE_GLO_CFG);
 437
 438         /* disable FOE */
 439         mtk_m32(eth,
 440                 MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
 441                 MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
 442                 MTK_PPE_FLOW_CFG_FUC_FOE | MTK_PPE_FLOW_CFG_FMC_FOE,
 443                 0, MTK_REG_PPE_FLOW_CFG);
 444
 445         /* disable FOE aging */
 446         mtk_m32(eth, 0,
 447                 MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
 448                 MTK_PPE_TB_CFG_TCP_AGE | MTK_PPE_TB_CFG_UNBD_AGE |
 449                 MTK_PPE_TB_CFG_NTU_AGE, MTK_REG_PPE_TB_CFG);
 450
 451         r1 = mtk_r32(eth, 0x100);
 452         r2 = mtk_r32(eth, 0x10c);
 453
 454         dev_info(eth->dev, "0x100 = 0x%x, 0x10c = 0x%x\n", r1, r2);
 455
 456         if (((r1 & 0xff00) >> 0x8) >= (r1 & 0xff) ||
 457             ((r1 & 0xff00) >> 0x8) >= (r2 & 0xff)) {
 458                 dev_info(eth->dev, "reset pse\n");
 459                 mtk_w32(eth, 0x1, 0x4);
 460         }
 461
 462         /* set the foe entry base address to 0 */
 463         mtk_w32(eth, 0, MTK_REG_PPE_TB_BASE);
 464
 465         if (mtk_ppe_busy_wait(eth))
 466                 return -ETIMEDOUT;
 467
 468         /* send all traffic back to the DMA engine */
 469 #ifdef CONFIG_RALINK
 470         mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(0));
 471         mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(1));
 472 #else
 473         mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(0));
 474         mtk_m32(eth, 0xffff, 0x5555, MTK_GDMA_FWD_CFG(1));
 475 #endif
 476         return 0;
 477 }
 478
 479 static void mtk_offload_keepalive(struct fe_priv *eth, unsigned int hash)
 480 {
 481         struct flow_offload *flow;
 482
 483         rcu_read_lock();
 484         flow = rcu_dereference(eth->foe_flow_table[hash]);
 485         if (flow)
 486                 flow->timeout = jiffies + 30 * HZ;
 487         rcu_read_unlock();
 488 }
 489
 490 int mtk_offload_check_rx(struct fe_priv *eth, struct sk_buff *skb, u32 rxd4)
 491 {
 492         unsigned int hash;
 493
 494         switch (FIELD_GET(MTK_RXD4_CPU_REASON, rxd4)) {
 495         case MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR:
 496         case MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR:
 497         case MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR:
 498                 hash = FIELD_GET(MTK_RXD4_FOE_ENTRY, rxd4);
 499                 mtk_offload_keepalive(eth, hash);
 500                 return -1;
 501         case MTK_CPU_REASON_PACKET_SAMPLING:
 502                 return -1;
 503         default:
 504                 return 0;
 505         }
 506 }
 507
 508 int mtk_ppe_probe(struct mtk_eth *eth)
 509 {
 510         int err;
 511
 512         err = mtk_ppe_start(eth);
 513         if (err)
 514                 return err;
 515
 516         err = mtk_ppe_debugfs_init(eth);
 517         if (err)
 518                 return err;
 519
 520         return 0;
 521 }
 522
 523 void mtk_ppe_remove(struct mtk_eth *eth)
 524 {
 525         mtk_ppe_stop(eth);
 526 }