ramips: switch to linux 4.14
[openwrt/openwrt.git] / target / linux / ramips / files-4.9 / drivers / net / ethernet / mtk / gsw_mt7620.h
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #ifndef _RALINK_GSW_MT7620_H__
16 #define _RALINK_GSW_MT7620_H__
17
18 #define GSW_REG_PHY_TIMEOUT (5 * HZ)
19
20 #ifdef CONFIG_SOC_MT7621
21 #define MT7620A_GSW_REG_PIAC 0x0004
22 #else
23 #define MT7620A_GSW_REG_PIAC 0x7004
24 #endif
25
26 #define GSW_NUM_VLANS 16
27 #define GSW_NUM_VIDS 4096
28 #define GSW_NUM_PORTS 7
29 #define GSW_PORT6 6
30
31 #define GSW_MDIO_ACCESS BIT(31)
32 #define GSW_MDIO_READ BIT(19)
33 #define GSW_MDIO_WRITE BIT(18)
34 #define GSW_MDIO_START BIT(16)
35 #define GSW_MDIO_ADDR_SHIFT 20
36 #define GSW_MDIO_REG_SHIFT 25
37
38 #define GSW_REG_MIB_CNT_EN 0x4000
39
40 #define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
41 #define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
42 #define GSW_REG_SMACCR0 0x3fE4
43 #define GSW_REG_SMACCR1 0x3fE8
44 #define GSW_REG_CKGCR 0x3ff0
45
46 #define GSW_REG_IMR 0x7008
47 #define GSW_REG_ISR 0x700c
48 #define GSW_REG_GPC1 0x7014
49
50 #define GSW_REG_MAC_P0_MCR 0x100
51 #define GSW_REG_MAC_P1_MCR 0x200
52
53 // Global MAC control register
54 #define GSW_REG_GMACCR 0x30E0
55
56 #define SYSC_REG_CHIP_REV_ID 0x0c
57 #define SYSC_REG_CFG1 0x14
58 #define RST_CTRL_MCM BIT(2)
59 #define SYSC_PAD_RGMII2_MDIO 0x58
60 #define SYSC_GPIO_MODE 0x60
61
62 #define PORT_IRQ_ST_CHG 0x7f
63
64 #ifdef CONFIG_SOC_MT7621
65 #define ESW_PHY_POLLING 0x0000
66 #else
67 #define ESW_PHY_POLLING 0x7000
68 #endif
69
70 #define PMCR_IPG BIT(18)
71 #define PMCR_MAC_MODE BIT(16)
72 #define PMCR_FORCE BIT(15)
73 #define PMCR_TX_EN BIT(14)
74 #define PMCR_RX_EN BIT(13)
75 #define PMCR_BACKOFF BIT(9)
76 #define PMCR_BACKPRES BIT(8)
77 #define PMCR_RX_FC BIT(5)
78 #define PMCR_TX_FC BIT(4)
79 #define PMCR_SPEED(_x) (_x << 2)
80 #define PMCR_DUPLEX BIT(1)
81 #define PMCR_LINK BIT(0)
82
83 #define PHY_AN_EN BIT(31)
84 #define PHY_PRE_EN BIT(30)
85 #define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
86
87
88 enum {
89 /* Global attributes. */
90 GSW_ATTR_ENABLE_VLAN,
91 /* Port attributes. */
92 GSW_ATTR_PORT_UNTAG,
93 };
94
95 enum {
96 PORT4_EPHY = 0,
97 PORT4_EXT,
98 };
99
100 struct mt7620_gsw {
101 struct device *dev;
102 void __iomem *base;
103 int irq;
104 int port4;
105 unsigned long int autopoll;
106 };
107
108 void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
109 u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
110 int mtk_gsw_init(struct fe_priv *priv);
111
112 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
113 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
114 void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
115 int mt7620_has_carrier(struct fe_priv *priv);
116 void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
117 int speed, int duplex);
118
119 void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
120 u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
121
122 u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
123 u32 phy_register, u32 write_data);
124 u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
125 void mt7620_handle_carrier(struct fe_priv *priv);
126
127 #endif