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[openwrt/openwrt.git] / target / linux / ramips / files-4.9 / drivers / net / ethernet / mtk / mt7530.c
1 /*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
13 * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
14 */
15
16 #include <linux/if.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/bitops.h>
25 #include <net/genetlink.h>
26 #include <linux/switch.h>
27 #include <linux/delay.h>
28 #include <linux/phy.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/lockdep.h>
32 #include <linux/workqueue.h>
33 #include <linux/of_device.h>
34
35 #include "mt7530.h"
36
37 #define MT7530_CPU_PORT 6
38 #define MT7530_NUM_PORTS 8
39 #ifdef CONFIG_SOC_MT7621
40 #define MT7530_NUM_VLANS 4095
41 #else
42 #define MT7530_NUM_VLANS 16
43 #endif
44 #define MT7530_MAX_VID 4095
45 #define MT7530_MIN_VID 0
46
47 #define MT7530_PORT_MIB_TXB_ID 2 /* TxGOC */
48 #define MT7530_PORT_MIB_RXB_ID 6 /* RxGOC */
49
50 #define MT7621_PORT_MIB_TXB_ID 18 /* TxByte */
51 #define MT7621_PORT_MIB_RXB_ID 37 /* RxByte */
52
53 /* registers */
54 #define REG_ESW_VLAN_VTCR 0x90
55 #define REG_ESW_VLAN_VAWD1 0x94
56 #define REG_ESW_VLAN_VAWD2 0x98
57 #define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
58
59 #define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
60 #define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
61 #define REG_ESW_VLAN_VAWD1_VALID BIT(0)
62
63 /* vlan egress mode */
64 enum {
65 ETAG_CTRL_UNTAG = 0,
66 ETAG_CTRL_TAG = 2,
67 ETAG_CTRL_SWAP = 1,
68 ETAG_CTRL_STACK = 3,
69 };
70
71 #define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
72 #define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
73 #define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
74
75 #define REG_HWTRAP 0x7804
76
77 #define MIB_DESC(_s , _o, _n) \
78 { \
79 .size = (_s), \
80 .offset = (_o), \
81 .name = (_n), \
82 }
83
84 struct mt7xxx_mib_desc {
85 unsigned int size;
86 unsigned int offset;
87 const char *name;
88 };
89
90 static const struct mt7xxx_mib_desc mt7620_mibs[] = {
91 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
92 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
93 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
94 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
95 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
96 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
97 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
98 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
99 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
100 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
101 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
102 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
103 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
104 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
105 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
106 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
107 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
108 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
109 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
110 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
111 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
112 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
113 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
114 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
115 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
116 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
117 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
118 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
119 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
120 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
121 };
122
123 static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
124 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN, "TxGPC"),
125 MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN, "TxBOC"),
126 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN, "TxGOC"),
127 MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN, "TxEPC"),
128 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN, "RxGPC"),
129 MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN, "RxBOC"),
130 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN, "RxGOC"),
131 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
132 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
133 };
134
135 static const struct mt7xxx_mib_desc mt7621_mibs[] = {
136 MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
137 MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
138 MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
139 MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
140 MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
141 MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
142 MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
143 MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
144 MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
145 MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
146 MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
147 MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
148 MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
149 MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
150 MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
151 MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
152 MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
153 MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
154 MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
155 MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
156 MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
157 MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
158 MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
159 MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
160 MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
161 MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
162 MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
163 MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
164 MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
165 MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
166 MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
167 MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
168 MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
169 MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
170 MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
171 MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
172 MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
173 MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
174 MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
175 MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
176 MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
177 };
178
179 enum {
180 /* Global attributes. */
181 MT7530_ATTR_ENABLE_VLAN,
182 };
183
184 struct mt7530_port_entry {
185 u16 pvid;
186 };
187
188 struct mt7530_vlan_entry {
189 u16 vid;
190 u8 member;
191 u8 etags;
192 };
193
194 struct mt7530_priv {
195 void __iomem *base;
196 struct mii_bus *bus;
197 struct switch_dev swdev;
198
199 bool global_vlan_enable;
200 struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
201 struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
202 };
203
204 struct mt7530_mapping {
205 char *name;
206 u16 pvids[MT7530_NUM_PORTS];
207 u8 members[MT7530_NUM_VLANS];
208 u8 etags[MT7530_NUM_VLANS];
209 u16 vids[MT7530_NUM_VLANS];
210 } mt7530_defaults[] = {
211 {
212 .name = "llllw",
213 .pvids = { 1, 1, 1, 1, 2, 1, 1 },
214 .members = { 0, 0x6f, 0x50 },
215 .etags = { 0, 0x40, 0x40 },
216 .vids = { 0, 1, 2 },
217 }, {
218 .name = "wllll",
219 .pvids = { 2, 1, 1, 1, 1, 1, 1 },
220 .members = { 0, 0x7e, 0x41 },
221 .etags = { 0, 0x40, 0x40 },
222 .vids = { 0, 1, 2 },
223 }, {
224 .name = "lwlll",
225 .pvids = { 1, 2, 1, 1, 1, 1, 1 },
226 .members = { 0, 0x7d, 0x42 },
227 .etags = { 0, 0x40, 0x40 },
228 .vids = { 0, 1, 2 },
229 },
230 };
231
232 struct mt7530_mapping*
233 mt7530_find_mapping(struct device_node *np)
234 {
235 const char *map;
236 int i;
237
238 if (of_property_read_string(np, "mediatek,portmap", &map))
239 return NULL;
240
241 for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
242 if (!strcmp(map, mt7530_defaults[i].name))
243 return &mt7530_defaults[i];
244
245 return NULL;
246 }
247
248 static void
249 mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
250 {
251 int i = 0;
252
253 for (i = 0; i < MT7530_NUM_PORTS; i++)
254 mt7530->port_entries[i].pvid = map->pvids[i];
255
256 for (i = 0; i < MT7530_NUM_VLANS; i++) {
257 mt7530->vlan_entries[i].member = map->members[i];
258 mt7530->vlan_entries[i].etags = map->etags[i];
259 mt7530->vlan_entries[i].vid = map->vids[i];
260 }
261 }
262
263 static int
264 mt7530_reset_switch(struct switch_dev *dev)
265 {
266 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
267 int i;
268
269 memset(priv->port_entries, 0, sizeof(priv->port_entries));
270 memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
271
272 /* set default vid of each vlan to the same number of vlan, so the vid
273 * won't need be set explicitly.
274 */
275 for (i = 0; i < MT7530_NUM_VLANS; i++) {
276 priv->vlan_entries[i].vid = i;
277 }
278
279 return 0;
280 }
281
282 static int
283 mt7530_get_vlan_enable(struct switch_dev *dev,
284 const struct switch_attr *attr,
285 struct switch_val *val)
286 {
287 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
288
289 val->value.i = priv->global_vlan_enable;
290
291 return 0;
292 }
293
294 static int
295 mt7530_set_vlan_enable(struct switch_dev *dev,
296 const struct switch_attr *attr,
297 struct switch_val *val)
298 {
299 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
300
301 priv->global_vlan_enable = val->value.i != 0;
302
303 return 0;
304 }
305
306 static u32
307 mt7530_r32(struct mt7530_priv *priv, u32 reg)
308 {
309 u32 val;
310 if (priv->bus) {
311 u16 high, low;
312
313 mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
314 low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
315 high = mdiobus_read(priv->bus, 0x1f, 0x10);
316
317 return (high << 16) | (low & 0xffff);
318 }
319
320 val = ioread32(priv->base + reg);
321 pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
322
323 return val;
324 }
325
326 static void
327 mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
328 {
329 if (priv->bus) {
330 mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
331 mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
332 mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
333 return;
334 }
335
336 pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
337 iowrite32(val, priv->base + reg);
338 }
339
340 static void
341 mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
342 {
343 int i;
344
345 mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
346
347 for (i = 0; i < 20; i++) {
348 u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
349
350 if ((val & BIT(31)) == 0)
351 break;
352
353 udelay(1000);
354 }
355 if (i == 20)
356 printk("mt7530: vtcr timeout\n");
357 }
358
359 static int
360 mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
361 {
362 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
363
364 if (port >= MT7530_NUM_PORTS)
365 return -EINVAL;
366
367 *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
368 *val &= 0xfff;
369
370 return 0;
371 }
372
373 static int
374 mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
375 {
376 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
377
378 if (port >= MT7530_NUM_PORTS)
379 return -EINVAL;
380
381 if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
382 return -EINVAL;
383
384 priv->port_entries[port].pvid = pvid;
385
386 return 0;
387 }
388
389 static int
390 mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
391 {
392 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
393 u32 member;
394 u32 etags;
395 int i;
396
397 val->len = 0;
398
399 if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
400 return -EINVAL;
401
402 mt7530_vtcr(priv, 0, val->port_vlan);
403
404 member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
405 member >>= 16;
406 member &= 0xff;
407
408 etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
409
410 for (i = 0; i < MT7530_NUM_PORTS; i++) {
411 struct switch_port *p;
412 int etag;
413
414 if (!(member & BIT(i)))
415 continue;
416
417 p = &val->value.ports[val->len++];
418 p->id = i;
419
420 etag = (etags >> (i * 2)) & 0x3;
421
422 if (etag == ETAG_CTRL_TAG)
423 p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
424 else if (etag != ETAG_CTRL_UNTAG)
425 printk("vlan egress tag control neither untag nor tag.\n");
426 }
427
428 return 0;
429 }
430
431 static int
432 mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
433 {
434 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
435 u8 member = 0;
436 u8 etags = 0;
437 int i;
438
439 if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
440 val->len > MT7530_NUM_PORTS)
441 return -EINVAL;
442
443 for (i = 0; i < val->len; i++) {
444 struct switch_port *p = &val->value.ports[i];
445
446 if (p->id >= MT7530_NUM_PORTS)
447 return -EINVAL;
448
449 member |= BIT(p->id);
450
451 if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
452 etags |= BIT(p->id);
453 }
454 priv->vlan_entries[val->port_vlan].member = member;
455 priv->vlan_entries[val->port_vlan].etags = etags;
456
457 return 0;
458 }
459
460 static int
461 mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
462 struct switch_val *val)
463 {
464 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
465 int vlan;
466 u16 vid;
467
468 vlan = val->port_vlan;
469 vid = (u16)val->value.i;
470
471 if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
472 return -EINVAL;
473
474 if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
475 return -EINVAL;
476
477 priv->vlan_entries[vlan].vid = vid;
478 return 0;
479 }
480
481 static int
482 mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
483 struct switch_val *val)
484 {
485 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
486 u32 vid;
487 int vlan;
488
489 vlan = val->port_vlan;
490
491 vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
492 if (vlan & 1)
493 vid = vid >> 12;
494 vid &= 0xfff;
495
496 val->value.i = vid;
497 return 0;
498 }
499
500 static void
501 mt7530_write_vlan_entry(struct mt7530_priv *priv, int vlan, u16 vid,
502 u8 ports, u8 etags)
503 {
504 int port;
505 u32 val;
506
507 #ifndef CONFIG_SOC_MT7621
508 /* vid of vlan */
509 val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
510 if (vlan % 2 == 0) {
511 val &= 0xfff000;
512 val |= vid;
513 } else {
514 val &= 0xfff;
515 val |= (vid << 12);
516 }
517 mt7530_w32(priv, REG_ESW_VLAN_VTIM(vlan), val);
518 #endif
519
520 /* vlan port membership */
521 if (ports)
522 mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
523 REG_ESW_VLAN_VAWD1_VTAG_EN | (ports << 16) |
524 REG_ESW_VLAN_VAWD1_VALID);
525 else
526 mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
527
528 /* egress mode */
529 val = 0;
530 for (port = 0; port < MT7530_NUM_PORTS; port++) {
531 if (etags & BIT(port))
532 val |= ETAG_CTRL_TAG << (port * 2);
533 else
534 val |= ETAG_CTRL_UNTAG << (port * 2);
535 }
536 mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
537
538 /* write to vlan table */
539 #ifdef CONFIG_SOC_MT7621
540 mt7530_vtcr(priv, 1, vid);
541 #else
542 mt7530_vtcr(priv, 1, vlan);
543 #endif
544 }
545
546 static int
547 mt7530_apply_config(struct switch_dev *dev)
548 {
549 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
550 int i, j;
551 u8 tag_ports;
552 u8 untag_ports;
553
554 if (!priv->global_vlan_enable) {
555 for (i = 0; i < MT7530_NUM_PORTS; i++)
556 mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00400000);
557
558 mt7530_w32(priv, REG_ESW_PORT_PCR(MT7530_CPU_PORT), 0x00ff0000);
559
560 for (i = 0; i < MT7530_NUM_PORTS; i++)
561 mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
562
563 return 0;
564 }
565
566 /* set all ports as security mode */
567 for (i = 0; i < MT7530_NUM_PORTS; i++)
568 mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
569
570 /* check if a port is used in tag/untag vlan egress mode */
571 tag_ports = 0;
572 untag_ports = 0;
573
574 for (i = 0; i < MT7530_NUM_VLANS; i++) {
575 u8 member = priv->vlan_entries[i].member;
576 u8 etags = priv->vlan_entries[i].etags;
577
578 if (!member)
579 continue;
580
581 for (j = 0; j < MT7530_NUM_PORTS; j++) {
582 if (!(member & BIT(j)))
583 continue;
584
585 if (etags & BIT(j))
586 tag_ports |= 1u << j;
587 else
588 untag_ports |= 1u << j;
589 }
590 }
591
592 /* set all untag-only ports as transparent and the rest as user port */
593 for (i = 0; i < MT7530_NUM_PORTS; i++) {
594 u32 pvc_mode = 0x81000000;
595
596 if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
597 pvc_mode = 0x810000c0;
598
599 mt7530_w32(priv, REG_ESW_PORT_PVC(i), pvc_mode);
600 }
601
602 /* first clear the swtich vlan table */
603 for (i = 0; i < MT7530_NUM_VLANS; i++)
604 mt7530_write_vlan_entry(priv, i, i, 0, 0);
605
606 /* now program only vlans with members to avoid
607 clobbering remapped entries in later iterations */
608 for (i = 0; i < MT7530_NUM_VLANS; i++) {
609 u16 vid = priv->vlan_entries[i].vid;
610 u8 member = priv->vlan_entries[i].member;
611 u8 etags = priv->vlan_entries[i].etags;
612
613 if (member)
614 mt7530_write_vlan_entry(priv, i, vid, member, etags);
615 }
616
617 /* Port Default PVID */
618 for (i = 0; i < MT7530_NUM_PORTS; i++) {
619 int vlan = priv->port_entries[i].pvid;
620 u16 pvid = 0;
621 u32 val;
622
623 if (vlan < MT7530_NUM_VLANS && priv->vlan_entries[vlan].member)
624 pvid = priv->vlan_entries[vlan].vid;
625
626 val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
627 val &= ~0xfff;
628 val |= pvid;
629 mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
630 }
631
632 return 0;
633 }
634
635 static int
636 mt7530_get_port_link(struct switch_dev *dev, int port,
637 struct switch_port_link *link)
638 {
639 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
640 u32 speed, pmsr;
641
642 if (port < 0 || port >= MT7530_NUM_PORTS)
643 return -EINVAL;
644
645 pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
646
647 link->link = pmsr & 1;
648 link->duplex = (pmsr >> 1) & 1;
649 speed = (pmsr >> 2) & 3;
650
651 switch (speed) {
652 case 0:
653 link->speed = SWITCH_PORT_SPEED_10;
654 break;
655 case 1:
656 link->speed = SWITCH_PORT_SPEED_100;
657 break;
658 case 2:
659 case 3: /* forced gige speed can be 2 or 3 */
660 link->speed = SWITCH_PORT_SPEED_1000;
661 break;
662 default:
663 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
664 break;
665 }
666
667 return 0;
668 }
669
670 static u64 get_mib_counter(struct mt7530_priv *priv, int i, int port)
671 {
672 unsigned int port_base;
673 u64 lo;
674
675 port_base = MT7621_MIB_COUNTER_BASE +
676 MT7621_MIB_COUNTER_PORT_OFFSET * port;
677
678 lo = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
679 if (mt7621_mibs[i].size == 2) {
680 u64 hi;
681
682 hi = mt7530_r32(priv, port_base + mt7621_mibs[i].offset + 4);
683 lo |= hi << 32;
684 }
685
686 return lo;
687 }
688
689 static int mt7621_sw_get_port_mib(struct switch_dev *dev,
690 const struct switch_attr *attr,
691 struct switch_val *val)
692 {
693 static char buf[4096];
694 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
695 int i, len = 0;
696
697 if (val->port_vlan >= MT7530_NUM_PORTS)
698 return -EINVAL;
699
700 len += snprintf(buf + len, sizeof(buf) - len,
701 "Port %d MIB counters\n", val->port_vlan);
702
703 for (i = 0; i < ARRAY_SIZE(mt7621_mibs); ++i) {
704 u64 counter;
705 len += snprintf(buf + len, sizeof(buf) - len,
706 "%-11s: ", mt7621_mibs[i].name);
707 counter = get_mib_counter(priv, i, val->port_vlan);
708 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
709 counter);
710 }
711
712 val->value.s = buf;
713 val->len = len;
714 return 0;
715 }
716
717 static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
718 {
719 return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
720 }
721
722 static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
723 {
724 return mt7530_r32(priv,
725 MT7620_MIB_COUNTER_BASE_PORT +
726 (MT7620_MIB_COUNTER_PORT_OFFSET * port) +
727 mt7620_port_mibs[i].offset);
728 }
729
730 static int mt7530_sw_get_mib(struct switch_dev *dev,
731 const struct switch_attr *attr,
732 struct switch_val *val)
733 {
734 static char buf[4096];
735 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
736 int i, len = 0;
737
738 len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
739
740 for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
741 u64 counter;
742 len += snprintf(buf + len, sizeof(buf) - len,
743 "%-11s: ", mt7620_mibs[i].name);
744 counter = get_mib_counter_7620(priv, i);
745 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
746 counter);
747 }
748
749 val->value.s = buf;
750 val->len = len;
751 return 0;
752 }
753
754 static int mt7530_sw_get_port_mib(struct switch_dev *dev,
755 const struct switch_attr *attr,
756 struct switch_val *val)
757 {
758 static char buf[4096];
759 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
760 int i, len = 0;
761
762 if (val->port_vlan >= MT7530_NUM_PORTS)
763 return -EINVAL;
764
765 len += snprintf(buf + len, sizeof(buf) - len,
766 "Port %d MIB counters\n", val->port_vlan);
767
768 for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
769 u64 counter;
770 len += snprintf(buf + len, sizeof(buf) - len,
771 "%-11s: ", mt7620_port_mibs[i].name);
772 counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
773 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
774 counter);
775 }
776
777 val->value.s = buf;
778 val->len = len;
779 return 0;
780 }
781
782 static int mt7530_get_port_stats(struct switch_dev *dev, int port,
783 struct switch_port_stats *stats)
784 {
785 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
786
787 if (port < 0 || port >= MT7530_NUM_PORTS)
788 return -EINVAL;
789
790 stats->tx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_TXB_ID, port);
791 stats->rx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_RXB_ID, port);
792
793 return 0;
794 }
795
796 static int mt7621_get_port_stats(struct switch_dev *dev, int port,
797 struct switch_port_stats *stats)
798 {
799 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
800
801 if (port < 0 || port >= MT7530_NUM_PORTS)
802 return -EINVAL;
803
804 stats->tx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_TXB_ID, port);
805 stats->rx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_RXB_ID, port);
806
807 return 0;
808 }
809
810 static const struct switch_attr mt7530_global[] = {
811 {
812 .type = SWITCH_TYPE_INT,
813 .name = "enable_vlan",
814 .description = "VLAN mode (1:enabled)",
815 .max = 1,
816 .id = MT7530_ATTR_ENABLE_VLAN,
817 .get = mt7530_get_vlan_enable,
818 .set = mt7530_set_vlan_enable,
819 }, {
820 .type = SWITCH_TYPE_STRING,
821 .name = "mib",
822 .description = "Get MIB counters for switch",
823 .get = mt7530_sw_get_mib,
824 .set = NULL,
825 },
826 };
827
828 static const struct switch_attr mt7621_port[] = {
829 {
830 .type = SWITCH_TYPE_STRING,
831 .name = "mib",
832 .description = "Get MIB counters for port",
833 .get = mt7621_sw_get_port_mib,
834 .set = NULL,
835 },
836 };
837
838 static const struct switch_attr mt7530_port[] = {
839 {
840 .type = SWITCH_TYPE_STRING,
841 .name = "mib",
842 .description = "Get MIB counters for port",
843 .get = mt7530_sw_get_port_mib,
844 .set = NULL,
845 },
846 };
847
848 static const struct switch_attr mt7530_vlan[] = {
849 {
850 .type = SWITCH_TYPE_INT,
851 .name = "vid",
852 .description = "VLAN ID (0-4094)",
853 .set = mt7530_set_vid,
854 .get = mt7530_get_vid,
855 .max = 4094,
856 },
857 };
858
859 static const struct switch_dev_ops mt7621_ops = {
860 .attr_global = {
861 .attr = mt7530_global,
862 .n_attr = ARRAY_SIZE(mt7530_global),
863 },
864 .attr_port = {
865 .attr = mt7621_port,
866 .n_attr = ARRAY_SIZE(mt7621_port),
867 },
868 .attr_vlan = {
869 .attr = mt7530_vlan,
870 .n_attr = ARRAY_SIZE(mt7530_vlan),
871 },
872 .get_vlan_ports = mt7530_get_vlan_ports,
873 .set_vlan_ports = mt7530_set_vlan_ports,
874 .get_port_pvid = mt7530_get_port_pvid,
875 .set_port_pvid = mt7530_set_port_pvid,
876 .get_port_link = mt7530_get_port_link,
877 .get_port_stats = mt7621_get_port_stats,
878 .apply_config = mt7530_apply_config,
879 .reset_switch = mt7530_reset_switch,
880 };
881
882 static const struct switch_dev_ops mt7530_ops = {
883 .attr_global = {
884 .attr = mt7530_global,
885 .n_attr = ARRAY_SIZE(mt7530_global),
886 },
887 .attr_port = {
888 .attr = mt7530_port,
889 .n_attr = ARRAY_SIZE(mt7530_port),
890 },
891 .attr_vlan = {
892 .attr = mt7530_vlan,
893 .n_attr = ARRAY_SIZE(mt7530_vlan),
894 },
895 .get_vlan_ports = mt7530_get_vlan_ports,
896 .set_vlan_ports = mt7530_set_vlan_ports,
897 .get_port_pvid = mt7530_get_port_pvid,
898 .set_port_pvid = mt7530_set_port_pvid,
899 .get_port_link = mt7530_get_port_link,
900 .get_port_stats = mt7530_get_port_stats,
901 .apply_config = mt7530_apply_config,
902 .reset_switch = mt7530_reset_switch,
903 };
904
905 int
906 mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
907 {
908 struct switch_dev *swdev;
909 struct mt7530_priv *mt7530;
910 struct mt7530_mapping *map;
911 int ret;
912
913 mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
914 if (!mt7530)
915 return -ENOMEM;
916
917 mt7530->base = base;
918 mt7530->bus = bus;
919 mt7530->global_vlan_enable = vlan;
920
921 swdev = &mt7530->swdev;
922 if (bus) {
923 swdev->alias = "mt7530";
924 swdev->name = "mt7530";
925 } else if (IS_ENABLED(CONFIG_SOC_MT7621)) {
926 swdev->alias = "mt7621";
927 swdev->name = "mt7621";
928 } else {
929 swdev->alias = "mt7620";
930 swdev->name = "mt7620";
931 }
932 swdev->cpu_port = MT7530_CPU_PORT;
933 swdev->ports = MT7530_NUM_PORTS;
934 swdev->vlans = MT7530_NUM_VLANS;
935 if (IS_ENABLED(CONFIG_SOC_MT7621))
936 swdev->ops = &mt7621_ops;
937 else
938 swdev->ops = &mt7530_ops;
939
940 ret = register_switch(swdev, NULL);
941 if (ret) {
942 dev_err(dev, "failed to register mt7530\n");
943 return ret;
944 }
945
946
947 map = mt7530_find_mapping(dev->of_node);
948 if (map)
949 mt7530_apply_mapping(mt7530, map);
950 mt7530_apply_config(swdev);
951
952 /* magic vodoo */
953 if (!IS_ENABLED(CONFIG_SOC_MT7621) && bus && mt7530_r32(mt7530, REG_HWTRAP) != 0x1117edf) {
954 dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
955 mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
956 }
957 dev_info(dev, "loaded %s driver\n", swdev->name);
958
959 return 0;
960 }
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