target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/init.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/of_net.h>
  30 #include <linux/of_mdio.h>
  31 #include <linux/of_irq.h>
  32 #include <linux/of_address.h>
  33 #include <linux/switch.h>
  34
  35 #include <asm/mach-ralink/ralink_regs.h>
  36
  37 #include "ralink_soc_eth.h"
  38
  39 #include <linux/ioport.h>
  40 #include <linux/switch.h>
  41 #include <linux/mii.h>
  42
  43 #include <ralink_regs.h>
  44 #include <asm/mach-ralink/mt7620.h>
  45
  46 #include "ralink_soc_eth.h"
  47 #include "gsw_mt7620a.h"
  48 #include "mt7530.h"
  49 #include "mdio.h"
  50
  51 #define GSW_REG_PHY_TIMEOUT     (5 * HZ)
  52
  53 #ifdef CONFIG_SOC_MT7621
  54 #define MT7620A_GSW_REG_PIAC    0x0004
  55 #else
  56 #define MT7620A_GSW_REG_PIAC    0x7004
  57 #endif
  58
  59 #define GSW_NUM_VLANS           16
  60 #define GSW_NUM_VIDS            4096
  61 #define GSW_NUM_PORTS           7
  62 #define GSW_PORT6               6
  63
  64 #define GSW_MDIO_ACCESS         BIT(31)
  65 #define GSW_MDIO_READ           BIT(19)
  66 #define GSW_MDIO_WRITE          BIT(18)
  67 #define GSW_MDIO_START          BIT(16)
  68 #define GSW_MDIO_ADDR_SHIFT     20
  69 #define GSW_MDIO_REG_SHIFT      25
  70
  71 #define GSW_REG_PORT_PMCR(x)    (0x3000 + (x * 0x100))
  72 #define GSW_REG_PORT_STATUS(x)  (0x3008 + (x * 0x100))
  73 #define GSW_REG_SMACCR0         0x3fE4
  74 #define GSW_REG_SMACCR1         0x3fE8
  75 #define GSW_REG_CKGCR           0x3ff0
  76
  77 #define GSW_REG_IMR             0x7008
  78 #define GSW_REG_ISR             0x700c
  79 #define GSW_REG_GPC1            0x7014
  80
  81 #define SYSC_REG_CHIP_REV_ID    0x0c
  82 #define SYSC_REG_CFG1           0x14
  83 #define RST_CTRL_MCM            BIT(2)
  84 #define SYSC_PAD_RGMII2_MDIO    0x58
  85 #define SYSC_GPIO_MODE          0x60
  86
  87 #define PORT_IRQ_ST_CHG         0x7f
  88
  89
  90 #ifdef CONFIG_SOC_MT7621
  91 #define ESW_PHY_POLLING         0x0000
  92 #else
  93 #define ESW_PHY_POLLING         0x7000
  94 #endif
  95
  96 #define PMCR_IPG                BIT(18)
  97 #define PMCR_MAC_MODE           BIT(16)
  98 #define PMCR_FORCE              BIT(15)
  99 #define PMCR_TX_EN              BIT(14)
 100 #define PMCR_RX_EN              BIT(13)
 101 #define PMCR_BACKOFF            BIT(9)
 102 #define PMCR_BACKPRES           BIT(8)
 103 #define PMCR_RX_FC              BIT(5)
 104 #define PMCR_TX_FC              BIT(4)
 105 #define PMCR_SPEED(_x)          (_x << 2)
 106 #define PMCR_DUPLEX             BIT(1)
 107 #define PMCR_LINK               BIT(0)
 108
 109 #define PHY_AN_EN               BIT(31)
 110 #define PHY_PRE_EN              BIT(30)
 111 #define PMY_MDC_CONF(_x)        ((_x & 0x3f) << 24)
 112
 113 enum {
 114         /* Global attributes. */
 115         GSW_ATTR_ENABLE_VLAN,
 116         /* Port attributes. */
 117         GSW_ATTR_PORT_UNTAG,
 118 };
 119
 120 enum {
 121         PORT4_EPHY = 0,
 122         PORT4_EXT,
 123 };
 124
 125 struct mt7620_gsw {
 126         struct device           *dev;
 127         void __iomem            *base;
 128         int                     irq;
 129         int                     port4;
 130         long unsigned int       autopoll;
 131 };
 132
 133 static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
 134 {
 135         iowrite32(val, gsw->base + reg);
 136 }
 137
 138 static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
 139 {
 140         return ioread32(gsw->base + reg);
 141 }
 142
 143 static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
 144 {
 145         unsigned long t_start = jiffies;
 146
 147         while (1) {
 148                 if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
 149                         return 0;
 150                 if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
 151                         break;
 152                 }
 153         }
 154
 155         printk(KERN_ERR "mdio: MDIO timeout\n");
 156         return -1;
 157 }
 158
 159 static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
 160                                 u32 write_data)
 161 {
 162         if (mt7620_mii_busy_wait(gsw))
 163                 return -1;
 164
 165         write_data &= 0xffff;
 166
 167         gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
 168                 (phy_register << GSW_MDIO_REG_SHIFT) |
 169                 (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
 170                 MT7620A_GSW_REG_PIAC);
 171
 172         if (mt7620_mii_busy_wait(gsw))
 173                 return -1;
 174
 175         return 0;
 176 }
 177
 178 static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
 179 {
 180         u32 d;
 181
 182         if (mt7620_mii_busy_wait(gsw))
 183                 return 0xffff;
 184
 185         gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
 186                 (phy_reg << GSW_MDIO_REG_SHIFT) |
 187                 (phy_addr << GSW_MDIO_ADDR_SHIFT),
 188                 MT7620A_GSW_REG_PIAC);
 189
 190         if (mt7620_mii_busy_wait(gsw))
 191                 return 0xffff;
 192
 193         d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
 194
 195         return d;
 196 }
 197
 198 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
 199 {
 200         struct fe_priv *priv = bus->priv;
 201         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 202
 203         return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
 204 }
 205
 206 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
 207 {
 208         struct fe_priv *priv = bus->priv;
 209         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 210
 211         return _mt7620_mii_read(gsw, phy_addr, phy_reg);
 212 }
 213
 214 static void
 215 mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
 216 {
 217         _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
 218         _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
 219         _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
 220 }
 221
 222 static u32
 223 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
 224 {
 225         u16 high, low;
 226
 227         _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
 228         low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
 229         high = _mt7620_mii_read(gsw, 0x1f, 0x10);
 230
 231         return (high << 16) | (low & 0xffff);
 232 }
 233
 234 static unsigned char *fe_speed_str(int speed)
 235 {
 236         switch (speed) {
 237         case 2:
 238         case SPEED_1000:
 239                 return "1000";
 240         case 1:
 241         case SPEED_100:
 242                 return "100";
 243         case 0:
 244         case SPEED_10:
 245                 return "10";
 246         }
 247
 248         return "? ";
 249 }
 250
 251 int mt7620a_has_carrier(struct fe_priv *priv)
 252 {
 253         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 254         int i;
 255
 256         for (i = 0; i < GSW_PORT6; i++)
 257                 if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
 258                         return 1;
 259         return 0;
 260 }
 261
 262 static void mt7620a_handle_carrier(struct fe_priv *priv)
 263 {
 264         if (!priv->phy)
 265                 return;
 266
 267         if (mt7620a_has_carrier(priv))
 268                 netif_carrier_on(priv->netdev);
 269         else
 270                 netif_carrier_off(priv->netdev);
 271 }
 272
 273 void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
 274 {
 275         if (priv->link[port])
 276                 netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
 277                         port, fe_speed_str(priv->phy->speed[port]),
 278                         (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
 279         else
 280                 netdev_info(priv->netdev, "port %d link down\n", port);
 281         mt7620a_handle_carrier(priv);
 282 }
 283
 284 static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
 285 {
 286         struct fe_priv *priv = (struct fe_priv *) _priv;
 287         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 288         u32 status;
 289         int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
 290
 291         status = gsw_r32(gsw, GSW_REG_ISR);
 292         if (status & PORT_IRQ_ST_CHG)
 293                 for (i = 0; i <= max; i++) {
 294                         u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
 295                         int link = status & 0x1;
 296
 297                         if (link != priv->link[i]) {
 298                                 if (link)
 299                                         netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
 300                                                         i, fe_speed_str((status >> 2) & 3),
 301                                                         (status & 0x2) ? "Full" : "Half");
 302                                 else
 303                                         netdev_info(priv->netdev, "port %d link down\n", i);
 304                         }
 305
 306                         priv->link[i] = link;
 307                 }
 308         mt7620a_handle_carrier(priv);
 309
 310         gsw_w32(gsw, status, GSW_REG_ISR);
 311
 312         return IRQ_HANDLED;
 313 }
 314
 315 static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
 316 {
 317         struct fe_priv *priv = (struct fe_priv *) _priv;
 318         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 319         u32 reg, i;
 320
 321         reg = mt7530_mdio_r32(gsw, 0x700c);
 322
 323         for (i = 0; i < 5; i++)
 324                 if (reg & BIT(i)) {
 325                         unsigned int link = mt7530_mdio_r32(gsw, 0x3008 + (i * 0x100)) & 0x1;
 326
 327                         if (link != priv->link[i]) {
 328                                 priv->link[i] = link;
 329                                 if (link)
 330                                         netdev_info(priv->netdev, "port %d link up\n", i);
 331                                 else
 332                                         netdev_info(priv->netdev, "port %d link down\n", i);
 333                         }
 334                 }
 335
 336         mt7620a_handle_carrier(priv);
 337         mt7530_mdio_w32(gsw, 0x700c, 0x1f);
 338
 339         return IRQ_HANDLED;
 340 }
 341
 342 static int mt7620_is_bga(void)
 343 {
 344         u32 bga = rt_sysc_r32(0x0c);
 345
 346         return (bga >> 16) & 1;
 347 }
 348
 349 static void gsw_auto_poll(struct mt7620_gsw *gsw)
 350 {
 351         int phy;
 352         int lsb = -1, msb = 0;
 353
 354         for_each_set_bit(phy, &gsw->autopoll, 32) {
 355                 if (lsb < 0)
 356                         lsb = phy;
 357                 msb = phy;
 358         }
 359
 360         if (lsb == msb)
 361                 lsb--;
 362
 363         gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
 364 }
 365
 366 void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 367 {
 368         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 369         const __be32 *_id = of_get_property(np, "reg", NULL);
 370         int phy_mode, size, id;
 371         int shift = 12;
 372         u32 val, mask = 0;
 373         int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
 374
 375         if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 376                 if (_id)
 377                         pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
 378                 else
 379                         pr_err("%s: invalid port id\n", np->name);
 380                 return;
 381         }
 382
 383         id = be32_to_cpu(*_id);
 384
 385         if (id == 4)
 386                 shift = 14;
 387
 388         priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
 389         if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 390                 pr_err("%s: invalid fixed link property\n", np->name);
 391                 priv->phy->phy_fixed[id] = NULL;
 392                 return;
 393         }
 394
 395         phy_mode = of_get_phy_mode(np);
 396         switch (phy_mode) {
 397         case PHY_INTERFACE_MODE_RGMII:
 398                 mask = 0;
 399                 break;
 400         case PHY_INTERFACE_MODE_MII:
 401                 mask = 1;
 402                 break;
 403         case PHY_INTERFACE_MODE_RMII:
 404                 mask = 2;
 405                 break;
 406         default:
 407                 dev_err(priv->device, "port %d - invalid phy mode\n", id);
 408                 return;
 409         }
 410
 411         priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 412         if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
 413                 return;
 414
 415         val = rt_sysc_r32(SYSC_REG_CFG1);
 416         val &= ~(3 << shift);
 417         val |= mask << shift;
 418         rt_sysc_w32(val, SYSC_REG_CFG1);
 419
 420         if (priv->phy->phy_fixed[id]) {
 421                 const __be32 *link = priv->phy->phy_fixed[id];
 422                 int tx_fc, rx_fc;
 423                 u32 val = 0;
 424
 425                 priv->phy->speed[id] = be32_to_cpup(link++);
 426                 tx_fc = be32_to_cpup(link++);
 427                 rx_fc = be32_to_cpup(link++);
 428                 priv->phy->duplex[id] = be32_to_cpup(link++);
 429                 priv->link[id] = 1;
 430
 431                 switch (priv->phy->speed[id]) {
 432                 case SPEED_10:
 433                         val = 0;
 434                         break;
 435                 case SPEED_100:
 436                         val = 1;
 437                         break;
 438                 case SPEED_1000:
 439                         val = 2;
 440                         break;
 441                 default:
 442                         dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
 443                         priv->phy->phy_fixed[id] = 0;
 444                         return;
 445                 }
 446                 val = PMCR_SPEED(val);
 447                 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 448                         PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 449                 if (tx_fc)
 450                         val |= PMCR_TX_FC;
 451                 if (rx_fc)
 452                         val |= PMCR_RX_FC;
 453                 if (priv->phy->duplex[id])
 454                         val |= PMCR_DUPLEX;
 455                 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 456                 dev_info(priv->device, "using fixed link parameters\n");
 457                 return;
 458         }
 459
 460         if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
 461                 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 462                         PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 463
 464                 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 465                 fe_connect_phy_node(priv, priv->phy->phy_node[id]);
 466                 gsw->autopoll |= BIT(id);
 467                 gsw_auto_poll(gsw);
 468                 return;
 469         }
 470 }
 471
 472 static void gsw_hw_init_mt7620(struct mt7620_gsw *gsw, struct device_node *np)
 473 {
 474         u32 is_BGA = mt7620_is_bga();
 475
 476         rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
 477         gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
 478
 479         if (of_property_read_bool(np, "mediatek,mt7530")) {
 480                 u32 val;
 481
 482                 /* turn off ephy and set phy base addr to 12 */
 483                 gsw_w32(gsw, gsw_r32(gsw, GSW_REG_GPC1) | (0x1f << 24) | (0xc << 16), GSW_REG_GPC1);
 484
 485                 /* set MT7530 central align */
 486                 val = mt7530_mdio_r32(gsw, 0x7830);
 487                 val &= ~1;
 488                 val |= 1<<1;
 489                 mt7530_mdio_w32(gsw, 0x7830, val);
 490
 491                 val = mt7530_mdio_r32(gsw, 0x7a40);
 492                 val &= ~(1<<30);
 493                 mt7530_mdio_w32(gsw, 0x7a40, val);
 494
 495                 mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 496         } else {
 497                 /* EPHY1 fixup - only run if the ephy is enabled */
 498
 499                 /*correct  PHY  setting L3.0 BGA*/
 500                 _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
 501
 502                 _mt7620_mii_write(gsw, 1, 17, 0x7444);
 503                 if (is_BGA)
 504                         _mt7620_mii_write(gsw, 1, 19, 0x0114);
 505                 else
 506                         _mt7620_mii_write(gsw, 1, 19, 0x0117);
 507
 508                 _mt7620_mii_write(gsw, 1, 22, 0x10cf);
 509                 _mt7620_mii_write(gsw, 1, 25, 0x6212);
 510                 _mt7620_mii_write(gsw, 1, 26, 0x0777);
 511                 _mt7620_mii_write(gsw, 1, 29, 0x4000);
 512                 _mt7620_mii_write(gsw, 1, 28, 0xc077);
 513                 _mt7620_mii_write(gsw, 1, 24, 0x0000);
 514
 515                 _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
 516                 _mt7620_mii_write(gsw, 1, 17, 0x4838);
 517
 518                 _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
 519                 if (is_BGA) {
 520                         _mt7620_mii_write(gsw, 1, 21, 0x0515);
 521                         _mt7620_mii_write(gsw, 1, 22, 0x0053);
 522                         _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 523                         _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
 524                         _mt7620_mii_write(gsw, 1, 25, 0x0fad);
 525                         _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
 526                 } else {
 527                         _mt7620_mii_write(gsw, 1, 21, 0x0517);
 528                         _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
 529                         _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 530                         _mt7620_mii_write(gsw, 1, 24, 0x0aab);
 531                         _mt7620_mii_write(gsw, 1, 25, 0x00ae);
 532                         _mt7620_mii_write(gsw, 1, 26, 0x0fff);
 533                 }
 534                 _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
 535                 _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
 536         }
 537
 538         _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
 539         _mt7620_mii_write(gsw, 0, 30, 0xa000);
 540         _mt7620_mii_write(gsw, 1, 30, 0xa000);
 541         _mt7620_mii_write(gsw, 2, 30, 0xa000);
 542         _mt7620_mii_write(gsw, 3, 30, 0xa000);
 543
 544         _mt7620_mii_write(gsw, 0, 4, 0x05e1);
 545         _mt7620_mii_write(gsw, 1, 4, 0x05e1);
 546         _mt7620_mii_write(gsw, 2, 4, 0x05e1);
 547         _mt7620_mii_write(gsw, 3, 4, 0x05e1);
 548
 549         _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
 550         _mt7620_mii_write(gsw, 0, 16, 0x1111);
 551         _mt7620_mii_write(gsw, 1, 16, 0x1010);
 552         _mt7620_mii_write(gsw, 2, 16, 0x1515);
 553         _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
 554
 555         /* CPU Port6 Force Link 1G, FC ON */
 556         gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
 557         /* Set Port6 CPU Port */
 558         gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
 559
 560         /* setup port 4 */
 561         if (gsw->port4 == PORT4_EPHY) {
 562                 u32 val = rt_sysc_r32(SYSC_REG_CFG1);
 563                 val |= 3 << 14;
 564                 rt_sysc_w32(val, SYSC_REG_CFG1);
 565                 _mt7620_mii_write(gsw, 4, 30, 0xa000);
 566                 _mt7620_mii_write(gsw, 4, 4, 0x05e1);
 567                 _mt7620_mii_write(gsw, 4, 16, 0x1313);
 568                 pr_info("gsw: setting port4 to ephy mode\n");
 569         }
 570 }
 571
 572 static void gsw_hw_init_mt7621(struct mt7620_gsw *gsw, struct device_node *np)
 573 {
 574         u32     i;
 575         u32     val;
 576
 577         /* Hardware reset Switch */
 578         fe_reset(RST_CTRL_MCM);
 579         udelay(10000);
 580
 581         /* reduce RGMII2 PAD driving strength */
 582         rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
 583
 584         /* gpio mux - RGMII1=Normal mode */
 585         rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
 586
 587         //GMAC1= RGMII mode
 588         rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
 589
 590         /* enable MDIO to control MT7530 */
 591         rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
 592
 593         /* turn off all PHYs */
 594         for (i = 0; i <= 4; i++) {
 595                 val = _mt7620_mii_read(gsw, i, 0x0);
 596                 val |= (0x1 << 11);
 597                 _mt7620_mii_write(gsw, i, 0x0, val);
 598         }
 599
 600         /* reset the switch */
 601         mt7530_mdio_w32(gsw, 0x7000, 0x3);
 602         udelay(10);
 603
 604         if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
 605                 /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
 606                 gsw_w32(gsw, 0x2105e30b, 0x100);
 607                 mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
 608         } else {
 609                 /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
 610                 gsw_w32(gsw, 0x2105e33b, 0x100);
 611                 mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
 612         }
 613
 614         /* (GE2, Link down) */
 615         gsw_w32(gsw, 0x8000, 0x200);
 616
 617         //val = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable
 618         val = mt7530_mdio_r32(gsw, 0x7804);
 619         val &= ~(1<<8); //Enable Port 6
 620         val |= (1<<6); //Disable Port 5
 621         val |= (1<<13); //Port 5 as GMAC, no Internal PHY
 622
 623         val |= (1<<16);//change HW-TRAP
 624         printk("change HW-TRAP to 0x%x\n", val);
 625         mt7530_mdio_w32(gsw, 0x7804, val);
 626
 627         val = rt_sysc_r32(0x10);
 628         val = (val >> 6) & 0x7;
 629         if (val >= 6) {
 630                 /* 25Mhz Xtal - do nothing */
 631         } else if(val >=3) {
 632                 /* 40Mhz */
 633
 634                 /* disable MT7530 core clock */
 635                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 636                 _mt7620_mii_write(gsw, 0, 14, 0x410);
 637                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 638                 _mt7620_mii_write(gsw, 0, 14, 0x0);
 639
 640                 /* disable MT7530 PLL */
 641                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 642                 _mt7620_mii_write(gsw, 0, 14, 0x40d);
 643                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 644                 _mt7620_mii_write(gsw, 0, 14, 0x2020);
 645
 646                 /* for MT7530 core clock = 500Mhz */
 647                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 648                 _mt7620_mii_write(gsw, 0, 14, 0x40e);
 649                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 650                 _mt7620_mii_write(gsw, 0, 14, 0x119);
 651
 652                 /* enable MT7530 PLL */
 653                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 654                 _mt7620_mii_write(gsw, 0, 14, 0x40d);
 655                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 656                 _mt7620_mii_write(gsw, 0, 14, 0x2820);
 657
 658                 udelay(20);
 659
 660                 /* enable MT7530 core clock */
 661                 _mt7620_mii_write(gsw, 0, 13, 0x1f);
 662                 _mt7620_mii_write(gsw, 0, 14, 0x410);
 663                 _mt7620_mii_write(gsw, 0, 13, 0x401f);
 664         } else {
 665                 /* 20Mhz Xtal - TODO */
 666         }
 667
 668         /* RGMII */
 669         _mt7620_mii_write(gsw, 0, 14, 0x1);
 670
 671         /* set MT7530 central align */
 672         val = mt7530_mdio_r32(gsw, 0x7830);
 673         val &= ~1;
 674         val |= 1<<1;
 675         mt7530_mdio_w32(gsw, 0x7830, val);
 676
 677         val = mt7530_mdio_r32(gsw, 0x7a40);
 678         val &= ~(1<<30);
 679         mt7530_mdio_w32(gsw, 0x7a40, val);
 680
 681         mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 682         mt7530_mdio_w32(gsw, 0x7b00, 0x102);  //delay setting for 10/1000M
 683         mt7530_mdio_w32(gsw, 0x7b04, 0x14);  //delay setting for 10/1000M
 684
 685         /*Tx Driving*/
 686         mt7530_mdio_w32(gsw, 0x7a54, 0x44);  //lower driving
 687         mt7530_mdio_w32(gsw, 0x7a5c, 0x44);  //lower driving
 688         mt7530_mdio_w32(gsw, 0x7a64, 0x44);  //lower driving
 689         mt7530_mdio_w32(gsw, 0x7a6c, 0x44);  //lower driving
 690         mt7530_mdio_w32(gsw, 0x7a74, 0x44);  //lower driving
 691         mt7530_mdio_w32(gsw, 0x7a7c, 0x44);  //lower driving
 692
 693         //LANWANPartition();
 694
 695         /* turn on all PHYs */
 696         for (i = 0; i <= 4; i++) {
 697                 val = _mt7620_mii_read(gsw, i, 0);
 698                 val &= ~BIT(11);
 699                 _mt7620_mii_write(gsw, i, 0, val);
 700         }
 701
 702         /* enable irq */
 703         val = mt7530_mdio_r32(gsw, 0x7808);
 704         val |= 3 << 16;
 705         mt7530_mdio_w32(gsw, 0x7808, val);
 706 }
 707
 708 void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
 709 {
 710         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 711         unsigned long flags;
 712
 713         spin_lock_irqsave(&priv->page_lock, flags);
 714         gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 715         gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 716                 GSW_REG_SMACCR0);
 717         spin_unlock_irqrestore(&priv->page_lock, flags);
 718 }
 719
 720 static struct of_device_id gsw_match[] = {
 721         { .compatible = "ralink,mt7620a-gsw" },
 722         {}
 723 };
 724
 725 int mt7620_gsw_config(struct fe_priv *priv)
 726 {
 727         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
 728
 729         /* is the mt7530 internal or external */
 730         if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
 731                 mt7530_probe(priv->device, gsw->base, NULL, 0);
 732                 mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
 733         } else {
 734                 mt7530_probe(priv->device, gsw->base, NULL, 1);
 735         }
 736
 737         return 0;
 738 }
 739
 740 int mt7621_gsw_config(struct fe_priv *priv)
 741 {
 742         if (priv->mii_bus && priv->mii_bus->phy_map[0x1f])
 743                 mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
 744
 745         return 0;
 746 }
 747
 748 int mt7620_gsw_probe(struct fe_priv *priv)
 749 {
 750         struct mt7620_gsw *gsw;
 751         struct device_node *np;
 752         const char *port4 = NULL;
 753
 754         np = of_find_matching_node(NULL, gsw_match);
 755         if (!np) {
 756                 dev_err(priv->device, "no gsw node found\n");
 757                 return -EINVAL;
 758         }
 759         np = of_node_get(np);
 760
 761         gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
 762         if (!gsw) {
 763                 dev_err(priv->device, "no gsw memory for private data\n");
 764                 return -ENOMEM;
 765         }
 766
 767         gsw->base = of_iomap(np, 0);
 768         if (!gsw->base) {
 769                 dev_err(priv->device, "gsw ioremap failed\n");
 770                 return -ENOMEM;
 771         }
 772
 773         gsw->dev = priv->device;
 774         priv->soc->swpriv = gsw;
 775
 776         of_property_read_string(np, "ralink,port4", &port4);
 777         if (port4 && !strcmp(port4, "ephy"))
 778                 gsw->port4 = PORT4_EPHY;
 779         else if (port4 && !strcmp(port4, "gmac"))
 780                 gsw->port4 = PORT4_EXT;
 781         else
 782                 gsw->port4 = PORT4_EPHY;
 783
 784         if (IS_ENABLED(CONFIG_SOC_MT7620))
 785                 gsw_hw_init_mt7620(gsw, np);
 786         else
 787                 gsw_hw_init_mt7621(gsw, np);
 788
 789         gsw->irq = irq_of_parse_and_map(np, 0);
 790         if (gsw->irq) {
 791                 if (IS_ENABLED(CONFIG_SOC_MT7620)) {
 792                         request_irq(gsw->irq, gsw_interrupt_mt7620, 0, "gsw", priv);
 793                         gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
 794                 } else {
 795                         request_irq(gsw->irq, gsw_interrupt_mt7621, 0, "gsw", priv);
 796                         mt7530_mdio_w32(gsw, 0x7008, 0x1f);
 797                 }
 798         }
 799
 800         return 0;
 801 }