ramips: 5.4: handle ERR_PTR properly
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
31 #include <linux/io.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35 #include <linux/of_gpio.h>
36 #include <linux/gpio.h>
37 #include <linux/gpio/consumer.h>
38
39 #include <asm/mach-ralink/ralink_regs.h>
40
41 #include "mtk_eth_soc.h"
42 #include "mdio.h"
43 #include "ethtool.h"
44
45 #define MAX_RX_LENGTH 1536
46 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
47 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
63
64 #define SYSC_REG_RSTCTRL 0x34
65
66 static int fe_msg_level = -1;
67 module_param_named(msg_level, fe_msg_level, int, 0);
68 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
69
70 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
71 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
72 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
73 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
74 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
75 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
76 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
77 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
78 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
79 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
80 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
81 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
82 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
83 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
84 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
85 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
86 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
87 };
88
89 static const u16 *fe_reg_table = fe_reg_table_default;
90
91 struct fe_work_t {
92 int bitnr;
93 void (*action)(struct fe_priv *);
94 };
95
96 static void __iomem *fe_base;
97
98 void fe_w32(u32 val, unsigned reg)
99 {
100 __raw_writel(val, fe_base + reg);
101 }
102
103 u32 fe_r32(unsigned reg)
104 {
105 return __raw_readl(fe_base + reg);
106 }
107
108 void fe_reg_w32(u32 val, enum fe_reg reg)
109 {
110 fe_w32(val, fe_reg_table[reg]);
111 }
112
113 u32 fe_reg_r32(enum fe_reg reg)
114 {
115 return fe_r32(fe_reg_table[reg]);
116 }
117
118 void fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg)
119 {
120 u32 val;
121
122 spin_lock(&eth->page_lock);
123 val = __raw_readl(fe_base + reg);
124 val &= ~clear;
125 val |= set;
126 __raw_writel(val, fe_base + reg);
127 spin_unlock(&eth->page_lock);
128 }
129
130 void fe_reset(u32 reset_bits)
131 {
132 u32 t;
133
134 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
135 t |= reset_bits;
136 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
137 usleep_range(10, 20);
138
139 t &= ~reset_bits;
140 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
141 usleep_range(10, 20);
142 }
143
144 static inline void fe_int_disable(u32 mask)
145 {
146 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
147 FE_REG_FE_INT_ENABLE);
148 /* flush write */
149 fe_reg_r32(FE_REG_FE_INT_ENABLE);
150 }
151
152 static inline void fe_int_enable(u32 mask)
153 {
154 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
155 FE_REG_FE_INT_ENABLE);
156 /* flush write */
157 fe_reg_r32(FE_REG_FE_INT_ENABLE);
158 }
159
160 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
161 {
162 unsigned long flags;
163
164 spin_lock_irqsave(&priv->page_lock, flags);
165 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
166 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
167 FE_GDMA1_MAC_ADRL);
168 spin_unlock_irqrestore(&priv->page_lock, flags);
169 }
170
171 static int fe_set_mac_address(struct net_device *dev, void *p)
172 {
173 int ret = eth_mac_addr(dev, p);
174
175 if (!ret) {
176 struct fe_priv *priv = netdev_priv(dev);
177
178 if (priv->soc->set_mac)
179 priv->soc->set_mac(priv, dev->dev_addr);
180 else
181 fe_hw_set_macaddr(priv, p);
182 }
183
184 return ret;
185 }
186
187 static inline int fe_max_frag_size(int mtu)
188 {
189 /* make sure buf_size will be at least MAX_RX_LENGTH */
190 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
191 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
192
193 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
194 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
195 }
196
197 static inline int fe_max_buf_size(int frag_size)
198 {
199 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
200 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
201
202 BUG_ON(buf_size < MAX_RX_LENGTH);
203 return buf_size;
204 }
205
206 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
207 {
208 rxd->rxd1 = dma_rxd->rxd1;
209 rxd->rxd2 = dma_rxd->rxd2;
210 rxd->rxd3 = dma_rxd->rxd3;
211 rxd->rxd4 = dma_rxd->rxd4;
212 }
213
214 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
215 {
216 dma_txd->txd1 = txd->txd1;
217 dma_txd->txd3 = txd->txd3;
218 dma_txd->txd4 = txd->txd4;
219 /* clean dma done flag last */
220 dma_txd->txd2 = txd->txd2;
221 }
222
223 static void fe_clean_rx(struct fe_priv *priv)
224 {
225 struct fe_rx_ring *ring = &priv->rx_ring;
226 struct page *page;
227 int i;
228
229 if (ring->rx_data) {
230 for (i = 0; i < ring->rx_ring_size; i++)
231 if (ring->rx_data[i]) {
232 if (ring->rx_dma && ring->rx_dma[i].rxd1)
233 dma_unmap_single(priv->dev,
234 ring->rx_dma[i].rxd1,
235 ring->rx_buf_size,
236 DMA_FROM_DEVICE);
237 skb_free_frag(ring->rx_data[i]);
238 }
239
240 kfree(ring->rx_data);
241 ring->rx_data = NULL;
242 }
243
244 if (ring->rx_dma) {
245 dma_free_coherent(priv->dev,
246 ring->rx_ring_size * sizeof(*ring->rx_dma),
247 ring->rx_dma,
248 ring->rx_phys);
249 ring->rx_dma = NULL;
250 }
251
252 if (!ring->frag_cache.va)
253 return;
254
255 page = virt_to_page(ring->frag_cache.va);
256 __page_frag_cache_drain(page, ring->frag_cache.pagecnt_bias);
257 memset(&ring->frag_cache, 0, sizeof(ring->frag_cache));
258 }
259
260 static int fe_alloc_rx(struct fe_priv *priv)
261 {
262 struct fe_rx_ring *ring = &priv->rx_ring;
263 int i, pad;
264
265 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
266 GFP_KERNEL);
267 if (!ring->rx_data)
268 goto no_rx_mem;
269
270 for (i = 0; i < ring->rx_ring_size; i++) {
271 ring->rx_data[i] = page_frag_alloc(&ring->frag_cache,
272 ring->frag_size,
273 GFP_KERNEL);
274 if (!ring->rx_data[i])
275 goto no_rx_mem;
276 }
277
278 ring->rx_dma = dma_alloc_coherent(priv->dev,
279 ring->rx_ring_size * sizeof(*ring->rx_dma),
280 &ring->rx_phys,
281 GFP_ATOMIC | __GFP_ZERO);
282 if (!ring->rx_dma)
283 goto no_rx_mem;
284
285 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
286 pad = 0;
287 else
288 pad = NET_IP_ALIGN;
289 for (i = 0; i < ring->rx_ring_size; i++) {
290 dma_addr_t dma_addr = dma_map_single(priv->dev,
291 ring->rx_data[i] + NET_SKB_PAD + pad,
292 ring->rx_buf_size,
293 DMA_FROM_DEVICE);
294 if (unlikely(dma_mapping_error(priv->dev, dma_addr)))
295 goto no_rx_mem;
296 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
297
298 if (priv->flags & FE_FLAG_RX_SG_DMA)
299 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
300 else
301 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
302 }
303 ring->rx_calc_idx = ring->rx_ring_size - 1;
304 /* make sure that all changes to the dma ring are flushed before we
305 * continue
306 */
307 wmb();
308
309 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
310 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
311 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
312 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
313
314 return 0;
315
316 no_rx_mem:
317 return -ENOMEM;
318 }
319
320 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
321 {
322 if (dma_unmap_len(tx_buf, dma_len0))
323 dma_unmap_page(dev,
324 dma_unmap_addr(tx_buf, dma_addr0),
325 dma_unmap_len(tx_buf, dma_len0),
326 DMA_TO_DEVICE);
327
328 if (dma_unmap_len(tx_buf, dma_len1))
329 dma_unmap_page(dev,
330 dma_unmap_addr(tx_buf, dma_addr1),
331 dma_unmap_len(tx_buf, dma_len1),
332 DMA_TO_DEVICE);
333
334 dma_unmap_len_set(tx_buf, dma_addr0, 0);
335 dma_unmap_len_set(tx_buf, dma_addr1, 0);
336 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
337 dev_kfree_skb_any(tx_buf->skb);
338 tx_buf->skb = NULL;
339 }
340
341 static void fe_clean_tx(struct fe_priv *priv)
342 {
343 int i;
344 struct device *dev = priv->dev;
345 struct fe_tx_ring *ring = &priv->tx_ring;
346
347 if (ring->tx_buf) {
348 for (i = 0; i < ring->tx_ring_size; i++)
349 fe_txd_unmap(dev, &ring->tx_buf[i]);
350 kfree(ring->tx_buf);
351 ring->tx_buf = NULL;
352 }
353
354 if (ring->tx_dma) {
355 dma_free_coherent(dev,
356 ring->tx_ring_size * sizeof(*ring->tx_dma),
357 ring->tx_dma,
358 ring->tx_phys);
359 ring->tx_dma = NULL;
360 }
361
362 netdev_reset_queue(priv->netdev);
363 }
364
365 static int fe_alloc_tx(struct fe_priv *priv)
366 {
367 int i;
368 struct fe_tx_ring *ring = &priv->tx_ring;
369
370 ring->tx_free_idx = 0;
371 ring->tx_next_idx = 0;
372 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
373 MAX_SKB_FRAGS);
374
375 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
376 GFP_KERNEL);
377 if (!ring->tx_buf)
378 goto no_tx_mem;
379
380 ring->tx_dma = dma_alloc_coherent(priv->dev,
381 ring->tx_ring_size * sizeof(*ring->tx_dma),
382 &ring->tx_phys,
383 GFP_ATOMIC | __GFP_ZERO);
384 if (!ring->tx_dma)
385 goto no_tx_mem;
386
387 for (i = 0; i < ring->tx_ring_size; i++) {
388 if (priv->soc->tx_dma)
389 priv->soc->tx_dma(&ring->tx_dma[i]);
390 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
391 }
392 /* make sure that all changes to the dma ring are flushed before we
393 * continue
394 */
395 wmb();
396
397 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
398 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
399 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
400 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
401
402 return 0;
403
404 no_tx_mem:
405 return -ENOMEM;
406 }
407
408 static int fe_init_dma(struct fe_priv *priv)
409 {
410 int err;
411
412 err = fe_alloc_tx(priv);
413 if (err)
414 return err;
415
416 err = fe_alloc_rx(priv);
417 if (err)
418 return err;
419
420 return 0;
421 }
422
423 static void fe_free_dma(struct fe_priv *priv)
424 {
425 fe_clean_tx(priv);
426 fe_clean_rx(priv);
427 }
428
429 void fe_stats_update(struct fe_priv *priv)
430 {
431 struct fe_hw_stats *hwstats = priv->hw_stats;
432 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
433 u64 stats;
434
435 u64_stats_update_begin(&hwstats->syncp);
436
437 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
438 hwstats->rx_bytes += fe_r32(base);
439 stats = fe_r32(base + 0x04);
440 if (stats)
441 hwstats->rx_bytes += (stats << 32);
442 hwstats->rx_packets += fe_r32(base + 0x08);
443 hwstats->rx_overflow += fe_r32(base + 0x10);
444 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
445 hwstats->rx_short_errors += fe_r32(base + 0x18);
446 hwstats->rx_long_errors += fe_r32(base + 0x1c);
447 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
448 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
449 hwstats->tx_skip += fe_r32(base + 0x28);
450 hwstats->tx_collisions += fe_r32(base + 0x2c);
451 hwstats->tx_bytes += fe_r32(base + 0x30);
452 stats = fe_r32(base + 0x34);
453 if (stats)
454 hwstats->tx_bytes += (stats << 32);
455 hwstats->tx_packets += fe_r32(base + 0x38);
456 } else {
457 hwstats->tx_bytes += fe_r32(base);
458 hwstats->tx_packets += fe_r32(base + 0x04);
459 hwstats->tx_skip += fe_r32(base + 0x08);
460 hwstats->tx_collisions += fe_r32(base + 0x0c);
461 hwstats->rx_bytes += fe_r32(base + 0x20);
462 hwstats->rx_packets += fe_r32(base + 0x24);
463 hwstats->rx_overflow += fe_r32(base + 0x28);
464 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
465 hwstats->rx_short_errors += fe_r32(base + 0x30);
466 hwstats->rx_long_errors += fe_r32(base + 0x34);
467 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
468 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
469 }
470
471 u64_stats_update_end(&hwstats->syncp);
472 }
473
474 static void fe_get_stats64(struct net_device *dev,
475 struct rtnl_link_stats64 *storage)
476 {
477 struct fe_priv *priv = netdev_priv(dev);
478 struct fe_hw_stats *hwstats = priv->hw_stats;
479 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
480 unsigned int start;
481
482 if (!base) {
483 netdev_stats_to_stats64(storage, &dev->stats);
484 return;
485 }
486
487 if (netif_running(dev) && netif_device_present(dev)) {
488 if (spin_trylock_bh(&hwstats->stats_lock)) {
489 fe_stats_update(priv);
490 spin_unlock_bh(&hwstats->stats_lock);
491 }
492 }
493
494 do {
495 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
496 storage->rx_packets = hwstats->rx_packets;
497 storage->tx_packets = hwstats->tx_packets;
498 storage->rx_bytes = hwstats->rx_bytes;
499 storage->tx_bytes = hwstats->tx_bytes;
500 storage->collisions = hwstats->tx_collisions;
501 storage->rx_length_errors = hwstats->rx_short_errors +
502 hwstats->rx_long_errors;
503 storage->rx_over_errors = hwstats->rx_overflow;
504 storage->rx_crc_errors = hwstats->rx_fcs_errors;
505 storage->rx_errors = hwstats->rx_checksum_errors;
506 storage->tx_aborted_errors = hwstats->tx_skip;
507 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
508
509 storage->tx_errors = priv->netdev->stats.tx_errors;
510 storage->rx_dropped = priv->netdev->stats.rx_dropped;
511 storage->tx_dropped = priv->netdev->stats.tx_dropped;
512 }
513
514 static int fe_vlan_rx_add_vid(struct net_device *dev,
515 __be16 proto, u16 vid)
516 {
517 struct fe_priv *priv = netdev_priv(dev);
518 u32 idx = (vid & 0xf);
519 u32 vlan_cfg;
520
521 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
522 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
523 return 0;
524
525 if (test_bit(idx, &priv->vlan_map)) {
526 netdev_warn(dev, "disable tx vlan offload\n");
527 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
528 netdev_update_features(dev);
529 } else {
530 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
531 ((idx >> 1) << 2));
532 if (idx & 0x1) {
533 vlan_cfg &= 0xffff;
534 vlan_cfg |= (vid << 16);
535 } else {
536 vlan_cfg &= 0xffff0000;
537 vlan_cfg |= vid;
538 }
539 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
540 ((idx >> 1) << 2));
541 set_bit(idx, &priv->vlan_map);
542 }
543
544 return 0;
545 }
546
547 static int fe_vlan_rx_kill_vid(struct net_device *dev,
548 __be16 proto, u16 vid)
549 {
550 struct fe_priv *priv = netdev_priv(dev);
551 u32 idx = (vid & 0xf);
552
553 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
554 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
555 return 0;
556
557 clear_bit(idx, &priv->vlan_map);
558
559 return 0;
560 }
561
562 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
563 {
564 barrier();
565 return (u32)(ring->tx_ring_size -
566 ((ring->tx_next_idx - ring->tx_free_idx) &
567 (ring->tx_ring_size - 1)));
568 }
569
570 struct fe_map_state {
571 struct device *dev;
572 struct fe_tx_dma txd;
573 u32 def_txd4;
574 int ring_idx;
575 int i;
576 };
577
578 static void fe_tx_dma_write_desc(struct fe_tx_ring *ring, struct fe_map_state *st)
579 {
580 fe_set_txd(&st->txd, &ring->tx_dma[st->ring_idx]);
581 memset(&st->txd, 0, sizeof(st->txd));
582 st->txd.txd4 = st->def_txd4;
583 st->ring_idx = NEXT_TX_DESP_IDX(st->ring_idx);
584 }
585
586 static int __fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,
587 struct page *page, size_t offset, size_t size)
588 {
589 struct device *dev = st->dev;
590 struct fe_tx_buf *tx_buf;
591 dma_addr_t mapped_addr;
592
593 mapped_addr = dma_map_page(dev, page, offset, size, DMA_TO_DEVICE);
594 if (unlikely(dma_mapping_error(dev, mapped_addr)))
595 return -EIO;
596
597 if (st->i && !(st->i & 1))
598 fe_tx_dma_write_desc(ring, st);
599
600 tx_buf = &ring->tx_buf[st->ring_idx];
601 if (st->i & 1) {
602 st->txd.txd3 = mapped_addr;
603 st->txd.txd2 |= TX_DMA_PLEN1(size);
604 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
605 dma_unmap_len_set(tx_buf, dma_len1, size);
606 } else {
607 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
608 st->txd.txd1 = mapped_addr;
609 st->txd.txd2 = TX_DMA_PLEN0(size);
610 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
611 dma_unmap_len_set(tx_buf, dma_len0, size);
612 }
613 st->i++;
614
615 return 0;
616 }
617
618 static int fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,
619 struct page *page, size_t offset, size_t size)
620 {
621 int cur_size;
622 int ret;
623
624 while (size > 0) {
625 cur_size = min_t(size_t, size, TX_DMA_BUF_LEN);
626
627 ret = __fe_tx_dma_map_page(ring, st, page, offset, cur_size);
628 if (ret)
629 return ret;
630
631 size -= cur_size;
632 offset += cur_size;
633 }
634
635 return 0;
636 }
637
638 static int fe_tx_dma_map_skb(struct fe_tx_ring *ring, struct fe_map_state *st,
639 struct sk_buff *skb)
640 {
641 struct page *page = virt_to_page(skb->data);
642 size_t offset = offset_in_page(skb->data);
643 size_t size = skb_headlen(skb);
644
645 return fe_tx_dma_map_page(ring, st, page, offset, size);
646 }
647
648 static inline struct sk_buff *
649 fe_next_frag(struct sk_buff *head, struct sk_buff *skb)
650 {
651 if (skb != head)
652 return skb->next;
653
654 if (skb_has_frag_list(skb))
655 return skb_shinfo(skb)->frag_list;
656
657 return NULL;
658 }
659
660
661 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
662 int tx_num, struct fe_tx_ring *ring)
663 {
664 struct fe_priv *priv = netdev_priv(dev);
665 struct fe_map_state st = {
666 .dev = priv->dev,
667 .ring_idx = ring->tx_next_idx,
668 };
669 struct sk_buff *head = skb;
670 struct fe_tx_buf *tx_buf;
671 unsigned int nr_frags;
672 int i, j;
673
674 /* init tx descriptor */
675 if (priv->soc->tx_dma)
676 priv->soc->tx_dma(&st.txd);
677 else
678 st.txd.txd4 = TX_DMA_DESP4_DEF;
679 st.def_txd4 = st.txd.txd4;
680
681 /* TX Checksum offload */
682 if (skb->ip_summed == CHECKSUM_PARTIAL)
683 st.txd.txd4 |= TX_DMA_CHKSUM;
684
685 /* VLAN header offload */
686 if (skb_vlan_tag_present(skb)) {
687 u16 tag = skb_vlan_tag_get(skb);
688
689 if (IS_ENABLED(CONFIG_SOC_MT7621))
690 st.txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
691 else
692 st.txd.txd4 |= TX_DMA_INS_VLAN |
693 ((tag >> VLAN_PRIO_SHIFT) << 4) |
694 (tag & 0xF);
695 }
696
697 /* TSO: fill MSS info in tcp checksum field */
698 if (skb_is_gso(skb)) {
699 if (skb_cow_head(skb, 0)) {
700 netif_warn(priv, tx_err, dev,
701 "GSO expand head fail.\n");
702 goto err_out;
703 }
704 if (skb_shinfo(skb)->gso_type &
705 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
706 st.txd.txd4 |= TX_DMA_TSO;
707 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
708 }
709 }
710
711 next_frag:
712 if (skb_headlen(skb) && fe_tx_dma_map_skb(ring, &st, skb))
713 goto err_dma;
714
715 /* TX SG offload */
716 nr_frags = skb_shinfo(skb)->nr_frags;
717 for (i = 0; i < nr_frags; i++) {
718 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
719 struct skb_frag_struct *frag;
720 #else
721 skb_frag_t *frag;
722 #endif
723
724 frag = &skb_shinfo(skb)->frags[i];
725 if (fe_tx_dma_map_page(ring, &st, skb_frag_page(frag),
726 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
727 frag->page_offset, skb_frag_size(frag)))
728 #else
729 skb_frag_off(frag), skb_frag_size(frag)))
730 #endif
731 goto err_dma;
732 }
733
734 skb = fe_next_frag(head, skb);
735 if (skb)
736 goto next_frag;
737
738 /* set last segment */
739 if (st.i & 0x1)
740 st.txd.txd2 |= TX_DMA_LS0;
741 else
742 st.txd.txd2 |= TX_DMA_LS1;
743
744 /* store skb to cleanup */
745 tx_buf = &ring->tx_buf[st.ring_idx];
746 tx_buf->skb = head;
747
748 netdev_sent_queue(dev, head->len);
749 skb_tx_timestamp(head);
750
751 fe_tx_dma_write_desc(ring, &st);
752 ring->tx_next_idx = st.ring_idx;
753
754 /* make sure that all changes to the dma ring are flushed before we
755 * continue
756 */
757 wmb();
758 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
759 netif_stop_queue(dev);
760 smp_mb();
761 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
762 netif_wake_queue(dev);
763 }
764
765 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)
766 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !head->xmit_more)
767 #else
768 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !netdev_xmit_more())
769 #endif
770 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
771
772 return 0;
773
774 err_dma:
775 j = ring->tx_next_idx;
776 for (i = 0; i < tx_num; i++) {
777 /* unmap dma */
778 fe_txd_unmap(priv->dev, &ring->tx_buf[j]);
779 ring->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
780
781 j = NEXT_TX_DESP_IDX(j);
782 }
783 /* make sure that all changes to the dma ring are flushed before we
784 * continue
785 */
786 wmb();
787
788 err_out:
789 return -1;
790 }
791
792 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
793 {
794 unsigned int len;
795 int ret;
796
797 ret = 0;
798 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
799 if ((priv->flags & FE_FLAG_PADDING_64B) &&
800 !(priv->flags & FE_FLAG_PADDING_BUG))
801 return ret;
802
803 if (skb_vlan_tag_present(skb))
804 len = ETH_ZLEN;
805 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
806 len = VLAN_ETH_ZLEN;
807 else if (!(priv->flags & FE_FLAG_PADDING_64B))
808 len = ETH_ZLEN;
809 else
810 return ret;
811
812 if (skb->len < len) {
813 ret = skb_pad(skb, len - skb->len);
814 if (ret < 0)
815 return ret;
816 skb->len = len;
817 skb_set_tail_pointer(skb, len);
818 }
819 }
820
821 return ret;
822 }
823
824 static inline int fe_cal_txd_req(struct sk_buff *skb)
825 {
826 struct sk_buff *head = skb;
827 int i, nfrags = 0;
828 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
829 struct skb_frag_struct *frag;
830 #else
831 skb_frag_t *frag;
832 #endif
833
834 next_frag:
835 nfrags++;
836 if (skb_is_gso(skb)) {
837 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
838 frag = &skb_shinfo(skb)->frags[i];
839 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)
840 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
841 #else
842 nfrags += DIV_ROUND_UP(skb_frag_size(frag), TX_DMA_BUF_LEN);
843 #endif
844 }
845 } else {
846 nfrags += skb_shinfo(skb)->nr_frags;
847 }
848
849 skb = fe_next_frag(head, skb);
850 if (skb)
851 goto next_frag;
852
853 return DIV_ROUND_UP(nfrags, 2);
854 }
855
856 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
857 {
858 struct fe_priv *priv = netdev_priv(dev);
859 struct fe_tx_ring *ring = &priv->tx_ring;
860 struct net_device_stats *stats = &dev->stats;
861 int tx_num;
862 int len = skb->len;
863
864 if (fe_skb_padto(skb, priv)) {
865 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
866 return NETDEV_TX_OK;
867 }
868
869 tx_num = fe_cal_txd_req(skb);
870 if (unlikely(fe_empty_txd(ring) <= tx_num)) {
871 netif_stop_queue(dev);
872 netif_err(priv, tx_queued, dev,
873 "Tx Ring full when queue awake!\n");
874 return NETDEV_TX_BUSY;
875 }
876
877 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
878 stats->tx_dropped++;
879 } else {
880 stats->tx_packets++;
881 stats->tx_bytes += len;
882 }
883
884 return NETDEV_TX_OK;
885 }
886
887 static int fe_poll_rx(struct napi_struct *napi, int budget,
888 struct fe_priv *priv, u32 rx_intr)
889 {
890 struct net_device *netdev = priv->netdev;
891 struct net_device_stats *stats = &netdev->stats;
892 struct fe_soc_data *soc = priv->soc;
893 struct fe_rx_ring *ring = &priv->rx_ring;
894 int idx = ring->rx_calc_idx;
895 u32 checksum_bit;
896 struct sk_buff *skb;
897 u8 *data, *new_data;
898 struct fe_rx_dma *rxd, trxd;
899 int done = 0, pad;
900
901 if (netdev->features & NETIF_F_RXCSUM)
902 checksum_bit = soc->checksum_bit;
903 else
904 checksum_bit = 0;
905
906 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
907 pad = 0;
908 else
909 pad = NET_IP_ALIGN;
910
911 while (done < budget) {
912 unsigned int pktlen;
913 dma_addr_t dma_addr;
914
915 idx = NEXT_RX_DESP_IDX(idx);
916 rxd = &ring->rx_dma[idx];
917 data = ring->rx_data[idx];
918
919 fe_get_rxd(&trxd, rxd);
920 if (!(trxd.rxd2 & RX_DMA_DONE))
921 break;
922
923 /* alloc new buffer */
924 new_data = page_frag_alloc(&ring->frag_cache, ring->frag_size,
925 GFP_ATOMIC);
926 if (unlikely(!new_data)) {
927 stats->rx_dropped++;
928 goto release_desc;
929 }
930 dma_addr = dma_map_single(priv->dev,
931 new_data + NET_SKB_PAD + pad,
932 ring->rx_buf_size,
933 DMA_FROM_DEVICE);
934 if (unlikely(dma_mapping_error(priv->dev, dma_addr))) {
935 skb_free_frag(new_data);
936 goto release_desc;
937 }
938
939 /* receive data */
940 skb = build_skb(data, ring->frag_size);
941 if (unlikely(!skb)) {
942 skb_free_frag(new_data);
943 goto release_desc;
944 }
945 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
946
947 dma_unmap_single(priv->dev, trxd.rxd1,
948 ring->rx_buf_size, DMA_FROM_DEVICE);
949 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
950 skb->dev = netdev;
951 skb_put(skb, pktlen);
952 if (trxd.rxd4 & checksum_bit)
953 skb->ip_summed = CHECKSUM_UNNECESSARY;
954 else
955 skb_checksum_none_assert(skb);
956 skb->protocol = eth_type_trans(skb, netdev);
957
958 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
959 RX_DMA_VID(trxd.rxd3))
960 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
961 RX_DMA_VID(trxd.rxd3));
962
963 #ifdef CONFIG_NET_RALINK_OFFLOAD
964 if (mtk_offload_check_rx(priv, skb, trxd.rxd4) == 0) {
965 #endif
966 stats->rx_packets++;
967 stats->rx_bytes += pktlen;
968
969 napi_gro_receive(napi, skb);
970 #ifdef CONFIG_NET_RALINK_OFFLOAD
971 } else {
972 dev_kfree_skb(skb);
973 }
974 #endif
975 ring->rx_data[idx] = new_data;
976 rxd->rxd1 = (unsigned int)dma_addr;
977
978 release_desc:
979 if (priv->flags & FE_FLAG_RX_SG_DMA)
980 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
981 else
982 rxd->rxd2 = RX_DMA_LSO;
983
984 ring->rx_calc_idx = idx;
985 /* make sure that all changes to the dma ring are flushed before
986 * we continue
987 */
988 wmb();
989 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
990 done++;
991 }
992
993 if (done < budget)
994 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
995
996 return done;
997 }
998
999 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
1000 int *tx_again)
1001 {
1002 struct net_device *netdev = priv->netdev;
1003 unsigned int bytes_compl = 0;
1004 struct sk_buff *skb;
1005 struct fe_tx_buf *tx_buf;
1006 int done = 0;
1007 u32 idx, hwidx;
1008 struct fe_tx_ring *ring = &priv->tx_ring;
1009
1010 idx = ring->tx_free_idx;
1011 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
1012
1013 while ((idx != hwidx) && budget) {
1014 tx_buf = &ring->tx_buf[idx];
1015 skb = tx_buf->skb;
1016
1017 if (!skb)
1018 break;
1019
1020 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
1021 bytes_compl += skb->len;
1022 done++;
1023 budget--;
1024 }
1025 fe_txd_unmap(priv->dev, tx_buf);
1026 idx = NEXT_TX_DESP_IDX(idx);
1027 }
1028 ring->tx_free_idx = idx;
1029
1030 if (idx == hwidx) {
1031 /* read hw index again make sure no new tx packet */
1032 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
1033 if (idx == hwidx)
1034 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
1035 else
1036 *tx_again = 1;
1037 } else {
1038 *tx_again = 1;
1039 }
1040
1041 if (done) {
1042 netdev_completed_queue(netdev, done, bytes_compl);
1043 smp_mb();
1044 if (unlikely(netif_queue_stopped(netdev) &&
1045 (fe_empty_txd(ring) > ring->tx_thresh)))
1046 netif_wake_queue(netdev);
1047 }
1048
1049 return done;
1050 }
1051
1052 static int fe_poll(struct napi_struct *napi, int budget)
1053 {
1054 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
1055 struct fe_hw_stats *hwstat = priv->hw_stats;
1056 int tx_done, rx_done, tx_again;
1057 u32 status, fe_status, status_reg, mask;
1058 u32 tx_intr, rx_intr, status_intr;
1059
1060 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1061 fe_status = status;
1062 tx_intr = priv->soc->tx_int;
1063 rx_intr = priv->soc->rx_int;
1064 status_intr = priv->soc->status_int;
1065 tx_done = 0;
1066 rx_done = 0;
1067 tx_again = 0;
1068
1069 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
1070 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
1071 status_reg = FE_REG_FE_INT_STATUS2;
1072 } else {
1073 status_reg = FE_REG_FE_INT_STATUS;
1074 }
1075
1076 if (status & tx_intr)
1077 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
1078
1079 if (status & rx_intr)
1080 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
1081
1082 if (unlikely(fe_status & status_intr)) {
1083 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
1084 fe_stats_update(priv);
1085 spin_unlock(&hwstat->stats_lock);
1086 }
1087 fe_reg_w32(status_intr, status_reg);
1088 }
1089
1090 if (unlikely(netif_msg_intr(priv))) {
1091 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
1092 netdev_info(priv->netdev,
1093 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1094 tx_done, rx_done, status, mask);
1095 }
1096
1097 if (!tx_again && (rx_done < budget)) {
1098 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1099 if (status & (tx_intr | rx_intr)) {
1100 /* let napi poll again */
1101 rx_done = budget;
1102 goto poll_again;
1103 }
1104
1105 napi_complete_done(napi, rx_done);
1106 fe_int_enable(tx_intr | rx_intr);
1107 } else {
1108 rx_done = budget;
1109 }
1110
1111 poll_again:
1112 return rx_done;
1113 }
1114
1115 static void fe_tx_timeout(struct net_device *dev)
1116 {
1117 struct fe_priv *priv = netdev_priv(dev);
1118 struct fe_tx_ring *ring = &priv->tx_ring;
1119
1120 priv->netdev->stats.tx_errors++;
1121 netif_err(priv, tx_err, dev,
1122 "transmit timed out\n");
1123 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1124 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1125 netif_info(priv, drv, dev, "tx_ring=%d, "
1126 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1127 0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1128 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1129 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1130 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1131 ring->tx_free_idx,
1132 ring->tx_next_idx);
1133 netif_info(priv, drv, dev,
1134 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1135 0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1136 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1137 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1138 fe_reg_r32(FE_REG_RX_DRX_IDX0));
1139
1140 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1141 schedule_work(&priv->pending_work);
1142 }
1143
1144 static irqreturn_t fe_handle_irq(int irq, void *dev)
1145 {
1146 struct fe_priv *priv = netdev_priv(dev);
1147 u32 status, int_mask;
1148
1149 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1150
1151 if (unlikely(!status))
1152 return IRQ_NONE;
1153
1154 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1155 if (likely(status & int_mask)) {
1156 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1157 fe_int_disable(int_mask);
1158 __napi_schedule(&priv->rx_napi);
1159 }
1160 } else {
1161 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1162 }
1163
1164 return IRQ_HANDLED;
1165 }
1166
1167 #ifdef CONFIG_NET_POLL_CONTROLLER
1168 static void fe_poll_controller(struct net_device *dev)
1169 {
1170 struct fe_priv *priv = netdev_priv(dev);
1171 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1172
1173 fe_int_disable(int_mask);
1174 fe_handle_irq(dev->irq, dev);
1175 fe_int_enable(int_mask);
1176 }
1177 #endif
1178
1179 int fe_set_clock_cycle(struct fe_priv *priv)
1180 {
1181 unsigned long sysclk = priv->sysclk;
1182
1183 sysclk /= FE_US_CYC_CNT_DIVISOR;
1184 sysclk <<= FE_US_CYC_CNT_SHIFT;
1185
1186 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1187 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1188 sysclk,
1189 FE_FE_GLO_CFG);
1190 return 0;
1191 }
1192
1193 void fe_fwd_config(struct fe_priv *priv)
1194 {
1195 u32 fwd_cfg;
1196
1197 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1198
1199 /* disable jumbo frame */
1200 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1201 fwd_cfg &= ~FE_GDM1_JMB_EN;
1202
1203 /* set unicast/multicast/broadcast frame to cpu */
1204 fwd_cfg &= ~0xffff;
1205
1206 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1207 }
1208
1209 static void fe_rxcsum_config(bool enable)
1210 {
1211 if (enable)
1212 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1213 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1214 FE_GDMA1_FWD_CFG);
1215 else
1216 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1217 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1218 FE_GDMA1_FWD_CFG);
1219 }
1220
1221 static void fe_txcsum_config(bool enable)
1222 {
1223 if (enable)
1224 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1225 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1226 FE_CDMA_CSG_CFG);
1227 else
1228 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1229 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1230 FE_CDMA_CSG_CFG);
1231 }
1232
1233 void fe_csum_config(struct fe_priv *priv)
1234 {
1235 struct net_device *dev = priv_netdev(priv);
1236
1237 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1238 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1239 }
1240
1241 static int fe_hw_init(struct net_device *dev)
1242 {
1243 struct fe_priv *priv = netdev_priv(dev);
1244 int i, err;
1245
1246 err = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0,
1247 dev_name(priv->dev), dev);
1248 if (err)
1249 return err;
1250
1251 if (priv->soc->set_mac)
1252 priv->soc->set_mac(priv, dev->dev_addr);
1253 else
1254 fe_hw_set_macaddr(priv, dev->dev_addr);
1255
1256 /* disable delay interrupt */
1257 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1258
1259 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1260
1261 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1262 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1263 for (i = 0; i < 16; i += 2)
1264 fe_w32(((i + 1) << 16) + i,
1265 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1266 (i * 2));
1267
1268 if (priv->soc->fwd_config(priv))
1269 netdev_err(dev, "unable to get clock\n");
1270
1271 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1272 fe_reg_w32(1, FE_REG_FE_RST_GL);
1273 fe_reg_w32(0, FE_REG_FE_RST_GL);
1274 }
1275
1276 return 0;
1277 }
1278
1279 static int fe_open(struct net_device *dev)
1280 {
1281 struct fe_priv *priv = netdev_priv(dev);
1282 unsigned long flags;
1283 u32 val;
1284 int err;
1285
1286 err = fe_init_dma(priv);
1287 if (err) {
1288 fe_free_dma(priv);
1289 return err;
1290 }
1291
1292 spin_lock_irqsave(&priv->page_lock, flags);
1293
1294 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1295 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1296 val |= FE_RX_2B_OFFSET;
1297 val |= priv->soc->pdma_glo_cfg;
1298 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1299
1300 spin_unlock_irqrestore(&priv->page_lock, flags);
1301
1302 if (priv->phy)
1303 priv->phy->start(priv);
1304
1305 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1306 netif_carrier_on(dev);
1307
1308 napi_enable(&priv->rx_napi);
1309 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1310 netif_start_queue(dev);
1311 #ifdef CONFIG_NET_RALINK_OFFLOAD
1312 mtk_ppe_probe(priv);
1313 #endif
1314
1315 return 0;
1316 }
1317
1318 static int fe_stop(struct net_device *dev)
1319 {
1320 struct fe_priv *priv = netdev_priv(dev);
1321 unsigned long flags;
1322 int i;
1323
1324 netif_tx_disable(dev);
1325 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1326 napi_disable(&priv->rx_napi);
1327
1328 if (priv->phy)
1329 priv->phy->stop(priv);
1330
1331 spin_lock_irqsave(&priv->page_lock, flags);
1332
1333 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1334 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1335 FE_REG_PDMA_GLO_CFG);
1336 spin_unlock_irqrestore(&priv->page_lock, flags);
1337
1338 /* wait dma stop */
1339 for (i = 0; i < 10; i++) {
1340 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1341 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1342 msleep(20);
1343 continue;
1344 }
1345 break;
1346 }
1347
1348 fe_free_dma(priv);
1349
1350 #ifdef CONFIG_NET_RALINK_OFFLOAD
1351 mtk_ppe_remove(priv);
1352 #endif
1353
1354 return 0;
1355 }
1356
1357 static void fe_reset_phy(struct fe_priv *priv)
1358 {
1359 int err, msec = 30;
1360 struct gpio_desc *phy_reset;
1361
1362 phy_reset = devm_gpiod_get_optional(priv->dev, "phy-reset",
1363 GPIOD_OUT_HIGH);
1364 if (!phy_reset)
1365 return;
1366
1367 if (IS_ERR(phy_reset)) {
1368 dev_err(priv->dev, "Error acquiring reset gpio pins: %ld\n",
1369 PTR_ERR(phy_reset));
1370 return;
1371 }
1372
1373 err = of_property_read_u32(priv->dev->of_node, "phy-reset-duration",
1374 &msec);
1375 if (!err && msec > 1000)
1376 msec = 30;
1377
1378 if (msec > 20)
1379 msleep(msec);
1380 else
1381 usleep_range(msec * 1000, msec * 1000 + 1000);
1382
1383 gpiod_set_value(phy_reset, 0);
1384 }
1385
1386 static int __init fe_init(struct net_device *dev)
1387 {
1388 struct fe_priv *priv = netdev_priv(dev);
1389 struct device_node *port;
1390 const char *mac_addr;
1391 int err;
1392
1393 priv->soc->reset_fe();
1394
1395 if (priv->soc->switch_init)
1396 if (priv->soc->switch_init(priv)) {
1397 netdev_err(dev, "failed to initialize switch core\n");
1398 return -ENODEV;
1399 }
1400
1401 fe_reset_phy(priv);
1402
1403 mac_addr = of_get_mac_address(priv->dev->of_node);
1404 if (!IS_ERR_OR_NULL(mac_addr))
1405 ether_addr_copy(dev->dev_addr, mac_addr);
1406
1407 /* If the mac address is invalid, use random mac address */
1408 if (!is_valid_ether_addr(dev->dev_addr)) {
1409 eth_hw_addr_random(dev);
1410 dev_err(priv->dev, "generated random MAC address %pM\n",
1411 dev->dev_addr);
1412 }
1413
1414 err = fe_mdio_init(priv);
1415 if (err)
1416 return err;
1417
1418 if (priv->soc->port_init)
1419 for_each_child_of_node(priv->dev->of_node, port)
1420 if (of_device_is_compatible(port, "mediatek,eth-port") &&
1421 of_device_is_available(port))
1422 priv->soc->port_init(priv, port);
1423
1424 if (priv->phy) {
1425 err = priv->phy->connect(priv);
1426 if (err)
1427 goto err_phy_disconnect;
1428 }
1429
1430 err = fe_hw_init(dev);
1431 if (err)
1432 goto err_phy_disconnect;
1433
1434 if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1435 priv->soc->switch_config(priv);
1436
1437 return 0;
1438
1439 err_phy_disconnect:
1440 if (priv->phy)
1441 priv->phy->disconnect(priv);
1442 fe_mdio_cleanup(priv);
1443
1444 return err;
1445 }
1446
1447 static void fe_uninit(struct net_device *dev)
1448 {
1449 struct fe_priv *priv = netdev_priv(dev);
1450
1451 if (priv->phy)
1452 priv->phy->disconnect(priv);
1453 fe_mdio_cleanup(priv);
1454
1455 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1456 free_irq(dev->irq, dev);
1457 }
1458
1459 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1460 {
1461 struct fe_priv *priv = netdev_priv(dev);
1462
1463 if (!priv->phy_dev)
1464 return -ENODEV;
1465
1466
1467 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1468 }
1469
1470 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1471 {
1472 struct fe_priv *priv = netdev_priv(dev);
1473 int frag_size, old_mtu;
1474 u32 fwd_cfg;
1475
1476 old_mtu = dev->mtu;
1477 dev->mtu = new_mtu;
1478
1479 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1480 return 0;
1481
1482 /* return early if the buffer sizes will not change */
1483 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1484 return 0;
1485 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1486 return 0;
1487
1488 if (new_mtu <= ETH_DATA_LEN)
1489 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1490 else
1491 priv->rx_ring.frag_size = PAGE_SIZE;
1492 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1493
1494 if (!netif_running(dev))
1495 return 0;
1496
1497 fe_stop(dev);
1498 if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
1499 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1500 if (new_mtu <= ETH_DATA_LEN) {
1501 fwd_cfg &= ~FE_GDM1_JMB_EN;
1502 } else {
1503 frag_size = fe_max_frag_size(new_mtu);
1504 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1505 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1506 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1507 }
1508 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1509 }
1510
1511 return fe_open(dev);
1512 }
1513
1514 #ifdef CONFIG_NET_RALINK_OFFLOAD
1515 static int
1516 fe_flow_offload(enum flow_offload_type type, struct flow_offload *flow,
1517 struct flow_offload_hw_path *src,
1518 struct flow_offload_hw_path *dest)
1519 {
1520 struct fe_priv *priv;
1521
1522 if (src->dev != dest->dev)
1523 return -EINVAL;
1524
1525 priv = netdev_priv(src->dev);
1526
1527 return mtk_flow_offload(priv, type, flow, src, dest);
1528 }
1529 #endif
1530
1531 static const struct net_device_ops fe_netdev_ops = {
1532 .ndo_init = fe_init,
1533 .ndo_uninit = fe_uninit,
1534 .ndo_open = fe_open,
1535 .ndo_stop = fe_stop,
1536 .ndo_start_xmit = fe_start_xmit,
1537 .ndo_set_mac_address = fe_set_mac_address,
1538 .ndo_validate_addr = eth_validate_addr,
1539 .ndo_do_ioctl = fe_do_ioctl,
1540 .ndo_change_mtu = fe_change_mtu,
1541 .ndo_tx_timeout = fe_tx_timeout,
1542 .ndo_get_stats64 = fe_get_stats64,
1543 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1544 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1545 #ifdef CONFIG_NET_POLL_CONTROLLER
1546 .ndo_poll_controller = fe_poll_controller,
1547 #endif
1548 #ifdef CONFIG_NET_RALINK_OFFLOAD
1549 .ndo_flow_offload = fe_flow_offload,
1550 #endif
1551 };
1552
1553 static void fe_reset_pending(struct fe_priv *priv)
1554 {
1555 struct net_device *dev = priv->netdev;
1556 int err;
1557
1558 rtnl_lock();
1559 fe_stop(dev);
1560
1561 err = fe_open(dev);
1562 if (err) {
1563 netif_alert(priv, ifup, dev,
1564 "Driver up/down cycle failed, closing device.\n");
1565 dev_close(dev);
1566 }
1567 rtnl_unlock();
1568 }
1569
1570 static const struct fe_work_t fe_work[] = {
1571 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1572 };
1573
1574 static void fe_pending_work(struct work_struct *work)
1575 {
1576 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1577 int i;
1578 bool pending;
1579
1580 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1581 pending = test_and_clear_bit(fe_work[i].bitnr,
1582 priv->pending_flags);
1583 if (pending)
1584 fe_work[i].action(priv);
1585 }
1586 }
1587
1588 static int fe_probe(struct platform_device *pdev)
1589 {
1590 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1591 const struct of_device_id *match;
1592 struct fe_soc_data *soc;
1593 struct net_device *netdev;
1594 struct fe_priv *priv;
1595 struct clk *sysclk;
1596 int err, napi_weight;
1597
1598 device_reset(&pdev->dev);
1599
1600 match = of_match_device(of_fe_match, &pdev->dev);
1601 soc = (struct fe_soc_data *)match->data;
1602
1603 if (soc->reg_table)
1604 fe_reg_table = soc->reg_table;
1605 else
1606 soc->reg_table = fe_reg_table;
1607
1608 fe_base = devm_ioremap_resource(&pdev->dev, res);
1609 if (IS_ERR(fe_base)) {
1610 err = -EADDRNOTAVAIL;
1611 goto err_out;
1612 }
1613
1614 netdev = alloc_etherdev(sizeof(*priv));
1615 if (!netdev) {
1616 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1617 err = -ENOMEM;
1618 goto err_iounmap;
1619 }
1620
1621 SET_NETDEV_DEV(netdev, &pdev->dev);
1622 netdev->netdev_ops = &fe_netdev_ops;
1623 netdev->base_addr = (unsigned long)fe_base;
1624
1625 netdev->irq = platform_get_irq(pdev, 0);
1626 if (netdev->irq < 0) {
1627 dev_err(&pdev->dev, "no IRQ resource found\n");
1628 err = -ENXIO;
1629 goto err_free_dev;
1630 }
1631
1632 if (soc->init_data)
1633 soc->init_data(soc, netdev);
1634 netdev->vlan_features = netdev->hw_features &
1635 ~(NETIF_F_HW_VLAN_CTAG_TX |
1636 NETIF_F_HW_VLAN_CTAG_RX);
1637 netdev->features |= netdev->hw_features;
1638
1639 if (IS_ENABLED(CONFIG_SOC_MT7621))
1640 netdev->max_mtu = 2048;
1641
1642 /* fake rx vlan filter func. to support tx vlan offload func */
1643 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1644 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1645
1646 priv = netdev_priv(netdev);
1647 spin_lock_init(&priv->page_lock);
1648 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1649 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1650 if (!priv->hw_stats) {
1651 err = -ENOMEM;
1652 goto err_free_dev;
1653 }
1654 spin_lock_init(&priv->hw_stats->stats_lock);
1655 }
1656
1657 sysclk = devm_clk_get(&pdev->dev, NULL);
1658 if (!IS_ERR(sysclk)) {
1659 priv->sysclk = clk_get_rate(sysclk);
1660 } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
1661 dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
1662 err = -ENXIO;
1663 goto err_free_dev;
1664 }
1665
1666 priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
1667 if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
1668 dev_err(&pdev->dev, "failed to read switch phandle\n");
1669 err = -ENODEV;
1670 goto err_free_dev;
1671 }
1672
1673 priv->netdev = netdev;
1674 priv->dev = &pdev->dev;
1675 priv->soc = soc;
1676 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1677 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1678 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1679 priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
1680 priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1681 INIT_WORK(&priv->pending_work, fe_pending_work);
1682 u64_stats_init(&priv->hw_stats->syncp);
1683
1684 napi_weight = 16;
1685 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1686 napi_weight *= 4;
1687 priv->tx_ring.tx_ring_size *= 4;
1688 priv->rx_ring.rx_ring_size *= 4;
1689 }
1690 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1691 fe_set_ethtool_ops(netdev);
1692
1693 err = register_netdev(netdev);
1694 if (err) {
1695 dev_err(&pdev->dev, "error bringing up device\n");
1696 goto err_free_dev;
1697 }
1698
1699 platform_set_drvdata(pdev, netdev);
1700
1701 netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
1702 netdev->base_addr, netdev->irq);
1703
1704 return 0;
1705
1706 err_free_dev:
1707 free_netdev(netdev);
1708 err_iounmap:
1709 devm_iounmap(&pdev->dev, fe_base);
1710 err_out:
1711 return err;
1712 }
1713
1714 static int fe_remove(struct platform_device *pdev)
1715 {
1716 struct net_device *dev = platform_get_drvdata(pdev);
1717 struct fe_priv *priv = netdev_priv(dev);
1718
1719 netif_napi_del(&priv->rx_napi);
1720 kfree(priv->hw_stats);
1721
1722 cancel_work_sync(&priv->pending_work);
1723
1724 unregister_netdev(dev);
1725 free_netdev(dev);
1726 platform_set_drvdata(pdev, NULL);
1727
1728 return 0;
1729 }
1730
1731 static struct platform_driver fe_driver = {
1732 .probe = fe_probe,
1733 .remove = fe_remove,
1734 .driver = {
1735 .name = "mtk_soc_eth",
1736 .owner = THIS_MODULE,
1737 .of_match_table = of_fe_match,
1738 },
1739 };
1740
1741 module_platform_driver(fe_driver);
1742
1743 MODULE_LICENSE("GPL");
1744 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1745 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1746 MODULE_VERSION(MTK_FE_DRV_VERSION);