projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
uclient: update to Git HEAD (2024-04-19)
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
31 #include <linux/io.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35 #include <linux/of_gpio.h>
36 #include <linux/gpio.h>
37 #include <linux/gpio/consumer.h>
38
39 #include <asm/mach-ralink/ralink_regs.h>
40
41 #include "mtk_eth_soc.h"
42 #include "mdio.h"
43 #include "ethtool.h"
44
45 #define MAX_RX_LENGTH 1536
46 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
47 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
76 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
77 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
78 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
79 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
80 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
81 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
82 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
83 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
84 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
85 };
86
87 static const u16 *fe_reg_table = fe_reg_table_default;
88
89 struct fe_work_t {
90 int bitnr;
91 void (*action)(struct fe_priv *);
92 };
93
94 static void __iomem *fe_base;
95
96 void fe_w32(u32 val, unsigned reg)
97 {
98 __raw_writel(val, fe_base + reg);
99 }
100
101 u32 fe_r32(unsigned reg)
102 {
103 return __raw_readl(fe_base + reg);
104 }
105
106 void fe_reg_w32(u32 val, enum fe_reg reg)
107 {
108 fe_w32(val, fe_reg_table[reg]);
109 }
110
111 u32 fe_reg_r32(enum fe_reg reg)
112 {
113 return fe_r32(fe_reg_table[reg]);
114 }
115
116 void fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg)
117 {
118 u32 val;
119
120 spin_lock(&eth->page_lock);
121 val = __raw_readl(fe_base + reg);
122 val &= ~clear;
123 val |= set;
124 __raw_writel(val, fe_base + reg);
125 spin_unlock(&eth->page_lock);
126 }
127
128 static void fe_reset_fe(struct fe_priv *priv)
129 {
130 if (!priv->resets)
131 return;
132
133 reset_control_assert(priv->resets);
134 usleep_range(60, 120);
135 reset_control_deassert(priv->resets);
136 usleep_range(1000, 1200);
137 }
138
139 static inline void fe_int_disable(u32 mask)
140 {
141 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
142 FE_REG_FE_INT_ENABLE);
143 /* flush write */
144 fe_reg_r32(FE_REG_FE_INT_ENABLE);
145 }
146
147 static inline void fe_int_enable(u32 mask)
148 {
149 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
150 FE_REG_FE_INT_ENABLE);
151 /* flush write */
152 fe_reg_r32(FE_REG_FE_INT_ENABLE);
153 }
154
155 static inline void fe_hw_set_macaddr(struct fe_priv *priv, const unsigned char *mac)
156 {
157 unsigned long flags;
158
159 spin_lock_irqsave(&priv->page_lock, flags);
160 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
161 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
162 FE_GDMA1_MAC_ADRL);
163 spin_unlock_irqrestore(&priv->page_lock, flags);
164 }
165
166 static int fe_set_mac_address(struct net_device *dev, void *p)
167 {
168 int ret = eth_mac_addr(dev, p);
169
170 if (!ret) {
171 struct fe_priv *priv = netdev_priv(dev);
172
173 if (priv->soc->set_mac)
174 priv->soc->set_mac(priv, dev->dev_addr);
175 else
176 fe_hw_set_macaddr(priv, p);
177 }
178
179 return ret;
180 }
181
182 static inline int fe_max_frag_size(int mtu)
183 {
184 /* make sure buf_size will be at least MAX_RX_LENGTH */
185 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
186 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
187
188 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
189 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
190 }
191
192 static inline int fe_max_buf_size(int frag_size)
193 {
194 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
195 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
196
197 BUG_ON(buf_size < MAX_RX_LENGTH);
198 return buf_size;
199 }
200
201 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
202 {
203 rxd->rxd1 = dma_rxd->rxd1;
204 rxd->rxd2 = dma_rxd->rxd2;
205 rxd->rxd3 = dma_rxd->rxd3;
206 rxd->rxd4 = dma_rxd->rxd4;
207 }
208
209 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
210 {
211 dma_txd->txd1 = txd->txd1;
212 dma_txd->txd3 = txd->txd3;
213 dma_txd->txd4 = txd->txd4;
214 /* clean dma done flag last */
215 dma_txd->txd2 = txd->txd2;
216 }
217
218 static void fe_clean_rx(struct fe_priv *priv)
219 {
220 struct fe_rx_ring *ring = &priv->rx_ring;
221 struct page *page;
222 int i;
223
224 if (ring->rx_data) {
225 for (i = 0; i < ring->rx_ring_size; i++)
226 if (ring->rx_data[i]) {
227 if (ring->rx_dma && ring->rx_dma[i].rxd1)
228 dma_unmap_single(priv->dev,
229 ring->rx_dma[i].rxd1,
230 ring->rx_buf_size,
231 DMA_FROM_DEVICE);
232 skb_free_frag(ring->rx_data[i]);
233 }
234
235 kfree(ring->rx_data);
236 ring->rx_data = NULL;
237 }
238
239 if (ring->rx_dma) {
240 dma_free_coherent(priv->dev,
241 ring->rx_ring_size * sizeof(*ring->rx_dma),
242 ring->rx_dma,
243 ring->rx_phys);
244 ring->rx_dma = NULL;
245 }
246
247 if (!ring->frag_cache.va)
248 return;
249
250 page = virt_to_page(ring->frag_cache.va);
251 __page_frag_cache_drain(page, ring->frag_cache.pagecnt_bias);
252 memset(&ring->frag_cache, 0, sizeof(ring->frag_cache));
253 }
254
255 static int fe_alloc_rx(struct fe_priv *priv)
256 {
257 struct fe_rx_ring *ring = &priv->rx_ring;
258 int i, pad;
259
260 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
261 GFP_KERNEL);
262 if (!ring->rx_data)
263 goto no_rx_mem;
264
265 for (i = 0; i < ring->rx_ring_size; i++) {
266 ring->rx_data[i] = page_frag_alloc(&ring->frag_cache,
267 ring->frag_size,
268 GFP_KERNEL);
269 if (!ring->rx_data[i])
270 goto no_rx_mem;
271 }
272
273 ring->rx_dma = dma_alloc_coherent(priv->dev,
274 ring->rx_ring_size * sizeof(*ring->rx_dma),
275 &ring->rx_phys,
276 GFP_ATOMIC | __GFP_ZERO);
277 if (!ring->rx_dma)
278 goto no_rx_mem;
279
280 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
281 pad = 0;
282 else
283 pad = NET_IP_ALIGN;
284 for (i = 0; i < ring->rx_ring_size; i++) {
285 dma_addr_t dma_addr = dma_map_single(priv->dev,
286 ring->rx_data[i] + NET_SKB_PAD + pad,
287 ring->rx_buf_size,
288 DMA_FROM_DEVICE);
289 if (unlikely(dma_mapping_error(priv->dev, dma_addr)))
290 goto no_rx_mem;
291 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
292
293 if (priv->flags & FE_FLAG_RX_SG_DMA)
294 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
295 else
296 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
297 }
298 ring->rx_calc_idx = ring->rx_ring_size - 1;
299 /* make sure that all changes to the dma ring are flushed before we
300 * continue
301 */
302 wmb();
303
304 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
305 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
306 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
307 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
308
309 return 0;
310
311 no_rx_mem:
312 return -ENOMEM;
313 }
314
315 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
316 {
317 if (dma_unmap_len(tx_buf, dma_len0))
318 dma_unmap_page(dev,
319 dma_unmap_addr(tx_buf, dma_addr0),
320 dma_unmap_len(tx_buf, dma_len0),
321 DMA_TO_DEVICE);
322
323 if (dma_unmap_len(tx_buf, dma_len1))
324 dma_unmap_page(dev,
325 dma_unmap_addr(tx_buf, dma_addr1),
326 dma_unmap_len(tx_buf, dma_len1),
327 DMA_TO_DEVICE);
328
329 dma_unmap_len_set(tx_buf, dma_addr0, 0);
330 dma_unmap_len_set(tx_buf, dma_addr1, 0);
331 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
332 dev_kfree_skb_any(tx_buf->skb);
333 tx_buf->skb = NULL;
334 }
335
336 static void fe_clean_tx(struct fe_priv *priv)
337 {
338 int i;
339 struct device *dev = priv->dev;
340 struct fe_tx_ring *ring = &priv->tx_ring;
341
342 if (ring->tx_buf) {
343 for (i = 0; i < ring->tx_ring_size; i++)
344 fe_txd_unmap(dev, &ring->tx_buf[i]);
345 kfree(ring->tx_buf);
346 ring->tx_buf = NULL;
347 }
348
349 if (ring->tx_dma) {
350 dma_free_coherent(dev,
351 ring->tx_ring_size * sizeof(*ring->tx_dma),
352 ring->tx_dma,
353 ring->tx_phys);
354 ring->tx_dma = NULL;
355 }
356
357 netdev_reset_queue(priv->netdev);
358 }
359
360 static int fe_alloc_tx(struct fe_priv *priv)
361 {
362 int i;
363 struct fe_tx_ring *ring = &priv->tx_ring;
364
365 ring->tx_free_idx = 0;
366 ring->tx_next_idx = 0;
367 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
368 MAX_SKB_FRAGS);
369
370 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
371 GFP_KERNEL);
372 if (!ring->tx_buf)
373 goto no_tx_mem;
374
375 ring->tx_dma = dma_alloc_coherent(priv->dev,
376 ring->tx_ring_size * sizeof(*ring->tx_dma),
377 &ring->tx_phys,
378 GFP_ATOMIC | __GFP_ZERO);
379 if (!ring->tx_dma)
380 goto no_tx_mem;
381
382 for (i = 0; i < ring->tx_ring_size; i++) {
383 if (priv->soc->tx_dma)
384 priv->soc->tx_dma(&ring->tx_dma[i]);
385 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
386 }
387 /* make sure that all changes to the dma ring are flushed before we
388 * continue
389 */
390 wmb();
391
392 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
393 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
394 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
395 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
396
397 return 0;
398
399 no_tx_mem:
400 return -ENOMEM;
401 }
402
403 static int fe_init_dma(struct fe_priv *priv)
404 {
405 int err;
406
407 err = fe_alloc_tx(priv);
408 if (err)
409 return err;
410
411 err = fe_alloc_rx(priv);
412 if (err)
413 return err;
414
415 return 0;
416 }
417
418 static void fe_free_dma(struct fe_priv *priv)
419 {
420 fe_clean_tx(priv);
421 fe_clean_rx(priv);
422 }
423
424 void fe_stats_update(struct fe_priv *priv)
425 {
426 struct fe_hw_stats *hwstats = priv->hw_stats;
427 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
428 u64 stats;
429
430 u64_stats_update_begin(&hwstats->syncp);
431
432 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
433 hwstats->rx_bytes += fe_r32(base);
434 stats = fe_r32(base + 0x04);
435 if (stats)
436 hwstats->rx_bytes += (stats << 32);
437 hwstats->rx_packets += fe_r32(base + 0x08);
438 hwstats->rx_overflow += fe_r32(base + 0x10);
439 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
440 hwstats->rx_short_errors += fe_r32(base + 0x18);
441 hwstats->rx_long_errors += fe_r32(base + 0x1c);
442 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
443 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
444 hwstats->tx_skip += fe_r32(base + 0x28);
445 hwstats->tx_collisions += fe_r32(base + 0x2c);
446 hwstats->tx_bytes += fe_r32(base + 0x30);
447 stats = fe_r32(base + 0x34);
448 if (stats)
449 hwstats->tx_bytes += (stats << 32);
450 hwstats->tx_packets += fe_r32(base + 0x38);
451 } else {
452 hwstats->tx_bytes += fe_r32(base);
453 hwstats->tx_packets += fe_r32(base + 0x04);
454 hwstats->tx_skip += fe_r32(base + 0x08);
455 hwstats->tx_collisions += fe_r32(base + 0x0c);
456 hwstats->rx_bytes += fe_r32(base + 0x20);
457 hwstats->rx_packets += fe_r32(base + 0x24);
458 hwstats->rx_overflow += fe_r32(base + 0x28);
459 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
460 hwstats->rx_short_errors += fe_r32(base + 0x30);
461 hwstats->rx_long_errors += fe_r32(base + 0x34);
462 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
463 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
464 }
465
466 u64_stats_update_end(&hwstats->syncp);
467 }
468
469 static void fe_get_stats64(struct net_device *dev,
470 struct rtnl_link_stats64 *storage)
471 {
472 struct fe_priv *priv = netdev_priv(dev);
473 struct fe_hw_stats *hwstats = priv->hw_stats;
474 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
475 unsigned int start;
476
477 if (!base) {
478 netdev_stats_to_stats64(storage, &dev->stats);
479 return;
480 }
481
482 if (netif_running(dev) && netif_device_present(dev)) {
483 if (spin_trylock_bh(&hwstats->stats_lock)) {
484 fe_stats_update(priv);
485 spin_unlock_bh(&hwstats->stats_lock);
486 }
487 }
488
489 do {
490 #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
491 start = u64_stats_fetch_begin(&hwstats->syncp);
492 #else
493 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
494 #endif
495 storage->rx_packets = hwstats->rx_packets;
496 storage->tx_packets = hwstats->tx_packets;
497 storage->rx_bytes = hwstats->rx_bytes;
498 storage->tx_bytes = hwstats->tx_bytes;
499 storage->collisions = hwstats->tx_collisions;
500 storage->rx_length_errors = hwstats->rx_short_errors +
501 hwstats->rx_long_errors;
502 storage->rx_over_errors = hwstats->rx_overflow;
503 storage->rx_crc_errors = hwstats->rx_fcs_errors;
504 storage->rx_errors = hwstats->rx_checksum_errors;
505 storage->tx_aborted_errors = hwstats->tx_skip;
506 #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 6, 0)
507 } while (u64_stats_fetch_retry(&hwstats->syncp, start));
508 #else
509 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
510 #endif
511
512 storage->tx_errors = priv->netdev->stats.tx_errors;
513 storage->rx_dropped = priv->netdev->stats.rx_dropped;
514 storage->tx_dropped = priv->netdev->stats.tx_dropped;
515 }
516
517 static int fe_vlan_rx_add_vid(struct net_device *dev,
518 __be16 proto, u16 vid)
519 {
520 struct fe_priv *priv = netdev_priv(dev);
521 u32 idx = (vid & 0xf);
522 u32 vlan_cfg;
523
524 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
525 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
526 return 0;
527
528 if (test_bit(idx, &priv->vlan_map)) {
529 netdev_warn(dev, "disable tx vlan offload\n");
530 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
531 netdev_update_features(dev);
532 } else {
533 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
534 ((idx >> 1) << 2));
535 if (idx & 0x1) {
536 vlan_cfg &= 0xffff;
537 vlan_cfg |= (vid << 16);
538 } else {
539 vlan_cfg &= 0xffff0000;
540 vlan_cfg |= vid;
541 }
542 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
543 ((idx >> 1) << 2));
544 set_bit(idx, &priv->vlan_map);
545 }
546
547 return 0;
548 }
549
550 static int fe_vlan_rx_kill_vid(struct net_device *dev,
551 __be16 proto, u16 vid)
552 {
553 struct fe_priv *priv = netdev_priv(dev);
554 u32 idx = (vid & 0xf);
555
556 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
557 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
558 return 0;
559
560 clear_bit(idx, &priv->vlan_map);
561
562 return 0;
563 }
564
565 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
566 {
567 barrier();
568 return (u32)(ring->tx_ring_size -
569 ((ring->tx_next_idx - ring->tx_free_idx) &
570 (ring->tx_ring_size - 1)));
571 }
572
573 struct fe_map_state {
574 struct device *dev;
575 struct fe_tx_dma txd;
576 u32 def_txd4;
577 int ring_idx;
578 int i;
579 };
580
581 static void fe_tx_dma_write_desc(struct fe_tx_ring *ring, struct fe_map_state *st)
582 {
583 fe_set_txd(&st->txd, &ring->tx_dma[st->ring_idx]);
584 memset(&st->txd, 0, sizeof(st->txd));
585 st->txd.txd4 = st->def_txd4;
586 st->ring_idx = NEXT_TX_DESP_IDX(st->ring_idx);
587 }
588
589 static int __fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,
590 struct page *page, size_t offset, size_t size)
591 {
592 struct device *dev = st->dev;
593 struct fe_tx_buf *tx_buf;
594 dma_addr_t mapped_addr;
595
596 mapped_addr = dma_map_page(dev, page, offset, size, DMA_TO_DEVICE);
597 if (unlikely(dma_mapping_error(dev, mapped_addr)))
598 return -EIO;
599
600 if (st->i && !(st->i & 1))
601 fe_tx_dma_write_desc(ring, st);
602
603 tx_buf = &ring->tx_buf[st->ring_idx];
604 if (st->i & 1) {
605 st->txd.txd3 = mapped_addr;
606 st->txd.txd2 |= TX_DMA_PLEN1(size);
607 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
608 dma_unmap_len_set(tx_buf, dma_len1, size);
609 } else {
610 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
611 st->txd.txd1 = mapped_addr;
612 st->txd.txd2 = TX_DMA_PLEN0(size);
613 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
614 dma_unmap_len_set(tx_buf, dma_len0, size);
615 }
616 st->i++;
617
618 return 0;
619 }
620
621 static int fe_tx_dma_map_page(struct fe_tx_ring *ring, struct fe_map_state *st,
622 struct page *page, size_t offset, size_t size)
623 {
624 int cur_size;
625 int ret;
626
627 while (size > 0) {
628 cur_size = min_t(size_t, size, TX_DMA_BUF_LEN);
629
630 ret = __fe_tx_dma_map_page(ring, st, page, offset, cur_size);
631 if (ret)
632 return ret;
633
634 size -= cur_size;
635 offset += cur_size;
636 }
637
638 return 0;
639 }
640
641 static int fe_tx_dma_map_skb(struct fe_tx_ring *ring, struct fe_map_state *st,
642 struct sk_buff *skb)
643 {
644 struct page *page = virt_to_page(skb->data);
645 size_t offset = offset_in_page(skb->data);
646 size_t size = skb_headlen(skb);
647
648 return fe_tx_dma_map_page(ring, st, page, offset, size);
649 }
650
651 static inline struct sk_buff *
652 fe_next_frag(struct sk_buff *head, struct sk_buff *skb)
653 {
654 if (skb != head)
655 return skb->next;
656
657 if (skb_has_frag_list(skb))
658 return skb_shinfo(skb)->frag_list;
659
660 return NULL;
661 }
662
663
664 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
665 int tx_num, struct fe_tx_ring *ring)
666 {
667 struct fe_priv *priv = netdev_priv(dev);
668 struct fe_map_state st = {
669 .dev = priv->dev,
670 .ring_idx = ring->tx_next_idx,
671 };
672 struct sk_buff *head = skb;
673 struct fe_tx_buf *tx_buf;
674 unsigned int nr_frags;
675 int i, j;
676
677 /* init tx descriptor */
678 if (priv->soc->tx_dma)
679 priv->soc->tx_dma(&st.txd);
680 else
681 st.txd.txd4 = TX_DMA_DESP4_DEF;
682 st.def_txd4 = st.txd.txd4;
683
684 /* TX Checksum offload */
685 if (skb->ip_summed == CHECKSUM_PARTIAL)
686 st.txd.txd4 |= TX_DMA_CHKSUM;
687
688 /* VLAN header offload */
689 if (skb_vlan_tag_present(skb)) {
690 u16 tag = skb_vlan_tag_get(skb);
691
692 if (IS_ENABLED(CONFIG_SOC_MT7621))
693 st.txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
694 else
695 st.txd.txd4 |= TX_DMA_INS_VLAN |
696 ((tag >> VLAN_PRIO_SHIFT) << 4) |
697 (tag & 0xF);
698 }
699
700 /* TSO: fill MSS info in tcp checksum field */
701 if (skb_is_gso(skb)) {
702 if (skb_cow_head(skb, 0)) {
703 netif_warn(priv, tx_err, dev,
704 "GSO expand head fail.\n");
705 goto err_out;
706 }
707 if (skb_shinfo(skb)->gso_type &
708 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
709 st.txd.txd4 |= TX_DMA_TSO;
710 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
711 }
712 }
713
714 next_frag:
715 if (skb_headlen(skb) && fe_tx_dma_map_skb(ring, &st, skb))
716 goto err_dma;
717
718 /* TX SG offload */
719 nr_frags = skb_shinfo(skb)->nr_frags;
720 for (i = 0; i < nr_frags; i++) {
721 skb_frag_t *frag;
722
723 frag = &skb_shinfo(skb)->frags[i];
724 if (fe_tx_dma_map_page(ring, &st, skb_frag_page(frag),
725 skb_frag_off(frag), skb_frag_size(frag)))
726 goto err_dma;
727 }
728
729 skb = fe_next_frag(head, skb);
730 if (skb)
731 goto next_frag;
732
733 /* set last segment */
734 if (st.i & 0x1)
735 st.txd.txd2 |= TX_DMA_LS0;
736 else
737 st.txd.txd2 |= TX_DMA_LS1;
738
739 /* store skb to cleanup */
740 tx_buf = &ring->tx_buf[st.ring_idx];
741 tx_buf->skb = head;
742
743 netdev_sent_queue(dev, head->len);
744 skb_tx_timestamp(head);
745
746 fe_tx_dma_write_desc(ring, &st);
747 ring->tx_next_idx = st.ring_idx;
748
749 /* make sure that all changes to the dma ring are flushed before we
750 * continue
751 */
752 wmb();
753 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
754 netif_stop_queue(dev);
755 smp_mb();
756 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
757 netif_wake_queue(dev);
758 }
759
760 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !netdev_xmit_more())
761 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
762
763 return 0;
764
765 err_dma:
766 j = ring->tx_next_idx;
767 for (i = 0; i < tx_num; i++) {
768 /* unmap dma */
769 fe_txd_unmap(priv->dev, &ring->tx_buf[j]);
770 ring->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
771
772 j = NEXT_TX_DESP_IDX(j);
773 }
774 /* make sure that all changes to the dma ring are flushed before we
775 * continue
776 */
777 wmb();
778
779 err_out:
780 return -1;
781 }
782
783 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
784 {
785 unsigned int len;
786 int ret;
787
788 ret = 0;
789 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
790 if ((priv->flags & FE_FLAG_PADDING_64B) &&
791 !(priv->flags & FE_FLAG_PADDING_BUG))
792 return ret;
793
794 if (skb_vlan_tag_present(skb))
795 len = ETH_ZLEN;
796 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
797 len = VLAN_ETH_ZLEN;
798 else if (!(priv->flags & FE_FLAG_PADDING_64B))
799 len = ETH_ZLEN;
800 else
801 return ret;
802
803 if (skb->len < len) {
804 ret = skb_pad(skb, len - skb->len);
805 if (ret < 0)
806 return ret;
807 skb->len = len;
808 skb_set_tail_pointer(skb, len);
809 }
810 }
811
812 return ret;
813 }
814
815 static inline int fe_cal_txd_req(struct sk_buff *skb)
816 {
817 struct sk_buff *head = skb;
818 int i, nfrags = 0;
819 skb_frag_t *frag;
820
821 next_frag:
822 nfrags++;
823 if (skb_is_gso(skb)) {
824 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
825 frag = &skb_shinfo(skb)->frags[i];
826 nfrags += DIV_ROUND_UP(skb_frag_size(frag), TX_DMA_BUF_LEN);
827 }
828 } else {
829 nfrags += skb_shinfo(skb)->nr_frags;
830 }
831
832 skb = fe_next_frag(head, skb);
833 if (skb)
834 goto next_frag;
835
836 return DIV_ROUND_UP(nfrags, 2);
837 }
838
839 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
840 {
841 struct fe_priv *priv = netdev_priv(dev);
842 struct fe_tx_ring *ring = &priv->tx_ring;
843 struct net_device_stats *stats = &dev->stats;
844 int tx_num;
845 int len = skb->len;
846
847 if (fe_skb_padto(skb, priv)) {
848 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
849 return NETDEV_TX_OK;
850 }
851
852 tx_num = fe_cal_txd_req(skb);
853 if (unlikely(fe_empty_txd(ring) <= tx_num)) {
854 netif_stop_queue(dev);
855 netif_err(priv, tx_queued, dev,
856 "Tx Ring full when queue awake!\n");
857 return NETDEV_TX_BUSY;
858 }
859
860 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
861 stats->tx_dropped++;
862 } else {
863 stats->tx_packets++;
864 stats->tx_bytes += len;
865 }
866
867 return NETDEV_TX_OK;
868 }
869
870 static int fe_poll_rx(struct napi_struct *napi, int budget,
871 struct fe_priv *priv, u32 rx_intr)
872 {
873 struct net_device *netdev = priv->netdev;
874 struct net_device_stats *stats = &netdev->stats;
875 struct fe_soc_data *soc = priv->soc;
876 struct fe_rx_ring *ring = &priv->rx_ring;
877 int idx = ring->rx_calc_idx;
878 u32 checksum_bit;
879 struct sk_buff *skb;
880 u8 *data, *new_data;
881 struct fe_rx_dma *rxd, trxd;
882 int done = 0, pad;
883
884 if (netdev->features & NETIF_F_RXCSUM)
885 checksum_bit = soc->checksum_bit;
886 else
887 checksum_bit = 0;
888
889 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
890 pad = 0;
891 else
892 pad = NET_IP_ALIGN;
893
894 while (done < budget) {
895 unsigned int pktlen;
896 dma_addr_t dma_addr;
897
898 idx = NEXT_RX_DESP_IDX(idx);
899 rxd = &ring->rx_dma[idx];
900 data = ring->rx_data[idx];
901
902 fe_get_rxd(&trxd, rxd);
903 if (!(trxd.rxd2 & RX_DMA_DONE))
904 break;
905
906 /* alloc new buffer */
907 new_data = page_frag_alloc(&ring->frag_cache, ring->frag_size,
908 GFP_ATOMIC);
909 if (unlikely(!new_data)) {
910 stats->rx_dropped++;
911 goto release_desc;
912 }
913 dma_addr = dma_map_single(priv->dev,
914 new_data + NET_SKB_PAD + pad,
915 ring->rx_buf_size,
916 DMA_FROM_DEVICE);
917 if (unlikely(dma_mapping_error(priv->dev, dma_addr))) {
918 skb_free_frag(new_data);
919 goto release_desc;
920 }
921
922 /* receive data */
923 skb = build_skb(data, ring->frag_size);
924 if (unlikely(!skb)) {
925 skb_free_frag(new_data);
926 goto release_desc;
927 }
928 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
929
930 dma_unmap_single(priv->dev, trxd.rxd1,
931 ring->rx_buf_size, DMA_FROM_DEVICE);
932 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
933 skb->dev = netdev;
934 skb_put(skb, pktlen);
935 if (trxd.rxd4 & checksum_bit)
936 skb->ip_summed = CHECKSUM_UNNECESSARY;
937 else
938 skb_checksum_none_assert(skb);
939 skb->protocol = eth_type_trans(skb, netdev);
940
941 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
942 RX_DMA_VID(trxd.rxd3))
943 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
944 RX_DMA_VID(trxd.rxd3));
945
946 stats->rx_packets++;
947 stats->rx_bytes += pktlen;
948
949 napi_gro_receive(napi, skb);
950
951 ring->rx_data[idx] = new_data;
952 rxd->rxd1 = (unsigned int)dma_addr;
953
954 release_desc:
955 if (priv->flags & FE_FLAG_RX_SG_DMA)
956 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
957 else
958 rxd->rxd2 = RX_DMA_LSO;
959
960 ring->rx_calc_idx = idx;
961 /* make sure that all changes to the dma ring are flushed before
962 * we continue
963 */
964 wmb();
965 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
966 done++;
967 }
968
969 if (done < budget)
970 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
971
972 return done;
973 }
974
975 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
976 int *tx_again)
977 {
978 struct net_device *netdev = priv->netdev;
979 unsigned int bytes_compl = 0;
980 struct sk_buff *skb;
981 struct fe_tx_buf *tx_buf;
982 int done = 0;
983 u32 idx, hwidx;
984 struct fe_tx_ring *ring = &priv->tx_ring;
985
986 idx = ring->tx_free_idx;
987 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
988
989 while ((idx != hwidx) && budget) {
990 tx_buf = &ring->tx_buf[idx];
991 skb = tx_buf->skb;
992
993 if (!skb)
994 break;
995
996 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
997 bytes_compl += skb->len;
998 done++;
999 budget--;
1000 }
1001 fe_txd_unmap(priv->dev, tx_buf);
1002 idx = NEXT_TX_DESP_IDX(idx);
1003 }
1004 ring->tx_free_idx = idx;
1005
1006 if (idx == hwidx) {
1007 /* read hw index again make sure no new tx packet */
1008 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
1009 if (idx == hwidx)
1010 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
1011 else
1012 *tx_again = 1;
1013 } else {
1014 *tx_again = 1;
1015 }
1016
1017 if (done) {
1018 netdev_completed_queue(netdev, done, bytes_compl);
1019 smp_mb();
1020 if (unlikely(netif_queue_stopped(netdev) &&
1021 (fe_empty_txd(ring) > ring->tx_thresh)))
1022 netif_wake_queue(netdev);
1023 }
1024
1025 return done;
1026 }
1027
1028 static int fe_poll(struct napi_struct *napi, int budget)
1029 {
1030 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
1031 struct fe_hw_stats *hwstat = priv->hw_stats;
1032 int tx_done, rx_done, tx_again;
1033 u32 status, fe_status, status_reg, mask;
1034 u32 tx_intr, rx_intr, status_intr;
1035
1036 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1037 fe_status = status;
1038 tx_intr = priv->soc->tx_int;
1039 rx_intr = priv->soc->rx_int;
1040 status_intr = priv->soc->status_int;
1041 tx_done = 0;
1042 rx_done = 0;
1043 tx_again = 0;
1044
1045 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
1046 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
1047 status_reg = FE_REG_FE_INT_STATUS2;
1048 } else {
1049 status_reg = FE_REG_FE_INT_STATUS;
1050 }
1051
1052 if (status & tx_intr)
1053 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
1054
1055 if (status & rx_intr)
1056 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
1057
1058 if (unlikely(fe_status & status_intr)) {
1059 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
1060 fe_stats_update(priv);
1061 spin_unlock(&hwstat->stats_lock);
1062 }
1063 fe_reg_w32(status_intr, status_reg);
1064 }
1065
1066 if (unlikely(netif_msg_intr(priv))) {
1067 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
1068 netdev_info(priv->netdev,
1069 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1070 tx_done, rx_done, status, mask);
1071 }
1072
1073 if (!tx_again && (rx_done < budget)) {
1074 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1075 if (status & (tx_intr | rx_intr)) {
1076 /* let napi poll again */
1077 rx_done = budget;
1078 goto poll_again;
1079 }
1080
1081 napi_complete_done(napi, rx_done);
1082 fe_int_enable(tx_intr | rx_intr);
1083 } else {
1084 rx_done = budget;
1085 }
1086
1087 poll_again:
1088 return rx_done;
1089 }
1090
1091 static void fe_tx_timeout(struct net_device *dev, unsigned int txqueue)
1092 {
1093 struct fe_priv *priv = netdev_priv(dev);
1094 struct fe_tx_ring *ring = &priv->tx_ring;
1095
1096 priv->netdev->stats.tx_errors++;
1097 netif_err(priv, tx_err, dev,
1098 "transmit timed out\n");
1099 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1100 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1101 netif_info(priv, drv, dev, "tx_ring=%d, "
1102 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1103 0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1104 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1105 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1106 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1107 ring->tx_free_idx,
1108 ring->tx_next_idx);
1109 netif_info(priv, drv, dev,
1110 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1111 0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1112 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1113 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1114 fe_reg_r32(FE_REG_RX_DRX_IDX0));
1115
1116 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1117 schedule_work(&priv->pending_work);
1118 }
1119
1120 static irqreturn_t fe_handle_irq(int irq, void *dev)
1121 {
1122 struct fe_priv *priv = netdev_priv(dev);
1123 u32 status, int_mask;
1124
1125 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1126
1127 if (unlikely(!status))
1128 return IRQ_NONE;
1129
1130 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1131 if (likely(status & int_mask)) {
1132 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1133 fe_int_disable(int_mask);
1134 __napi_schedule(&priv->rx_napi);
1135 }
1136 } else {
1137 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1138 }
1139
1140 return IRQ_HANDLED;
1141 }
1142
1143 #ifdef CONFIG_NET_POLL_CONTROLLER
1144 static void fe_poll_controller(struct net_device *dev)
1145 {
1146 struct fe_priv *priv = netdev_priv(dev);
1147 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1148
1149 fe_int_disable(int_mask);
1150 fe_handle_irq(dev->irq, dev);
1151 fe_int_enable(int_mask);
1152 }
1153 #endif
1154
1155 int fe_set_clock_cycle(struct fe_priv *priv)
1156 {
1157 unsigned long sysclk = priv->sysclk;
1158
1159 sysclk /= FE_US_CYC_CNT_DIVISOR;
1160 sysclk <<= FE_US_CYC_CNT_SHIFT;
1161
1162 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1163 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1164 sysclk,
1165 FE_FE_GLO_CFG);
1166 return 0;
1167 }
1168
1169 void fe_fwd_config(struct fe_priv *priv)
1170 {
1171 u32 fwd_cfg;
1172
1173 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1174
1175 /* disable jumbo frame */
1176 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1177 fwd_cfg &= ~FE_GDM1_JMB_EN;
1178
1179 /* set unicast/multicast/broadcast frame to cpu */
1180 fwd_cfg &= ~0xffff;
1181
1182 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1183 }
1184
1185 static void fe_rxcsum_config(bool enable)
1186 {
1187 if (enable)
1188 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1189 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1190 FE_GDMA1_FWD_CFG);
1191 else
1192 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1193 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1194 FE_GDMA1_FWD_CFG);
1195 }
1196
1197 static void fe_txcsum_config(bool enable)
1198 {
1199 if (enable)
1200 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1201 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1202 FE_CDMA_CSG_CFG);
1203 else
1204 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1205 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1206 FE_CDMA_CSG_CFG);
1207 }
1208
1209 void fe_csum_config(struct fe_priv *priv)
1210 {
1211 struct net_device *dev = priv_netdev(priv);
1212
1213 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1214 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1215 }
1216
1217 static int fe_hw_init(struct net_device *dev)
1218 {
1219 struct fe_priv *priv = netdev_priv(dev);
1220 int i, err;
1221
1222 err = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0,
1223 dev_name(priv->dev), dev);
1224 if (err)
1225 return err;
1226
1227 if (priv->soc->set_mac)
1228 priv->soc->set_mac(priv, dev->dev_addr);
1229 else
1230 fe_hw_set_macaddr(priv, dev->dev_addr);
1231
1232 /* disable delay interrupt */
1233 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1234
1235 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1236
1237 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1238 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1239 for (i = 0; i < 16; i += 2)
1240 fe_w32(((i + 1) << 16) + i,
1241 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1242 (i * 2));
1243
1244 if (priv->soc->fwd_config(priv))
1245 netdev_err(dev, "unable to get clock\n");
1246
1247 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1248 fe_reg_w32(1, FE_REG_FE_RST_GL);
1249 fe_reg_w32(0, FE_REG_FE_RST_GL);
1250 }
1251
1252 return 0;
1253 }
1254
1255 static int fe_open(struct net_device *dev)
1256 {
1257 struct fe_priv *priv = netdev_priv(dev);
1258 unsigned long flags;
1259 u32 val;
1260 int err;
1261
1262 err = fe_init_dma(priv);
1263 if (err) {
1264 fe_free_dma(priv);
1265 return err;
1266 }
1267
1268 spin_lock_irqsave(&priv->page_lock, flags);
1269
1270 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1271 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1272 val |= FE_RX_2B_OFFSET;
1273 val |= priv->soc->pdma_glo_cfg;
1274 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1275
1276 spin_unlock_irqrestore(&priv->page_lock, flags);
1277
1278 if (priv->phy)
1279 priv->phy->start(priv);
1280
1281 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1282 netif_carrier_on(dev);
1283
1284 napi_enable(&priv->rx_napi);
1285 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1286 netif_start_queue(dev);
1287
1288 return 0;
1289 }
1290
1291 static int fe_stop(struct net_device *dev)
1292 {
1293 struct fe_priv *priv = netdev_priv(dev);
1294 unsigned long flags;
1295 int i;
1296
1297 netif_tx_disable(dev);
1298 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1299 napi_disable(&priv->rx_napi);
1300
1301 if (priv->phy)
1302 priv->phy->stop(priv);
1303
1304 spin_lock_irqsave(&priv->page_lock, flags);
1305
1306 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1307 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1308 FE_REG_PDMA_GLO_CFG);
1309 spin_unlock_irqrestore(&priv->page_lock, flags);
1310
1311 /* wait dma stop */
1312 for (i = 0; i < 10; i++) {
1313 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1314 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1315 msleep(20);
1316 continue;
1317 }
1318 break;
1319 }
1320
1321 fe_free_dma(priv);
1322
1323 return 0;
1324 }
1325
1326 static void fe_reset_phy(struct fe_priv *priv)
1327 {
1328 int err, msec = 30;
1329 struct gpio_desc *phy_reset;
1330
1331 phy_reset = devm_gpiod_get_optional(priv->dev, "phy-reset",
1332 GPIOD_OUT_HIGH);
1333 if (!phy_reset)
1334 return;
1335
1336 if (IS_ERR(phy_reset)) {
1337 dev_err(priv->dev, "Error acquiring reset gpio pins: %ld\n",
1338 PTR_ERR(phy_reset));
1339 return;
1340 }
1341
1342 err = of_property_read_u32(priv->dev->of_node, "phy-reset-duration",
1343 &msec);
1344 if (!err && msec > 1000)
1345 msec = 30;
1346
1347 if (msec > 20)
1348 msleep(msec);
1349 else
1350 usleep_range(msec * 1000, msec * 1000 + 1000);
1351
1352 gpiod_set_value(phy_reset, 0);
1353 }
1354
1355 static int __init fe_init(struct net_device *dev)
1356 {
1357 struct fe_priv *priv = netdev_priv(dev);
1358 struct device_node *port;
1359 int err;
1360
1361 fe_reset_fe(priv);
1362
1363 if (priv->soc->switch_init) {
1364 err = priv->soc->switch_init(priv);
1365 if (err) {
1366 if (err == -EPROBE_DEFER)
1367 return err;
1368
1369 netdev_err(dev, "failed to initialize switch core\n");
1370 return -ENODEV;
1371 }
1372 }
1373
1374 fe_reset_phy(priv);
1375
1376 /* Set the MAC address if it is correct, if not use a random MAC address */
1377 if (of_get_ethdev_address(priv->dev->of_node, dev)) {
1378 eth_hw_addr_random(dev);
1379 dev_err(priv->dev, "generated random MAC address %pM\n",
1380 dev->dev_addr);
1381 }
1382
1383 err = fe_mdio_init(priv);
1384 if (err)
1385 return err;
1386
1387 if (priv->soc->port_init)
1388 for_each_child_of_node(priv->dev->of_node, port)
1389 if (of_device_is_compatible(port, "mediatek,eth-port") &&
1390 of_device_is_available(port))
1391 priv->soc->port_init(priv, port);
1392
1393 if (priv->phy) {
1394 err = priv->phy->connect(priv);
1395 if (err)
1396 goto err_phy_disconnect;
1397 }
1398
1399 err = fe_hw_init(dev);
1400 if (err)
1401 goto err_phy_disconnect;
1402
1403 if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1404 priv->soc->switch_config(priv);
1405
1406 return 0;
1407
1408 err_phy_disconnect:
1409 if (priv->phy)
1410 priv->phy->disconnect(priv);
1411 fe_mdio_cleanup(priv);
1412
1413 return err;
1414 }
1415
1416 static void fe_uninit(struct net_device *dev)
1417 {
1418 struct fe_priv *priv = netdev_priv(dev);
1419
1420 if (priv->phy)
1421 priv->phy->disconnect(priv);
1422 fe_mdio_cleanup(priv);
1423
1424 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1425 free_irq(dev->irq, dev);
1426 }
1427
1428 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1429 {
1430 struct fe_priv *priv = netdev_priv(dev);
1431
1432 if (!priv->phy_dev)
1433 return -ENODEV;
1434
1435
1436 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1437 }
1438
1439 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1440 {
1441 struct fe_priv *priv = netdev_priv(dev);
1442 int frag_size, old_mtu;
1443 u32 fwd_cfg;
1444
1445 old_mtu = dev->mtu;
1446 dev->mtu = new_mtu;
1447
1448 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1449 return 0;
1450
1451 /* return early if the buffer sizes will not change */
1452 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1453 return 0;
1454 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1455 return 0;
1456
1457 if (new_mtu <= ETH_DATA_LEN)
1458 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1459 else
1460 priv->rx_ring.frag_size = PAGE_SIZE;
1461 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1462
1463 if (!netif_running(dev))
1464 return 0;
1465
1466 fe_stop(dev);
1467 if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
1468 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1469 if (new_mtu <= ETH_DATA_LEN) {
1470 fwd_cfg &= ~FE_GDM1_JMB_EN;
1471 } else {
1472 frag_size = fe_max_frag_size(new_mtu);
1473 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1474 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1475 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1476 }
1477 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1478 }
1479
1480 return fe_open(dev);
1481 }
1482
1483 static const struct net_device_ops fe_netdev_ops = {
1484 .ndo_init = fe_init,
1485 .ndo_uninit = fe_uninit,
1486 .ndo_open = fe_open,
1487 .ndo_stop = fe_stop,
1488 .ndo_start_xmit = fe_start_xmit,
1489 .ndo_set_mac_address = fe_set_mac_address,
1490 .ndo_validate_addr = eth_validate_addr,
1491 .ndo_do_ioctl = fe_do_ioctl,
1492 .ndo_change_mtu = fe_change_mtu,
1493 .ndo_tx_timeout = fe_tx_timeout,
1494 .ndo_get_stats64 = fe_get_stats64,
1495 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1496 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1497 #ifdef CONFIG_NET_POLL_CONTROLLER
1498 .ndo_poll_controller = fe_poll_controller,
1499 #endif
1500 };
1501
1502 static void fe_reset_pending(struct fe_priv *priv)
1503 {
1504 struct net_device *dev = priv->netdev;
1505 int err;
1506
1507 rtnl_lock();
1508 fe_stop(dev);
1509
1510 err = fe_open(dev);
1511 if (err) {
1512 netif_alert(priv, ifup, dev,
1513 "Driver up/down cycle failed, closing device.\n");
1514 dev_close(dev);
1515 }
1516 rtnl_unlock();
1517 }
1518
1519 static const struct fe_work_t fe_work[] = {
1520 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1521 };
1522
1523 static void fe_pending_work(struct work_struct *work)
1524 {
1525 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1526 int i;
1527 bool pending;
1528
1529 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1530 pending = test_and_clear_bit(fe_work[i].bitnr,
1531 priv->pending_flags);
1532 if (pending)
1533 fe_work[i].action(priv);
1534 }
1535 }
1536
1537 static int fe_probe(struct platform_device *pdev)
1538 {
1539 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1540 const struct of_device_id *match;
1541 struct fe_soc_data *soc;
1542 struct net_device *netdev;
1543 struct fe_priv *priv;
1544 struct clk *sysclk;
1545 int err, napi_weight;
1546
1547 err = device_reset(&pdev->dev);
1548 if (err)
1549 dev_err(&pdev->dev, "failed to reset device\n");
1550
1551 match = of_match_device(of_fe_match, &pdev->dev);
1552 soc = (struct fe_soc_data *)match->data;
1553
1554 if (soc->reg_table)
1555 fe_reg_table = soc->reg_table;
1556 else
1557 soc->reg_table = fe_reg_table;
1558
1559 fe_base = devm_ioremap_resource(&pdev->dev, res);
1560 if (IS_ERR(fe_base)) {
1561 err = -EADDRNOTAVAIL;
1562 goto err_out;
1563 }
1564
1565 netdev = alloc_etherdev(sizeof(*priv));
1566 if (!netdev) {
1567 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1568 err = -ENOMEM;
1569 goto err_iounmap;
1570 }
1571
1572 SET_NETDEV_DEV(netdev, &pdev->dev);
1573 netdev->netdev_ops = &fe_netdev_ops;
1574 netdev->base_addr = (unsigned long)fe_base;
1575
1576 netdev->irq = platform_get_irq(pdev, 0);
1577 if (netdev->irq < 0) {
1578 dev_err(&pdev->dev, "no IRQ resource found\n");
1579 err = -ENXIO;
1580 goto err_free_dev;
1581 }
1582
1583 priv = netdev_priv(netdev);
1584 spin_lock_init(&priv->page_lock);
1585 priv->resets = devm_reset_control_array_get_exclusive(&pdev->dev);
1586 if (IS_ERR(priv->resets)) {
1587 dev_err(&pdev->dev, "Failed to get resets for FE and ESW cores: %pe\n", priv->resets);
1588 priv->resets = NULL;
1589 }
1590
1591 if (soc->init_data)
1592 soc->init_data(soc, netdev);
1593 netdev->vlan_features = netdev->hw_features &
1594 ~(NETIF_F_HW_VLAN_CTAG_TX |
1595 NETIF_F_HW_VLAN_CTAG_RX);
1596 netdev->features |= netdev->hw_features;
1597
1598 if (IS_ENABLED(CONFIG_SOC_MT7621))
1599 netdev->max_mtu = 2048;
1600
1601 /* fake rx vlan filter func. to support tx vlan offload func */
1602 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1603 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1604
1605 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1606 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1607 if (!priv->hw_stats) {
1608 err = -ENOMEM;
1609 goto err_free_dev;
1610 }
1611 spin_lock_init(&priv->hw_stats->stats_lock);
1612 u64_stats_init(&priv->hw_stats->syncp);
1613 }
1614
1615 sysclk = devm_clk_get(&pdev->dev, NULL);
1616 if (!IS_ERR(sysclk)) {
1617 priv->sysclk = clk_get_rate(sysclk);
1618 } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
1619 dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
1620 err = -ENXIO;
1621 goto err_free_dev;
1622 }
1623
1624 priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
1625 if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
1626 dev_err(&pdev->dev, "failed to read switch phandle\n");
1627 err = -ENODEV;
1628 goto err_free_dev;
1629 }
1630
1631 priv->netdev = netdev;
1632 priv->dev = &pdev->dev;
1633 priv->soc = soc;
1634 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1635 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1636 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1637 priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
1638 priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1639 INIT_WORK(&priv->pending_work, fe_pending_work);
1640
1641 napi_weight = 16;
1642 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1643 napi_weight *= 4;
1644 priv->tx_ring.tx_ring_size *= 4;
1645 priv->rx_ring.rx_ring_size *= 4;
1646 }
1647 netif_napi_add_weight(netdev, &priv->rx_napi, fe_poll, napi_weight);
1648 fe_set_ethtool_ops(netdev);
1649
1650 err = register_netdev(netdev);
1651 if (err) {
1652 dev_err(&pdev->dev, "error bringing up device\n");
1653 goto err_free_dev;
1654 }
1655
1656 platform_set_drvdata(pdev, netdev);
1657
1658 netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
1659 netdev->base_addr, netdev->irq);
1660
1661 return 0;
1662
1663 err_free_dev:
1664 free_netdev(netdev);
1665 err_iounmap:
1666 devm_iounmap(&pdev->dev, fe_base);
1667 err_out:
1668 return err;
1669 }
1670
1671 static int fe_remove(struct platform_device *pdev)
1672 {
1673 struct net_device *dev = platform_get_drvdata(pdev);
1674 struct fe_priv *priv = netdev_priv(dev);
1675
1676 netif_napi_del(&priv->rx_napi);
1677 kfree(priv->hw_stats);
1678
1679 cancel_work_sync(&priv->pending_work);
1680
1681 unregister_netdev(dev);
1682 free_netdev(dev);
1683 platform_set_drvdata(pdev, NULL);
1684
1685 return 0;
1686 }
1687
1688 static struct platform_driver fe_driver = {
1689 .probe = fe_probe,
1690 .remove = fe_remove,
1691 .driver = {
1692 .name = "mtk_soc_eth",
1693 .owner = THIS_MODULE,
1694 .of_match_table = of_fe_match,
1695 },
1696 };
1697
1698 module_platform_driver(fe_driver);
1699
1700 MODULE_LICENSE("GPL");
1701 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1702 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1703 MODULE_VERSION(MTK_FE_DRV_VERSION);
OpenWrt Source Repository