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ramips: Fix too small rx buffer
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35 #include <linux/bug.h>
36
37 #include <asm/mach-ralink/ralink_regs.h>
38
39 #include "ralink_soc_eth.h"
40 #include "esw_rt3052.h"
41 #include "mdio.h"
42 #include "ralink_ethtool.h"
43
44 #define MAX_RX_LENGTH 1536
45 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
46 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
47 #define DMA_DUMMY_DESC 0xffffffff
48 #define FE_DEFAULT_MSG_ENABLE \
49 (NETIF_MSG_DRV | \
50 NETIF_MSG_PROBE | \
51 NETIF_MSG_LINK | \
52 NETIF_MSG_TIMER | \
53 NETIF_MSG_IFDOWN | \
54 NETIF_MSG_IFUP | \
55 NETIF_MSG_RX_ERR | \
56 NETIF_MSG_TX_ERR)
57
58 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
59 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
60 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
61 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
62
63 #define SYSC_REG_RSTCTRL 0x34
64
65 static int fe_msg_level = -1;
66 module_param_named(msg_level, fe_msg_level, int, 0);
67 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
68
69 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
70 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
71 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
72 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
73 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
74 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
75 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
76 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
77 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
78 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
79 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
80 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
81 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
82 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
83 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
84 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
85 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
86 };
87
88 static const u16 *fe_reg_table = fe_reg_table_default;
89
90 struct fe_work_t {
91 int bitnr;
92 void (*action)(struct fe_priv *);
93 };
94
95 static void __iomem *fe_base = 0;
96
97 void fe_w32(u32 val, unsigned reg)
98 {
99 __raw_writel(val, fe_base + reg);
100 }
101
102 u32 fe_r32(unsigned reg)
103 {
104 return __raw_readl(fe_base + reg);
105 }
106
107 void fe_reg_w32(u32 val, enum fe_reg reg)
108 {
109 fe_w32(val, fe_reg_table[reg]);
110 }
111
112 u32 fe_reg_r32(enum fe_reg reg)
113 {
114 return fe_r32(fe_reg_table[reg]);
115 }
116
117 void fe_reset(u32 reset_bits)
118 {
119 u32 t;
120
121 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
122 t |= reset_bits;
123 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
124 udelay(10);
125
126 t &= ~reset_bits;
127 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
128 udelay(10);
129 }
130
131 static inline void fe_int_disable(u32 mask)
132 {
133 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
134 FE_REG_FE_INT_ENABLE);
135 /* flush write */
136 fe_reg_r32(FE_REG_FE_INT_ENABLE);
137 }
138
139 static inline void fe_int_enable(u32 mask)
140 {
141 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
142 FE_REG_FE_INT_ENABLE);
143 /* flush write */
144 fe_reg_r32(FE_REG_FE_INT_ENABLE);
145 }
146
147 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
148 {
149 unsigned long flags;
150
151 spin_lock_irqsave(&priv->page_lock, flags);
152 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
153 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
154 FE_GDMA1_MAC_ADRL);
155 spin_unlock_irqrestore(&priv->page_lock, flags);
156 }
157
158 static int fe_set_mac_address(struct net_device *dev, void *p)
159 {
160 int ret = eth_mac_addr(dev, p);
161
162 if (!ret) {
163 struct fe_priv *priv = netdev_priv(dev);
164
165 if (priv->soc->set_mac)
166 priv->soc->set_mac(priv, dev->dev_addr);
167 else
168 fe_hw_set_macaddr(priv, p);
169 }
170
171 return ret;
172 }
173
174 static inline int fe_max_frag_size(int mtu)
175 {
176 /* make sure buf_size will be at least MAX_RX_LENGTH */
177 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
178 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
179
180 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
181 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
182 }
183
184 static inline int fe_max_buf_size(int frag_size)
185 {
186 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
187 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
188
189 BUG_ON(buf_size < MAX_RX_LENGTH);
190 return buf_size;
191 }
192
193 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
194 {
195 rxd->rxd1 = dma_rxd->rxd1;
196 rxd->rxd2 = dma_rxd->rxd2;
197 rxd->rxd3 = dma_rxd->rxd3;
198 rxd->rxd4 = dma_rxd->rxd4;
199 }
200
201 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
202 {
203 dma_txd->txd1 = txd->txd1;
204 dma_txd->txd3 = txd->txd3;
205 dma_txd->txd4 = txd->txd4;
206 /* clean dma done flag last */
207 dma_txd->txd2 = txd->txd2;
208 }
209
210 static void fe_clean_rx(struct fe_priv *priv)
211 {
212 int i;
213 struct fe_rx_ring *ring = &priv->rx_ring;
214
215 if (ring->rx_data) {
216 for (i = 0; i < ring->rx_ring_size; i++)
217 if (ring->rx_data[i]) {
218 if (ring->rx_dma && ring->rx_dma[i].rxd1)
219 dma_unmap_single(&priv->netdev->dev,
220 ring->rx_dma[i].rxd1,
221 ring->rx_buf_size,
222 DMA_FROM_DEVICE);
223 put_page(virt_to_head_page(ring->rx_data[i]));
224 }
225
226 kfree(ring->rx_data);
227 ring->rx_data = NULL;
228 }
229
230 if (ring->rx_dma) {
231 dma_free_coherent(&priv->netdev->dev,
232 ring->rx_ring_size * sizeof(*ring->rx_dma),
233 ring->rx_dma,
234 ring->rx_phys);
235 ring->rx_dma = NULL;
236 }
237 }
238
239 static int fe_alloc_rx(struct fe_priv *priv)
240 {
241 struct net_device *netdev = priv->netdev;
242 struct fe_rx_ring *ring = &priv->rx_ring;
243 int i, pad;
244
245 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
246 GFP_KERNEL);
247 if (!ring->rx_data)
248 goto no_rx_mem;
249
250 for (i = 0; i < ring->rx_ring_size; i++) {
251 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
252 if (!ring->rx_data[i])
253 goto no_rx_mem;
254 }
255
256 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
257 ring->rx_ring_size * sizeof(*ring->rx_dma),
258 &ring->rx_phys,
259 GFP_ATOMIC | __GFP_ZERO);
260 if (!ring->rx_dma)
261 goto no_rx_mem;
262
263 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
264 pad = 0;
265 else
266 pad = NET_IP_ALIGN;
267 for (i = 0; i < ring->rx_ring_size; i++) {
268 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
269 ring->rx_data[i] + NET_SKB_PAD + pad,
270 ring->rx_buf_size,
271 DMA_FROM_DEVICE);
272 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
273 goto no_rx_mem;
274 ring->rx_dma[i].rxd1 = (unsigned int) dma_addr;
275
276 if (priv->flags & FE_FLAG_RX_SG_DMA)
277 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
278 else
279 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
280 }
281 ring->rx_calc_idx = ring->rx_ring_size - 1;
282 wmb();
283
284 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
285 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
286 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
287 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
288
289 return 0;
290
291 no_rx_mem:
292 return -ENOMEM;
293 }
294
295 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
296 {
297 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
298 dma_unmap_single(dev,
299 dma_unmap_addr(tx_buf, dma_addr0),
300 dma_unmap_len(tx_buf, dma_len0),
301 DMA_TO_DEVICE);
302 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
303 dma_unmap_page(dev,
304 dma_unmap_addr(tx_buf, dma_addr0),
305 dma_unmap_len(tx_buf, dma_len0),
306 DMA_TO_DEVICE);
307 }
308 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
309 dma_unmap_page(dev,
310 dma_unmap_addr(tx_buf, dma_addr1),
311 dma_unmap_len(tx_buf, dma_len1),
312 DMA_TO_DEVICE);
313
314 tx_buf->flags = 0;
315 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *) DMA_DUMMY_DESC)) {
316 dev_kfree_skb_any(tx_buf->skb);
317 }
318 tx_buf->skb = NULL;
319 }
320
321 static void fe_clean_tx(struct fe_priv *priv)
322 {
323 int i;
324 struct device *dev = &priv->netdev->dev;
325 struct fe_tx_ring *ring = &priv->tx_ring;
326
327 if (ring->tx_buf) {
328 for (i = 0; i < ring->tx_ring_size; i++)
329 fe_txd_unmap(dev, &ring->tx_buf[i]);
330 kfree(ring->tx_buf);
331 ring->tx_buf = NULL;
332 }
333
334 if (ring->tx_dma) {
335 dma_free_coherent(dev,
336 ring->tx_ring_size * sizeof(*ring->tx_dma),
337 ring->tx_dma,
338 ring->tx_phys);
339 ring->tx_dma = NULL;
340 }
341
342 netdev_reset_queue(priv->netdev);
343 }
344
345 static int fe_alloc_tx(struct fe_priv *priv)
346 {
347 int i;
348 struct fe_tx_ring *ring = &priv->tx_ring;
349
350 ring->tx_free_idx = 0;
351 ring->tx_next_idx = 0;
352 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2, MAX_SKB_FRAGS);
353
354 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
355 GFP_KERNEL);
356 if (!ring->tx_buf)
357 goto no_tx_mem;
358
359 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
360 ring->tx_ring_size * sizeof(*ring->tx_dma),
361 &ring->tx_phys,
362 GFP_ATOMIC | __GFP_ZERO);
363 if (!ring->tx_dma)
364 goto no_tx_mem;
365
366 for (i = 0; i < ring->tx_ring_size; i++) {
367 if (priv->soc->tx_dma) {
368 priv->soc->tx_dma(&ring->tx_dma[i]);
369 }
370 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
371 }
372 wmb();
373
374 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
375 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
376 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
377 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
378
379 return 0;
380
381 no_tx_mem:
382 return -ENOMEM;
383 }
384
385 static int fe_init_dma(struct fe_priv *priv)
386 {
387 int err;
388
389 err = fe_alloc_tx(priv);
390 if (err)
391 return err;
392
393 err = fe_alloc_rx(priv);
394 if (err)
395 return err;
396
397 return 0;
398 }
399
400 static void fe_free_dma(struct fe_priv *priv)
401 {
402 fe_clean_tx(priv);
403 fe_clean_rx(priv);
404 }
405
406 void fe_stats_update(struct fe_priv *priv)
407 {
408 struct fe_hw_stats *hwstats = priv->hw_stats;
409 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
410 u64 stats;
411
412 u64_stats_update_begin(&hwstats->syncp);
413
414 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
415 hwstats->rx_bytes += fe_r32(base);
416 stats = fe_r32(base + 0x04);
417 if (stats)
418 hwstats->rx_bytes += (stats << 32);
419 hwstats->rx_packets += fe_r32(base + 0x08);
420 hwstats->rx_overflow += fe_r32(base + 0x10);
421 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
422 hwstats->rx_short_errors += fe_r32(base + 0x18);
423 hwstats->rx_long_errors += fe_r32(base + 0x1c);
424 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
425 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
426 hwstats->tx_skip += fe_r32(base + 0x28);
427 hwstats->tx_collisions += fe_r32(base + 0x2c);
428 hwstats->tx_bytes += fe_r32(base + 0x30);
429 stats = fe_r32(base + 0x34);
430 if (stats)
431 hwstats->tx_bytes += (stats << 32);
432 hwstats->tx_packets += fe_r32(base + 0x38);
433 } else {
434 hwstats->tx_bytes += fe_r32(base);
435 hwstats->tx_packets += fe_r32(base + 0x04);
436 hwstats->tx_skip += fe_r32(base + 0x08);
437 hwstats->tx_collisions += fe_r32(base + 0x0c);
438 hwstats->rx_bytes += fe_r32(base + 0x20);
439 hwstats->rx_packets += fe_r32(base + 0x24);
440 hwstats->rx_overflow += fe_r32(base + 0x28);
441 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
442 hwstats->rx_short_errors += fe_r32(base + 0x30);
443 hwstats->rx_long_errors += fe_r32(base + 0x34);
444 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
445 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
446 }
447
448 u64_stats_update_end(&hwstats->syncp);
449 }
450
451 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
452 struct rtnl_link_stats64 *storage)
453 {
454 struct fe_priv *priv = netdev_priv(dev);
455 struct fe_hw_stats *hwstats = priv->hw_stats;
456 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
457 unsigned int start;
458
459 if (!base) {
460 netdev_stats_to_stats64(storage, &dev->stats);
461 return storage;
462 }
463
464 if (netif_running(dev) && netif_device_present(dev)) {
465 if (spin_trylock(&hwstats->stats_lock)) {
466 fe_stats_update(priv);
467 spin_unlock(&hwstats->stats_lock);
468 }
469 }
470
471 do {
472 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
473 storage->rx_packets = hwstats->rx_packets;
474 storage->tx_packets = hwstats->tx_packets;
475 storage->rx_bytes = hwstats->rx_bytes;
476 storage->tx_bytes = hwstats->tx_bytes;
477 storage->collisions = hwstats->tx_collisions;
478 storage->rx_length_errors = hwstats->rx_short_errors +
479 hwstats->rx_long_errors;
480 storage->rx_over_errors = hwstats->rx_overflow;
481 storage->rx_crc_errors = hwstats->rx_fcs_errors;
482 storage->rx_errors = hwstats->rx_checksum_errors;
483 storage->tx_aborted_errors = hwstats->tx_skip;
484 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
485
486 storage->tx_errors = priv->netdev->stats.tx_errors;
487 storage->rx_dropped = priv->netdev->stats.rx_dropped;
488 storage->tx_dropped = priv->netdev->stats.tx_dropped;
489
490 return storage;
491 }
492
493 static int fe_vlan_rx_add_vid(struct net_device *dev,
494 __be16 proto, u16 vid)
495 {
496 struct fe_priv *priv = netdev_priv(dev);
497 u32 idx = (vid & 0xf);
498 u32 vlan_cfg;
499
500 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
501 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
502 return 0;
503
504 if (test_bit(idx, &priv->vlan_map)) {
505 netdev_warn(dev, "disable tx vlan offload\n");
506 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
507 netdev_update_features(dev);
508 } else {
509 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
510 ((idx >> 1) << 2));
511 if (idx & 0x1) {
512 vlan_cfg &= 0xffff;
513 vlan_cfg |= (vid << 16);
514 } else {
515 vlan_cfg &= 0xffff0000;
516 vlan_cfg |= vid;
517 }
518 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
519 ((idx >> 1) << 2));
520 set_bit(idx, &priv->vlan_map);
521 }
522
523 return 0;
524 }
525
526 static int fe_vlan_rx_kill_vid(struct net_device *dev,
527 __be16 proto, u16 vid)
528 {
529 struct fe_priv *priv = netdev_priv(dev);
530 u32 idx = (vid & 0xf);
531
532 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
533 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
534 return 0;
535
536 clear_bit(idx, &priv->vlan_map);
537
538 return 0;
539 }
540
541 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
542 {
543 barrier();
544 return (u32)(ring->tx_ring_size -
545 ((ring->tx_next_idx - ring->tx_free_idx) &
546 (ring->tx_ring_size - 1)));
547 }
548
549 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
550 int tx_num, struct fe_tx_ring *ring)
551 {
552 struct fe_priv *priv = netdev_priv(dev);
553 struct skb_frag_struct *frag;
554 struct fe_tx_dma txd, *ptxd;
555 struct fe_tx_buf *tx_buf;
556 dma_addr_t mapped_addr;
557 unsigned int nr_frags;
558 u32 def_txd4;
559 int i, j, k, frag_size, frag_map_size, offset;
560
561 tx_buf = &ring->tx_buf[ring->tx_next_idx];
562 memset(tx_buf, 0, sizeof(*tx_buf));
563 memset(&txd, 0, sizeof(txd));
564 nr_frags = skb_shinfo(skb)->nr_frags;
565
566 /* init tx descriptor */
567 if (priv->soc->tx_dma)
568 priv->soc->tx_dma(&txd);
569 else
570 txd.txd4 = TX_DMA_DESP4_DEF;
571 def_txd4 = txd.txd4;
572
573 /* TX Checksum offload */
574 if (skb->ip_summed == CHECKSUM_PARTIAL)
575 txd.txd4 |= TX_DMA_CHKSUM;
576
577 /* VLAN header offload */
578 if (vlan_tx_tag_present(skb)) {
579 if (IS_ENABLED(CONFIG_SOC_MT7621))
580 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
581 else
582 txd.txd4 |= TX_DMA_INS_VLAN |
583 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
584 (vlan_tx_tag_get(skb) & 0xF);
585 }
586
587 /* TSO: fill MSS info in tcp checksum field */
588 if (skb_is_gso(skb)) {
589 if (skb_cow_head(skb, 0)) {
590 netif_warn(priv, tx_err, dev,
591 "GSO expand head fail.\n");
592 goto err_out;
593 }
594 if (skb_shinfo(skb)->gso_type &
595 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
596 txd.txd4 |= TX_DMA_TSO;
597 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
598 }
599 }
600
601 mapped_addr = dma_map_single(&dev->dev, skb->data,
602 skb_headlen(skb), DMA_TO_DEVICE);
603 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
604 goto err_out;
605 txd.txd1 = mapped_addr;
606 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
607
608 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
609 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
610 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
611
612 /* TX SG offload */
613 j = ring->tx_next_idx;
614 k = 0;
615 for (i = 0; i < nr_frags; i++) {
616 offset = 0;
617 frag = &skb_shinfo(skb)->frags[i];
618 frag_size = skb_frag_size(frag);
619
620 while (frag_size > 0) {
621 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
622 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
623 frag_map_size, DMA_TO_DEVICE);
624 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
625 goto err_dma;
626
627 if (k & 0x1) {
628 j = NEXT_TX_DESP_IDX(j);
629 txd.txd1 = mapped_addr;
630 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
631 txd.txd4 = def_txd4;
632
633 tx_buf = &ring->tx_buf[j];
634 memset(tx_buf, 0, sizeof(*tx_buf));
635
636 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
637 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
638 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
639 } else {
640 txd.txd3 = mapped_addr;
641 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
642
643 tx_buf->skb = (struct sk_buff *) DMA_DUMMY_DESC;
644 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
645 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
646 dma_unmap_len_set(tx_buf, dma_len1, frag_map_size);
647
648 if (!((i == (nr_frags -1)) &&
649 (frag_map_size == frag_size))) {
650 fe_set_txd(&txd, &ring->tx_dma[j]);
651 memset(&txd, 0, sizeof(txd));
652 }
653 }
654 frag_size -= frag_map_size;
655 offset += frag_map_size;
656 k++;
657 }
658 }
659
660 /* set last segment */
661 if (k & 0x1)
662 txd.txd2 |= TX_DMA_LS1;
663 else
664 txd.txd2 |= TX_DMA_LS0;
665 fe_set_txd(&txd, &ring->tx_dma[j]);
666
667 /* store skb to cleanup */
668 tx_buf->skb = skb;
669
670 netdev_sent_queue(dev, skb->len);
671 skb_tx_timestamp(skb);
672
673 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
674 wmb();
675 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
676 netif_stop_queue(dev);
677 smp_mb();
678 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
679 netif_wake_queue(dev);
680 }
681
682 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
683 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
684
685 return 0;
686
687 err_dma:
688 j = ring->tx_next_idx;
689 for (i = 0; i < tx_num; i++) {
690 ptxd = &ring->tx_dma[j];
691 tx_buf = &ring->tx_buf[j];
692
693 /* unmap dma */
694 fe_txd_unmap(&dev->dev, tx_buf);
695
696 ptxd->txd2 = TX_DMA_DESP2_DEF;
697 j = NEXT_TX_DESP_IDX(j);
698 }
699 wmb();
700
701 err_out:
702 return -1;
703 }
704
705 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
706 unsigned int len;
707 int ret;
708
709 ret = 0;
710 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
711 if ((priv->flags & FE_FLAG_PADDING_64B) &&
712 !(priv->flags & FE_FLAG_PADDING_BUG))
713 return ret;
714
715 if (vlan_tx_tag_present(skb))
716 len = ETH_ZLEN;
717 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
718 len = VLAN_ETH_ZLEN;
719 else if(!(priv->flags & FE_FLAG_PADDING_64B))
720 len = ETH_ZLEN;
721 else
722 return ret;
723
724 if (skb->len < len) {
725 if ((ret = skb_pad(skb, len - skb->len)) < 0)
726 return ret;
727 skb->len = len;
728 skb_set_tail_pointer(skb, len);
729 }
730 }
731
732 return ret;
733 }
734
735 static inline int fe_cal_txd_req(struct sk_buff *skb)
736 {
737 int i, nfrags;
738 struct skb_frag_struct *frag;
739
740 nfrags = 1;
741 if (skb_is_gso(skb)) {
742 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
743 frag = &skb_shinfo(skb)->frags[i];
744 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
745 }
746 } else {
747 nfrags += skb_shinfo(skb)->nr_frags;
748 }
749
750 return DIV_ROUND_UP(nfrags, 2);
751 }
752
753 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
754 {
755 struct fe_priv *priv = netdev_priv(dev);
756 struct fe_tx_ring *ring = &priv->tx_ring;
757 struct net_device_stats *stats = &dev->stats;
758 int tx_num;
759 int len = skb->len;
760
761 if (fe_skb_padto(skb, priv)) {
762 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
763 return NETDEV_TX_OK;
764 }
765
766 tx_num = fe_cal_txd_req(skb);
767 if (unlikely(fe_empty_txd(ring) <= tx_num))
768 {
769 netif_stop_queue(dev);
770 netif_err(priv, tx_queued,dev,
771 "Tx Ring full when queue awake!\n");
772 return NETDEV_TX_BUSY;
773 }
774
775 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
776 stats->tx_dropped++;
777 } else {
778 stats->tx_packets++;
779 stats->tx_bytes += len;
780 }
781
782 return NETDEV_TX_OK;
783 }
784
785 static inline void fe_rx_vlan(struct sk_buff *skb)
786 {
787 struct ethhdr *ehdr;
788 u16 vlanid;
789
790 if (!__vlan_get_tag(skb, &vlanid)) {
791 /* pop the vlan tag */
792 ehdr = (struct ethhdr *)skb->data;
793 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
794 skb_pull(skb, VLAN_HLEN);
795 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
796 }
797 }
798
799 static int fe_poll_rx(struct napi_struct *napi, int budget,
800 struct fe_priv *priv, u32 rx_intr)
801 {
802 struct net_device *netdev = priv->netdev;
803 struct net_device_stats *stats = &netdev->stats;
804 struct fe_soc_data *soc = priv->soc;
805 struct fe_rx_ring *ring = &priv->rx_ring;
806 int idx = ring->rx_calc_idx;
807 u32 checksum_bit;
808 struct sk_buff *skb;
809 u8 *data, *new_data;
810 struct fe_rx_dma *rxd, trxd;
811 int done = 0, pad;
812 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
813
814 if (netdev->features & NETIF_F_RXCSUM)
815 checksum_bit = soc->checksum_bit;
816 else
817 checksum_bit = 0;
818
819 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
820 pad = 0;
821 else
822 pad = NET_IP_ALIGN;
823
824 while (done < budget) {
825 unsigned int pktlen;
826 dma_addr_t dma_addr;
827 idx = NEXT_RX_DESP_IDX(idx);
828 rxd = &ring->rx_dma[idx];
829 data = ring->rx_data[idx];
830
831 fe_get_rxd(&trxd, rxd);
832 if (!(trxd.rxd2 & RX_DMA_DONE))
833 break;
834
835 /* alloc new buffer */
836 new_data = netdev_alloc_frag(ring->frag_size);
837 if (unlikely(!new_data)) {
838 stats->rx_dropped++;
839 goto release_desc;
840 }
841 dma_addr = dma_map_single(&netdev->dev,
842 new_data + NET_SKB_PAD + pad,
843 ring->rx_buf_size,
844 DMA_FROM_DEVICE);
845 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
846 put_page(virt_to_head_page(new_data));
847 goto release_desc;
848 }
849
850 /* receive data */
851 skb = build_skb(data, ring->frag_size);
852 if (unlikely(!skb)) {
853 put_page(virt_to_head_page(new_data));
854 goto release_desc;
855 }
856 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
857
858 dma_unmap_single(&netdev->dev, trxd.rxd1,
859 ring->rx_buf_size, DMA_FROM_DEVICE);
860 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
861 skb->dev = netdev;
862 skb_put(skb, pktlen);
863 if (trxd.rxd4 & checksum_bit) {
864 skb->ip_summed = CHECKSUM_UNNECESSARY;
865 } else {
866 skb_checksum_none_assert(skb);
867 }
868 if (rx_vlan)
869 fe_rx_vlan(skb);
870 skb->protocol = eth_type_trans(skb, netdev);
871
872 stats->rx_packets++;
873 stats->rx_bytes += pktlen;
874
875 napi_gro_receive(napi, skb);
876
877 ring->rx_data[idx] = new_data;
878 rxd->rxd1 = (unsigned int) dma_addr;
879
880 release_desc:
881 if (priv->flags & FE_FLAG_RX_SG_DMA)
882 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
883 else
884 rxd->rxd2 = RX_DMA_LSO;
885
886 ring->rx_calc_idx = idx;
887 wmb();
888 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
889 done++;
890 }
891
892 if (done < budget)
893 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
894
895 return done;
896 }
897
898 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
899 int *tx_again)
900 {
901 struct net_device *netdev = priv->netdev;
902 struct device *dev = &netdev->dev;
903 unsigned int bytes_compl = 0;
904 struct sk_buff *skb;
905 struct fe_tx_buf *tx_buf;
906 int done = 0;
907 u32 idx, hwidx;
908 struct fe_tx_ring *ring = &priv->tx_ring;
909
910 idx = ring->tx_free_idx;
911 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
912
913 while ((idx != hwidx) && budget) {
914 tx_buf = &ring->tx_buf[idx];
915 skb = tx_buf->skb;
916
917 if (!skb)
918 break;
919
920 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
921 bytes_compl += skb->len;
922 done++;
923 budget--;
924 }
925 fe_txd_unmap(dev, tx_buf);
926 idx = NEXT_TX_DESP_IDX(idx);
927 }
928 ring->tx_free_idx = idx;
929
930 if (idx == hwidx) {
931 /* read hw index again make sure no new tx packet */
932 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
933 if (idx == hwidx)
934 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
935 else
936 *tx_again = 1;
937 } else
938 *tx_again = 1;
939
940 if (done) {
941 netdev_completed_queue(netdev, done, bytes_compl);
942 smp_mb();
943 if (unlikely(netif_queue_stopped(netdev) &&
944 (fe_empty_txd(ring) > ring->tx_thresh)))
945 netif_wake_queue(netdev);
946 }
947
948 return done;
949 }
950
951 static int fe_poll(struct napi_struct *napi, int budget)
952 {
953 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
954 struct fe_hw_stats *hwstat = priv->hw_stats;
955 int tx_done, rx_done, tx_again;
956 u32 status, fe_status, status_reg, mask;
957 u32 tx_intr, rx_intr, status_intr;
958
959 fe_status = status = fe_reg_r32(FE_REG_FE_INT_STATUS);
960 tx_intr = priv->soc->tx_int;
961 rx_intr = priv->soc->rx_int;
962 status_intr = priv->soc->status_int;
963 tx_done = rx_done = tx_again = 0;
964
965 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
966 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
967 status_reg = FE_REG_FE_INT_STATUS2;
968 } else
969 status_reg = FE_REG_FE_INT_STATUS;
970
971 if (status & tx_intr)
972 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
973
974 if (status & rx_intr)
975 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
976
977 if (unlikely(fe_status & status_intr)) {
978 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
979 fe_stats_update(priv);
980 spin_unlock(&hwstat->stats_lock);
981 }
982 fe_reg_w32(status_intr, status_reg);
983 }
984
985 if (unlikely(netif_msg_intr(priv))) {
986 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
987 netdev_info(priv->netdev,
988 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
989 tx_done, rx_done, status, mask);
990 }
991
992 if (!tx_again && (rx_done < budget)) {
993 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
994 if (status & (tx_intr | rx_intr ))
995 goto poll_again;
996
997 napi_complete(napi);
998 fe_int_enable(tx_intr | rx_intr);
999 }
1000
1001 poll_again:
1002 return rx_done;
1003 }
1004
1005 static void fe_tx_timeout(struct net_device *dev)
1006 {
1007 struct fe_priv *priv = netdev_priv(dev);
1008 struct fe_tx_ring *ring = &priv->tx_ring;
1009
1010 priv->netdev->stats.tx_errors++;
1011 netif_err(priv, tx_err, dev,
1012 "transmit timed out\n");
1013 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1014 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1015 netif_info(priv, drv, dev, "tx_ring=%d, " \
1016 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n", 0,
1017 fe_reg_r32(FE_REG_TX_BASE_PTR0),
1018 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1019 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1020 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1021 ring->tx_free_idx,
1022 ring->tx_next_idx
1023 );
1024 netif_info(priv, drv, dev, "rx_ring=%d, " \
1025 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
1026 fe_reg_r32(FE_REG_RX_BASE_PTR0),
1027 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1028 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1029 fe_reg_r32(FE_REG_RX_DRX_IDX0)
1030 );
1031
1032 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1033 schedule_work(&priv->pending_work);
1034 }
1035
1036 static irqreturn_t fe_handle_irq(int irq, void *dev)
1037 {
1038 struct fe_priv *priv = netdev_priv(dev);
1039 u32 status, int_mask;
1040
1041 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1042
1043 if (unlikely(!status))
1044 return IRQ_NONE;
1045
1046 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1047 if (likely(status & int_mask)) {
1048 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1049 fe_int_disable(int_mask);
1050 __napi_schedule(&priv->rx_napi);
1051 }
1052 } else {
1053 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1054 }
1055
1056 return IRQ_HANDLED;
1057 }
1058
1059 #ifdef CONFIG_NET_POLL_CONTROLLER
1060 static void fe_poll_controller(struct net_device *dev)
1061 {
1062 struct fe_priv *priv = netdev_priv(dev);
1063 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1064
1065 fe_int_disable(int_mask);
1066 fe_handle_irq(dev->irq, dev);
1067 fe_int_enable(int_mask);
1068 }
1069 #endif
1070
1071 int fe_set_clock_cycle(struct fe_priv *priv)
1072 {
1073 unsigned long sysclk = priv->sysclk;
1074
1075 if (!sysclk) {
1076 return -EINVAL;
1077 }
1078
1079 sysclk /= FE_US_CYC_CNT_DIVISOR;
1080 sysclk <<= FE_US_CYC_CNT_SHIFT;
1081
1082 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1083 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1084 sysclk,
1085 FE_FE_GLO_CFG);
1086 return 0;
1087 }
1088
1089 void fe_fwd_config(struct fe_priv *priv)
1090 {
1091 u32 fwd_cfg;
1092
1093 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1094
1095 /* disable jumbo frame */
1096 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1097 fwd_cfg &= ~FE_GDM1_JMB_EN;
1098
1099 /* set unicast/multicast/broadcast frame to cpu */
1100 fwd_cfg &= ~0xffff;
1101
1102 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1103 }
1104
1105 static void fe_rxcsum_config(bool enable)
1106 {
1107 if (enable)
1108 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1109 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1110 FE_GDMA1_FWD_CFG);
1111 else
1112 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1113 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1114 FE_GDMA1_FWD_CFG);
1115 }
1116
1117 static void fe_txcsum_config(bool enable)
1118 {
1119 if (enable)
1120 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1121 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1122 FE_CDMA_CSG_CFG);
1123 else
1124 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1125 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1126 FE_CDMA_CSG_CFG);
1127 }
1128
1129 void fe_csum_config(struct fe_priv *priv)
1130 {
1131 struct net_device *dev = priv_netdev(priv);
1132
1133 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1134 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1135 }
1136
1137 static int fe_hw_init(struct net_device *dev)
1138 {
1139 struct fe_priv *priv = netdev_priv(dev);
1140 int i, err;
1141
1142 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1143 dev_name(priv->device), dev);
1144 if (err)
1145 return err;
1146
1147 if (priv->soc->set_mac)
1148 priv->soc->set_mac(priv, dev->dev_addr);
1149 else
1150 fe_hw_set_macaddr(priv, dev->dev_addr);
1151
1152 /* disable delay interrupt */
1153 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1154
1155 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1156
1157 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1158 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1159 for (i = 0; i < 16; i += 2)
1160 fe_w32(((i + 1) << 16) + i,
1161 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1162 (i * 2));
1163
1164 BUG_ON(!priv->soc->fwd_config);
1165 if (priv->soc->fwd_config(priv))
1166 netdev_err(dev, "unable to get clock\n");
1167
1168 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1169 fe_reg_w32(1, FE_REG_FE_RST_GL);
1170 fe_reg_w32(0, FE_REG_FE_RST_GL);
1171 }
1172
1173 return 0;
1174 }
1175
1176 static int fe_open(struct net_device *dev)
1177 {
1178 struct fe_priv *priv = netdev_priv(dev);
1179 unsigned long flags;
1180 u32 val;
1181 int err;
1182
1183 err = fe_init_dma(priv);
1184 if (err)
1185 goto err_out;
1186
1187 spin_lock_irqsave(&priv->page_lock, flags);
1188
1189 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1190 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1191 val |= FE_RX_2B_OFFSET;
1192 val |= priv->soc->pdma_glo_cfg;
1193 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1194
1195 spin_unlock_irqrestore(&priv->page_lock, flags);
1196
1197 if (priv->phy)
1198 priv->phy->start(priv);
1199
1200 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1201 netif_carrier_on(dev);
1202
1203 napi_enable(&priv->rx_napi);
1204 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1205 netif_start_queue(dev);
1206
1207 return 0;
1208
1209 err_out:
1210 fe_free_dma(priv);
1211 return err;
1212 }
1213
1214 static int fe_stop(struct net_device *dev)
1215 {
1216 struct fe_priv *priv = netdev_priv(dev);
1217 unsigned long flags;
1218 int i;
1219
1220 netif_tx_disable(dev);
1221 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1222 napi_disable(&priv->rx_napi);
1223
1224 if (priv->phy)
1225 priv->phy->stop(priv);
1226
1227 spin_lock_irqsave(&priv->page_lock, flags);
1228
1229 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1230 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1231 FE_REG_PDMA_GLO_CFG);
1232 spin_unlock_irqrestore(&priv->page_lock, flags);
1233
1234 /* wait dma stop */
1235 for (i = 0; i < 10; i++) {
1236 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1237 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1238 msleep(10);
1239 continue;
1240 }
1241 break;
1242 }
1243
1244 fe_free_dma(priv);
1245
1246 return 0;
1247 }
1248
1249 static int __init fe_init(struct net_device *dev)
1250 {
1251 struct fe_priv *priv = netdev_priv(dev);
1252 struct device_node *port;
1253 int err;
1254
1255 BUG_ON(!priv->soc->reset_fe);
1256 priv->soc->reset_fe();
1257
1258 if (priv->soc->switch_init)
1259 priv->soc->switch_init(priv);
1260
1261 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1262 /*If the mac address is invalid, use random mac address */
1263 if (!is_valid_ether_addr(dev->dev_addr)) {
1264 random_ether_addr(dev->dev_addr);
1265 dev_err(priv->device, "generated random MAC address %pM\n",
1266 dev->dev_addr);
1267 }
1268
1269 err = fe_mdio_init(priv);
1270 if (err)
1271 return err;
1272
1273 if (priv->soc->port_init)
1274 for_each_child_of_node(priv->device->of_node, port)
1275 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1276 priv->soc->port_init(priv, port);
1277
1278 if (priv->phy) {
1279 err = priv->phy->connect(priv);
1280 if (err)
1281 goto err_phy_disconnect;
1282 }
1283
1284 err = fe_hw_init(dev);
1285 if (err)
1286 goto err_phy_disconnect;
1287
1288 if (priv->soc->switch_config)
1289 priv->soc->switch_config(priv);
1290
1291 return 0;
1292
1293 err_phy_disconnect:
1294 if (priv->phy)
1295 priv->phy->disconnect(priv);
1296 fe_mdio_cleanup(priv);
1297
1298 return err;
1299 }
1300
1301 static void fe_uninit(struct net_device *dev)
1302 {
1303 struct fe_priv *priv = netdev_priv(dev);
1304
1305 if (priv->phy)
1306 priv->phy->disconnect(priv);
1307 fe_mdio_cleanup(priv);
1308
1309 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1310 free_irq(dev->irq, dev);
1311 }
1312
1313 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1314 {
1315 struct fe_priv *priv = netdev_priv(dev);
1316
1317 if (!priv->phy_dev)
1318 return -ENODEV;
1319
1320 switch (cmd) {
1321 case SIOCETHTOOL:
1322 return phy_ethtool_ioctl(priv->phy_dev,
1323 (void *) ifr->ifr_data);
1324 case SIOCGMIIPHY:
1325 case SIOCGMIIREG:
1326 case SIOCSMIIREG:
1327 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1328 default:
1329 break;
1330 }
1331
1332 return -EOPNOTSUPP;
1333 }
1334
1335 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1336 {
1337 struct fe_priv *priv = netdev_priv(dev);
1338 int frag_size, old_mtu;
1339 u32 fwd_cfg;
1340
1341 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1342 return eth_change_mtu(dev, new_mtu);
1343
1344 frag_size = fe_max_frag_size(new_mtu);
1345 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1346 return -EINVAL;
1347
1348 old_mtu = dev->mtu;
1349 dev->mtu = new_mtu;
1350
1351 /* return early if the buffer sizes will not change */
1352 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1353 return 0;
1354 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1355 return 0;
1356
1357 if (new_mtu <= ETH_DATA_LEN)
1358 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1359 else
1360 priv->rx_ring.frag_size = PAGE_SIZE;
1361 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1362
1363 if (!netif_running(dev))
1364 return 0;
1365
1366 fe_stop(dev);
1367 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1368 if (new_mtu <= ETH_DATA_LEN)
1369 fwd_cfg &= ~FE_GDM1_JMB_EN;
1370 else {
1371 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1372 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1373 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1374 }
1375 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1376
1377 return fe_open(dev);
1378 }
1379
1380 static const struct net_device_ops fe_netdev_ops = {
1381 .ndo_init = fe_init,
1382 .ndo_uninit = fe_uninit,
1383 .ndo_open = fe_open,
1384 .ndo_stop = fe_stop,
1385 .ndo_start_xmit = fe_start_xmit,
1386 .ndo_set_mac_address = fe_set_mac_address,
1387 .ndo_validate_addr = eth_validate_addr,
1388 .ndo_do_ioctl = fe_do_ioctl,
1389 .ndo_change_mtu = fe_change_mtu,
1390 .ndo_tx_timeout = fe_tx_timeout,
1391 .ndo_get_stats64 = fe_get_stats64,
1392 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1393 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1394 #ifdef CONFIG_NET_POLL_CONTROLLER
1395 .ndo_poll_controller = fe_poll_controller,
1396 #endif
1397 };
1398
1399 static void fe_reset_pending(struct fe_priv *priv)
1400 {
1401 struct net_device *dev = priv->netdev;
1402 int err;
1403
1404 rtnl_lock();
1405 fe_stop(dev);
1406
1407 err = fe_open(dev);
1408 if (err)
1409 goto error;
1410 rtnl_unlock();
1411
1412 return;
1413 error:
1414 netif_alert(priv, ifup, dev,
1415 "Driver up/down cycle failed, closing device.\n");
1416 dev_close(dev);
1417 rtnl_unlock();
1418 }
1419
1420 static const struct fe_work_t fe_work[] = {
1421 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1422 };
1423
1424 static void fe_pending_work(struct work_struct *work)
1425 {
1426 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1427 int i;
1428 bool pending;
1429
1430 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1431 pending = test_and_clear_bit(fe_work[i].bitnr,
1432 priv->pending_flags);
1433 if (pending)
1434 fe_work[i].action(priv);
1435 }
1436 }
1437
1438 static int fe_probe(struct platform_device *pdev)
1439 {
1440 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1441 const struct of_device_id *match;
1442 struct fe_soc_data *soc;
1443 struct net_device *netdev;
1444 struct fe_priv *priv;
1445 struct clk *sysclk;
1446 int err, napi_weight;
1447
1448 device_reset(&pdev->dev);
1449
1450 match = of_match_device(of_fe_match, &pdev->dev);
1451 soc = (struct fe_soc_data *) match->data;
1452
1453 if (soc->reg_table)
1454 fe_reg_table = soc->reg_table;
1455 else
1456 soc->reg_table = fe_reg_table;
1457
1458 fe_base = devm_ioremap_resource(&pdev->dev, res);
1459 if (!fe_base) {
1460 err = -EADDRNOTAVAIL;
1461 goto err_out;
1462 }
1463
1464 netdev = alloc_etherdev(sizeof(*priv));
1465 if (!netdev) {
1466 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1467 err = -ENOMEM;
1468 goto err_iounmap;
1469 }
1470
1471 SET_NETDEV_DEV(netdev, &pdev->dev);
1472 netdev->netdev_ops = &fe_netdev_ops;
1473 netdev->base_addr = (unsigned long) fe_base;
1474
1475 netdev->irq = platform_get_irq(pdev, 0);
1476 if (netdev->irq < 0) {
1477 dev_err(&pdev->dev, "no IRQ resource found\n");
1478 err = -ENXIO;
1479 goto err_free_dev;
1480 }
1481
1482 if (soc->init_data)
1483 soc->init_data(soc, netdev);
1484 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1485 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1486 netdev->vlan_features = netdev->hw_features &
1487 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1488 netdev->features |= netdev->hw_features;
1489
1490 /* fake rx vlan filter func. to support tx vlan offload func */
1491 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1492 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1493
1494 priv = netdev_priv(netdev);
1495 spin_lock_init(&priv->page_lock);
1496 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1497 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1498 if (!priv->hw_stats) {
1499 err = -ENOMEM;
1500 goto err_free_dev;
1501 }
1502 spin_lock_init(&priv->hw_stats->stats_lock);
1503 }
1504
1505 sysclk = devm_clk_get(&pdev->dev, NULL);
1506 if (!IS_ERR(sysclk))
1507 priv->sysclk = clk_get_rate(sysclk);
1508
1509 priv->netdev = netdev;
1510 priv->device = &pdev->dev;
1511 priv->soc = soc;
1512 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1513 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1514 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1515 priv->tx_ring.tx_ring_size = priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1516 INIT_WORK(&priv->pending_work, fe_pending_work);
1517
1518 napi_weight = 32;
1519 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1520 napi_weight *= 4;
1521 priv->tx_ring.tx_ring_size *= 4;
1522 priv->rx_ring.rx_ring_size *= 4;
1523 }
1524 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1525 fe_set_ethtool_ops(netdev);
1526
1527 err = register_netdev(netdev);
1528 if (err) {
1529 dev_err(&pdev->dev, "error bringing up device\n");
1530 goto err_free_dev;
1531 }
1532
1533 platform_set_drvdata(pdev, netdev);
1534
1535 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1536 netdev->base_addr, netdev->irq);
1537
1538 return 0;
1539
1540 err_free_dev:
1541 free_netdev(netdev);
1542 err_iounmap:
1543 devm_iounmap(&pdev->dev, fe_base);
1544 err_out:
1545 return err;
1546 }
1547
1548 static int fe_remove(struct platform_device *pdev)
1549 {
1550 struct net_device *dev = platform_get_drvdata(pdev);
1551 struct fe_priv *priv = netdev_priv(dev);
1552
1553 netif_napi_del(&priv->rx_napi);
1554 if (priv->hw_stats)
1555 kfree(priv->hw_stats);
1556
1557 cancel_work_sync(&priv->pending_work);
1558
1559 unregister_netdev(dev);
1560 free_netdev(dev);
1561 platform_set_drvdata(pdev, NULL);
1562
1563 return 0;
1564 }
1565
1566 static struct platform_driver fe_driver = {
1567 .probe = fe_probe,
1568 .remove = fe_remove,
1569 .driver = {
1570 .name = "ralink_soc_eth",
1571 .owner = THIS_MODULE,
1572 .of_match_table = of_fe_match,
1573 },
1574 };
1575
1576 static int __init init_rtfe(void)
1577 {
1578 int ret;
1579
1580 ret = rtesw_init();
1581 if (ret)
1582 return ret;
1583
1584 ret = platform_driver_register(&fe_driver);
1585 if (ret)
1586 rtesw_exit();
1587
1588 return ret;
1589 }
1590
1591 static void __exit exit_rtfe(void)
1592 {
1593 platform_driver_unregister(&fe_driver);
1594 rtesw_exit();
1595 }
1596
1597 module_init(init_rtfe);
1598 module_exit(exit_rtfe);
1599
1600 MODULE_LICENSE("GPL");
1601 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1602 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1603 MODULE_VERSION(FE_DRV_VERSION);
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