068366a7c6946613841dcb631e10a7c04104d8ba
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define TX_TIMEOUT (2 * HZ)
44 #define MAX_RX_LENGTH 1536
45 #define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
46 #define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
47 ETH_FCS_LEN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u32 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
79 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
80 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
81 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
82 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
83 };
84
85 static const u32 *fe_reg_table = fe_reg_table_default;
86
87 static void __iomem *fe_base = 0;
88
89 void fe_w32(u32 val, unsigned reg)
90 {
91 __raw_writel(val, fe_base + reg);
92 }
93
94 u32 fe_r32(unsigned reg)
95 {
96 return __raw_readl(fe_base + reg);
97 }
98
99 void fe_reg_w32(u32 val, enum fe_reg reg)
100 {
101 fe_w32(val, fe_reg_table[reg]);
102 }
103
104 u32 fe_reg_r32(enum fe_reg reg)
105 {
106 return fe_r32(fe_reg_table[reg]);
107 }
108
109 static inline void fe_int_disable(u32 mask)
110 {
111 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
112 FE_REG_FE_INT_ENABLE);
113 /* flush write */
114 fe_reg_r32(FE_REG_FE_INT_ENABLE);
115 }
116
117 static inline void fe_int_enable(u32 mask)
118 {
119 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
120 FE_REG_FE_INT_ENABLE);
121 /* flush write */
122 fe_reg_r32(FE_REG_FE_INT_ENABLE);
123 }
124
125 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
126 {
127 unsigned long flags;
128
129 spin_lock_irqsave(&priv->page_lock, flags);
130 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
131 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
132 FE_GDMA1_MAC_ADRL);
133 spin_unlock_irqrestore(&priv->page_lock, flags);
134 }
135
136 static int fe_set_mac_address(struct net_device *dev, void *p)
137 {
138 int ret = eth_mac_addr(dev, p);
139
140 if (!ret) {
141 struct fe_priv *priv = netdev_priv(dev);
142
143 if (priv->soc->set_mac)
144 priv->soc->set_mac(priv, dev->dev_addr);
145 else
146 fe_hw_set_macaddr(priv, p);
147 }
148
149 return ret;
150 }
151
152 static inline int fe_max_frag_size(int mtu)
153 {
154 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
155 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
156 }
157
158 static inline int fe_max_buf_size(int frag_size)
159 {
160 return frag_size - FE_RX_HLEN -
161 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
162 }
163
164 static void fe_clean_rx(struct fe_priv *priv)
165 {
166 int i;
167
168 if (priv->rx_data) {
169 for (i = 0; i < NUM_DMA_DESC; i++)
170 if (priv->rx_data[i]) {
171 if (priv->rx_dma && priv->rx_dma[i].rxd1)
172 dma_unmap_single(&priv->netdev->dev,
173 priv->rx_dma[i].rxd1,
174 priv->rx_buf_size,
175 DMA_FROM_DEVICE);
176 put_page(virt_to_head_page(priv->rx_data[i]));
177 }
178
179 kfree(priv->rx_data);
180 priv->rx_data = NULL;
181 }
182
183 if (priv->rx_dma) {
184 dma_free_coherent(&priv->netdev->dev,
185 NUM_DMA_DESC * sizeof(*priv->rx_dma),
186 priv->rx_dma,
187 priv->rx_phys);
188 priv->rx_dma = NULL;
189 }
190 }
191
192 static int fe_alloc_rx(struct fe_priv *priv)
193 {
194 struct net_device *netdev = priv->netdev;
195 int i;
196
197 priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
198 GFP_KERNEL);
199 if (!priv->rx_data)
200 goto no_rx_mem;
201
202 for (i = 0; i < NUM_DMA_DESC; i++) {
203 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
204 if (!priv->rx_data[i])
205 goto no_rx_mem;
206 }
207
208 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
209 NUM_DMA_DESC * sizeof(*priv->rx_dma),
210 &priv->rx_phys,
211 GFP_ATOMIC | __GFP_ZERO);
212 if (!priv->rx_dma)
213 goto no_rx_mem;
214
215 for (i = 0; i < NUM_DMA_DESC; i++) {
216 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
217 priv->rx_data[i] + FE_RX_OFFSET,
218 priv->rx_buf_size,
219 DMA_FROM_DEVICE);
220 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
221 goto no_rx_mem;
222 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
223
224 if (priv->soc->rx_dma)
225 priv->soc->rx_dma(priv, i, priv->rx_buf_size);
226 else
227 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
228 }
229 wmb();
230
231 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
232 fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
233 fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
234 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
235
236 return 0;
237
238 no_rx_mem:
239 return -ENOMEM;
240 }
241
242 static void fe_clean_tx(struct fe_priv *priv)
243 {
244 int i;
245
246 if (priv->tx_skb) {
247 for (i = 0; i < NUM_DMA_DESC; i++) {
248 if (priv->tx_skb[i])
249 dev_kfree_skb_any(priv->tx_skb[i]);
250 }
251 kfree(priv->tx_skb);
252 priv->tx_skb = NULL;
253 }
254
255 if (priv->tx_dma) {
256 dma_free_coherent(&priv->netdev->dev,
257 NUM_DMA_DESC * sizeof(*priv->tx_dma),
258 priv->tx_dma,
259 priv->tx_phys);
260 priv->tx_dma = NULL;
261 }
262 }
263
264 static int fe_alloc_tx(struct fe_priv *priv)
265 {
266 int i;
267
268 priv->tx_free_idx = 0;
269
270 priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
271 GFP_KERNEL);
272 if (!priv->tx_skb)
273 goto no_tx_mem;
274
275 priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
276 NUM_DMA_DESC * sizeof(*priv->tx_dma),
277 &priv->tx_phys,
278 GFP_ATOMIC | __GFP_ZERO);
279 if (!priv->tx_dma)
280 goto no_tx_mem;
281
282 for (i = 0; i < NUM_DMA_DESC; i++) {
283 if (priv->soc->tx_dma) {
284 priv->soc->tx_dma(priv, i, NULL);
285 continue;
286 }
287 priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
288 }
289 wmb();
290
291 fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
292 fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
293 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
294 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
295
296 return 0;
297
298 no_tx_mem:
299 return -ENOMEM;
300 }
301
302 static int fe_init_dma(struct fe_priv *priv)
303 {
304 int err;
305
306 err = fe_alloc_tx(priv);
307 if (err)
308 return err;
309
310 err = fe_alloc_rx(priv);
311 if (err)
312 return err;
313
314 return 0;
315 }
316
317 static void fe_free_dma(struct fe_priv *priv)
318 {
319 fe_clean_tx(priv);
320 fe_clean_rx(priv);
321
322 netdev_reset_queue(priv->netdev);
323 }
324
325 static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
326 {
327 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
328 dma_unmap_single(dev, txd->txd1,
329 TX_DMA_GET_PLEN0(txd->txd2),
330 DMA_TO_DEVICE);
331 }
332
333 static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
334 {
335 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
336 dma_unmap_page(dev, txd->txd1,
337 TX_DMA_GET_PLEN0(txd->txd2),
338 DMA_TO_DEVICE);
339 }
340
341 static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
342 {
343 if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
344 dma_unmap_page(dev, txd->txd3,
345 TX_DMA_GET_PLEN1(txd->txd2),
346 DMA_TO_DEVICE);
347 }
348
349 void fe_stats_update(struct fe_priv *priv)
350 {
351 struct fe_hw_stats *hwstats = priv->hw_stats;
352 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
353
354 u64_stats_update_begin(&hwstats->syncp);
355
356 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
357 hwstats->rx_bytes += fe_r32(base);
358 hwstats->rx_packets += fe_r32(base + 0x08);
359 hwstats->rx_overflow += fe_r32(base + 0x10);
360 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
361 hwstats->rx_short_errors += fe_r32(base + 0x18);
362 hwstats->rx_long_errors += fe_r32(base + 0x1c);
363 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
364 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
365 hwstats->tx_skip += fe_r32(base + 0x28);
366 hwstats->tx_collisions += fe_r32(base + 0x2c);
367 hwstats->tx_bytes += fe_r32(base + 0x30);
368 hwstats->tx_packets += fe_r32(base + 0x38);
369 } else {
370 hwstats->tx_bytes += fe_r32(base);
371 hwstats->tx_packets += fe_r32(base + 0x04);
372 hwstats->tx_skip += fe_r32(base + 0x08);
373 hwstats->tx_collisions += fe_r32(base + 0x0c);
374 hwstats->rx_bytes += fe_r32(base + 0x20);
375 hwstats->rx_packets += fe_r32(base + 0x24);
376 hwstats->rx_overflow += fe_r32(base + 0x28);
377 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
378 hwstats->rx_short_errors += fe_r32(base + 0x30);
379 hwstats->rx_long_errors += fe_r32(base + 0x34);
380 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
381 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
382 }
383
384 u64_stats_update_end(&hwstats->syncp);
385 }
386
387 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
388 struct rtnl_link_stats64 *storage)
389 {
390 struct fe_priv *priv = netdev_priv(dev);
391 struct fe_hw_stats *hwstats = priv->hw_stats;
392 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
393 unsigned int start;
394
395 if (!base) {
396 netdev_stats_to_stats64(storage, &dev->stats);
397 return storage;
398 }
399
400 if (netif_running(dev) && netif_device_present(dev)) {
401 if (spin_trylock(&hwstats->stats_lock)) {
402 fe_stats_update(priv);
403 spin_unlock(&hwstats->stats_lock);
404 }
405 }
406
407 do {
408 start = u64_stats_fetch_begin_bh(&hwstats->syncp);
409 storage->rx_packets = hwstats->rx_packets;
410 storage->tx_packets = hwstats->tx_packets;
411 storage->rx_bytes = hwstats->rx_bytes;
412 storage->tx_bytes = hwstats->tx_bytes;
413 storage->collisions = hwstats->tx_collisions;
414 storage->rx_length_errors = hwstats->rx_short_errors +
415 hwstats->rx_long_errors;
416 storage->rx_over_errors = hwstats->rx_overflow;
417 storage->rx_crc_errors = hwstats->rx_fcs_errors;
418 storage->rx_errors = hwstats->rx_checksum_errors;
419 storage->tx_aborted_errors = hwstats->tx_skip;
420 } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
421
422 storage->tx_errors = priv->netdev->stats.tx_errors;
423 storage->rx_dropped = priv->netdev->stats.rx_dropped;
424 storage->tx_dropped = priv->netdev->stats.tx_dropped;
425
426 return storage;
427 }
428
429 static int fe_vlan_rx_add_vid(struct net_device *dev,
430 __be16 proto, u16 vid)
431 {
432 struct fe_priv *priv = netdev_priv(dev);
433 u32 idx = (vid & 0xf);
434 u32 vlan_cfg;
435
436 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
437 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
438 return 0;
439
440 if (test_bit(idx, &priv->vlan_map)) {
441 netdev_warn(dev, "disable tx vlan offload\n");
442 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
443 netdev_update_features(dev);
444 } else {
445 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
446 ((idx >> 1) << 2));
447 if (idx & 0x1) {
448 vlan_cfg &= 0xffff;
449 vlan_cfg |= (vid << 16);
450 } else {
451 vlan_cfg &= 0xffff0000;
452 vlan_cfg |= vid;
453 }
454 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
455 ((idx >> 1) << 2));
456 set_bit(idx, &priv->vlan_map);
457 }
458
459 return 0;
460 }
461
462 static int fe_vlan_rx_kill_vid(struct net_device *dev,
463 __be16 proto, u16 vid)
464 {
465 struct fe_priv *priv = netdev_priv(dev);
466 u32 idx = (vid & 0xf);
467
468 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
469 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
470 return 0;
471
472 clear_bit(idx, &priv->vlan_map);
473
474 return 0;
475 }
476
477 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
478 int idx)
479 {
480 struct fe_priv *priv = netdev_priv(dev);
481 struct skb_frag_struct *frag;
482 struct fe_tx_dma *txd;
483 dma_addr_t mapped_addr;
484 unsigned int nr_frags;
485 u32 def_txd4, txd2;
486 int i, j, unmap_idx, tx_num;
487
488 txd = &priv->tx_dma[idx];
489 nr_frags = skb_shinfo(skb)->nr_frags;
490 tx_num = 1 + (nr_frags >> 1);
491
492 /* init tx descriptor */
493 if (priv->soc->tx_dma)
494 priv->soc->tx_dma(priv, idx, skb);
495 else
496 txd->txd4 = TX_DMA_DESP4_DEF;
497 def_txd4 = txd->txd4;
498
499 /* use dma_unmap_single to free it */
500 txd->txd4 |= priv->soc->tx_udf_bit;
501
502 /* TX Checksum offload */
503 if (skb->ip_summed == CHECKSUM_PARTIAL)
504 txd->txd4 |= TX_DMA_CHKSUM;
505
506 /* VLAN header offload */
507 if (vlan_tx_tag_present(skb)) {
508 if (IS_ENABLED(CONFIG_SOC_MT7621))
509 txd->txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
510 else
511 txd->txd4 |= TX_DMA_INS_VLAN |
512 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
513 (vlan_tx_tag_get(skb) & 0xF);
514 }
515
516 /* TSO: fill MSS info in tcp checksum field */
517 if (skb_is_gso(skb)) {
518 if (skb_cow_head(skb, 0)) {
519 netif_warn(priv, tx_err, dev,
520 "GSO expand head fail.\n");
521 goto err_out;
522 }
523 if (skb_shinfo(skb)->gso_type &
524 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
525 txd->txd4 |= TX_DMA_TSO;
526 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
527 }
528 }
529
530 mapped_addr = dma_map_single(&dev->dev, skb->data,
531 skb_headlen(skb), DMA_TO_DEVICE);
532 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
533 goto err_out;
534 txd->txd1 = mapped_addr;
535 txd2 = TX_DMA_PLEN0(skb_headlen(skb));
536
537 /* TX SG offload */
538 j = idx;
539 for (i = 0; i < nr_frags; i++) {
540
541 frag = &skb_shinfo(skb)->frags[i];
542 mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
543 skb_frag_size(frag), DMA_TO_DEVICE);
544 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
545 goto err_dma;
546
547 if (i & 0x1) {
548 j = NEXT_TX_DESP_IDX(j);
549 txd = &priv->tx_dma[j];
550 txd->txd1 = mapped_addr;
551 txd2 = TX_DMA_PLEN0(frag->size);
552 txd->txd4 = def_txd4;
553 } else {
554 txd->txd3 = mapped_addr;
555 txd2 |= TX_DMA_PLEN1(frag->size);
556 if (i != (nr_frags -1))
557 txd->txd2 = txd2;
558 priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
559 }
560 }
561
562 /* set last segment */
563 if (nr_frags & 0x1)
564 txd->txd2 = (txd2 | TX_DMA_LS1);
565 else
566 txd->txd2 = (txd2 | TX_DMA_LS0);
567
568 /* store skb to cleanup */
569 priv->tx_skb[j] = skb;
570
571 wmb();
572 j = NEXT_TX_DESP_IDX(j);
573 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
574
575 return 0;
576
577 err_dma:
578 /* unmap dma */
579 txd = &priv->tx_dma[idx];
580 txd_unmap_single(&dev->dev, txd);
581
582 j = idx;
583 unmap_idx = i;
584 for (i = 0; i < unmap_idx; i++) {
585 if (i & 0x1) {
586 j = NEXT_TX_DESP_IDX(j);
587 txd = &priv->tx_dma[j];
588 txd_unmap_page0(&dev->dev, txd);
589 } else {
590 txd_unmap_page1(&dev->dev, txd);
591 }
592 }
593
594 err_out:
595 /* reinit descriptors and skb */
596 j = idx;
597 for (i = 0; i < tx_num; i++) {
598 priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
599 priv->tx_skb[j] = NULL;
600 j = NEXT_TX_DESP_IDX(j);
601 }
602 wmb();
603
604 return -1;
605 }
606
607 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
608 unsigned int len;
609 int ret;
610
611 ret = 0;
612 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
613 if ((priv->flags & FE_FLAG_PADDING_64B) &&
614 !(priv->flags & FE_FLAG_PADDING_BUG))
615 return ret;
616
617 if (vlan_tx_tag_present(skb))
618 len = ETH_ZLEN;
619 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
620 len = VLAN_ETH_ZLEN;
621 else if(!(priv->flags & FE_FLAG_PADDING_64B))
622 len = ETH_ZLEN;
623 else
624 return ret;
625
626 if (skb->len < len) {
627 if ((ret = skb_pad(skb, len - skb->len)) < 0)
628 return ret;
629 skb->len = len;
630 skb_set_tail_pointer(skb, len);
631 }
632 }
633
634 return ret;
635 }
636
637 static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
638 {
639 return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
640 (NUM_DMA_DESC - 1)));
641 }
642
643 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
644 {
645 struct fe_priv *priv = netdev_priv(dev);
646 struct net_device_stats *stats = &dev->stats;
647 u32 tx;
648 int tx_num;
649
650 if (fe_skb_padto(skb, priv)) {
651 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
652 return NETDEV_TX_OK;
653 }
654
655 spin_lock(&priv->page_lock);
656 tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
657 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
658 if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
659 {
660 netif_stop_queue(dev);
661 spin_unlock(&priv->page_lock);
662 netif_err(priv, tx_queued,dev,
663 "Tx Ring full when queue awake!\n");
664 return NETDEV_TX_BUSY;
665 }
666
667 if (fe_tx_map_dma(skb, dev, tx) < 0) {
668 kfree_skb(skb);
669
670 stats->tx_dropped++;
671 } else {
672 netdev_sent_queue(dev, skb->len);
673 skb_tx_timestamp(skb);
674
675 stats->tx_packets++;
676 stats->tx_bytes += skb->len;
677 }
678
679 spin_unlock(&priv->page_lock);
680
681 return NETDEV_TX_OK;
682 }
683
684 static inline void fe_rx_vlan(struct sk_buff *skb)
685 {
686 struct ethhdr *ehdr;
687 u16 vlanid;
688
689 if (!__vlan_get_tag(skb, &vlanid)) {
690 /* pop the vlan tag */
691 ehdr = (struct ethhdr *)skb->data;
692 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
693 skb_pull(skb, VLAN_HLEN);
694 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
695 }
696 }
697
698 static int fe_poll_rx(struct napi_struct *napi, int budget,
699 struct fe_priv *priv)
700 {
701 struct net_device *netdev = priv->netdev;
702 struct net_device_stats *stats = &netdev->stats;
703 struct fe_soc_data *soc = priv->soc;
704 u32 checksum_bit;
705 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
706 struct sk_buff *skb;
707 u8 *data, *new_data;
708 struct fe_rx_dma *rxd;
709 int done = 0;
710 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
711
712 if (netdev->features & NETIF_F_RXCSUM)
713 checksum_bit = soc->checksum_bit;
714 else
715 checksum_bit = 0;
716
717 while (done < budget) {
718 unsigned int pktlen;
719 dma_addr_t dma_addr;
720 idx = NEXT_RX_DESP_IDX(idx);
721 rxd = &priv->rx_dma[idx];
722 data = priv->rx_data[idx];
723
724 if (!(rxd->rxd2 & RX_DMA_DONE))
725 break;
726
727 /* alloc new buffer */
728 new_data = netdev_alloc_frag(priv->frag_size);
729 if (unlikely(!new_data)) {
730 stats->rx_dropped++;
731 goto release_desc;
732 }
733 dma_addr = dma_map_single(&netdev->dev,
734 new_data + FE_RX_OFFSET,
735 priv->rx_buf_size,
736 DMA_FROM_DEVICE);
737 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
738 put_page(virt_to_head_page(new_data));
739 goto release_desc;
740 }
741
742 /* receive data */
743 skb = build_skb(data, priv->frag_size);
744 if (unlikely(!skb)) {
745 put_page(virt_to_head_page(new_data));
746 goto release_desc;
747 }
748 skb_reserve(skb, FE_RX_OFFSET);
749
750 dma_unmap_single(&netdev->dev, rxd->rxd1,
751 priv->rx_buf_size, DMA_FROM_DEVICE);
752 pktlen = RX_DMA_PLEN0(rxd->rxd2);
753 skb_put(skb, pktlen);
754 skb->dev = netdev;
755 if (rxd->rxd4 & checksum_bit) {
756 skb->ip_summed = CHECKSUM_UNNECESSARY;
757 } else {
758 skb_checksum_none_assert(skb);
759 }
760 if (rx_vlan)
761 fe_rx_vlan(skb);
762 skb->protocol = eth_type_trans(skb, netdev);
763
764 stats->rx_packets++;
765 stats->rx_bytes += pktlen;
766
767 if (skb->ip_summed == CHECKSUM_NONE)
768 netif_receive_skb(skb);
769 else
770 napi_gro_receive(napi, skb);
771
772 priv->rx_data[idx] = new_data;
773 rxd->rxd1 = (unsigned int) dma_addr;
774
775 release_desc:
776 if (soc->rx_dma)
777 soc->rx_dma(priv, idx, priv->rx_buf_size);
778 else
779 rxd->rxd2 = RX_DMA_LSO;
780
781 wmb();
782 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
783 done++;
784 }
785
786 return done;
787 }
788
789 static int fe_poll_tx(struct fe_priv *priv, int budget)
790 {
791 struct net_device *netdev = priv->netdev;
792 struct device *dev = &netdev->dev;
793 unsigned int bytes_compl = 0;
794 struct sk_buff *skb;
795 struct fe_tx_dma *txd;
796 int done = 0, idx;
797 u32 udf_bit = priv->soc->tx_udf_bit;
798
799 idx = priv->tx_free_idx;
800 while (done < budget) {
801 txd = &priv->tx_dma[idx];
802 skb = priv->tx_skb[idx];
803
804 if (!(txd->txd2 & TX_DMA_DONE) || !skb)
805 break;
806
807 txd_unmap_page1(dev, txd);
808
809 if (txd->txd4 & udf_bit)
810 txd_unmap_single(dev, txd);
811 else
812 txd_unmap_page0(dev, txd);
813
814 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
815 bytes_compl += skb->len;
816 dev_kfree_skb_any(skb);
817 done++;
818 }
819 priv->tx_skb[idx] = NULL;
820 idx = NEXT_TX_DESP_IDX(idx);
821 }
822 priv->tx_free_idx = idx;
823
824 if (!done)
825 return 0;
826
827 netdev_completed_queue(netdev, done, bytes_compl);
828 if (unlikely(netif_queue_stopped(netdev) &&
829 netif_carrier_ok(netdev))) {
830 netif_wake_queue(netdev);
831 }
832
833 return done;
834 }
835
836 static int fe_poll(struct napi_struct *napi, int budget)
837 {
838 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
839 struct fe_hw_stats *hwstat = priv->hw_stats;
840 int tx_done, rx_done;
841 u32 status, mask;
842 u32 tx_intr, rx_intr;
843
844 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
845 tx_intr = priv->soc->tx_dly_int;
846 rx_intr = priv->soc->rx_dly_int;
847 tx_done = rx_done = 0;
848
849 poll_again:
850 if (status & tx_intr) {
851 tx_done += fe_poll_tx(priv, budget - tx_done);
852 if (tx_done < budget) {
853 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
854 }
855 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
856 }
857
858 if (status & rx_intr) {
859 rx_done += fe_poll_rx(napi, budget - rx_done, priv);
860 if (rx_done < budget) {
861 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
862 }
863 }
864
865 if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
866 if (spin_trylock(&hwstat->stats_lock)) {
867 fe_stats_update(priv);
868 spin_unlock(&hwstat->stats_lock);
869 }
870 fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
871 }
872
873 if (unlikely(netif_msg_intr(priv))) {
874 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
875 netdev_info(priv->netdev,
876 "done tx %d, rx %d, intr 0x%x/0x%x\n",
877 tx_done, rx_done, status, mask);
878 }
879
880 if ((tx_done < budget) && (rx_done < budget)) {
881 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
882 if (status & (tx_intr | rx_intr )) {
883 goto poll_again;
884 }
885 napi_complete(napi);
886 fe_int_enable(tx_intr | rx_intr);
887 }
888
889 return rx_done;
890 }
891
892 static void fe_tx_timeout(struct net_device *dev)
893 {
894 struct fe_priv *priv = netdev_priv(dev);
895
896 priv->netdev->stats.tx_errors++;
897 netif_err(priv, tx_err, dev,
898 "transmit timed out, waking up the queue\n");
899 netif_info(priv, drv, dev, ": dma_cfg:%08x, free_idx:%d, " \
900 "dma_ctx_idx=%u, dma_crx_idx=%u\n",
901 fe_reg_r32(FE_REG_PDMA_GLO_CFG), priv->tx_free_idx,
902 fe_reg_r32(FE_REG_TX_CTX_IDX0),
903 fe_reg_r32(FE_REG_RX_CALC_IDX0));
904 netif_wake_queue(dev);
905 }
906
907 static irqreturn_t fe_handle_irq(int irq, void *dev)
908 {
909 struct fe_priv *priv = netdev_priv(dev);
910 u32 status, dly_int;
911
912 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
913
914 if (unlikely(!status))
915 return IRQ_NONE;
916
917 dly_int = (priv->soc->rx_dly_int | priv->soc->tx_dly_int);
918 if (likely(status & dly_int)) {
919 fe_int_disable(dly_int);
920 napi_schedule(&priv->rx_napi);
921 } else {
922 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
923 }
924
925 return IRQ_HANDLED;
926 }
927
928 #ifdef CONFIG_NET_POLL_CONTROLLER
929 static void fe_poll_controller(struct net_device *dev)
930 {
931 struct fe_priv *priv = netdev_priv(dev);
932 u32 dly_int = priv->soc->tx_dly_int | priv->soc->rx_dly_int;
933
934 fe_int_disable(dly_int);
935 fe_handle_irq(dev->irq, dev);
936 fe_int_enable(dly_int);
937 }
938 #endif
939
940 int fe_set_clock_cycle(struct fe_priv *priv)
941 {
942 unsigned long sysclk = priv->sysclk;
943
944 if (!sysclk) {
945 return -EINVAL;
946 }
947
948 sysclk /= FE_US_CYC_CNT_DIVISOR;
949 sysclk <<= FE_US_CYC_CNT_SHIFT;
950
951 fe_w32((fe_r32(FE_FE_GLO_CFG) &
952 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
953 sysclk,
954 FE_FE_GLO_CFG);
955 return 0;
956 }
957
958 void fe_fwd_config(struct fe_priv *priv)
959 {
960 u32 fwd_cfg;
961
962 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
963
964 /* disable jumbo frame */
965 if (priv->flags & FE_FLAG_JUMBO_FRAME)
966 fwd_cfg &= ~FE_GDM1_JMB_EN;
967
968 /* set unicast/multicast/broadcast frame to cpu */
969 fwd_cfg &= ~0xffff;
970
971 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
972 }
973
974 static void fe_rxcsum_config(bool enable)
975 {
976 if (enable)
977 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
978 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
979 FE_GDMA1_FWD_CFG);
980 else
981 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
982 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
983 FE_GDMA1_FWD_CFG);
984 }
985
986 static void fe_txcsum_config(bool enable)
987 {
988 if (enable)
989 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
990 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
991 FE_CDMA_CSG_CFG);
992 else
993 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
994 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
995 FE_CDMA_CSG_CFG);
996 }
997
998 void fe_csum_config(struct fe_priv *priv)
999 {
1000 struct net_device *dev = priv_netdev(priv);
1001
1002 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1003 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1004 }
1005
1006 static int fe_hw_init(struct net_device *dev)
1007 {
1008 struct fe_priv *priv = netdev_priv(dev);
1009 int i, err;
1010
1011 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1012 dev_name(priv->device), dev);
1013 if (err)
1014 return err;
1015
1016 if (priv->soc->set_mac)
1017 priv->soc->set_mac(priv, dev->dev_addr);
1018 else
1019 fe_hw_set_macaddr(priv, dev->dev_addr);
1020
1021 fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
1022
1023 fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
1024
1025 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1026 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1027 for (i = 0; i < 16; i += 2)
1028 fe_w32(((i + 1) << 16) + i,
1029 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1030 (i * 2));
1031
1032 BUG_ON(!priv->soc->fwd_config);
1033 if (priv->soc->fwd_config(priv))
1034 netdev_err(dev, "unable to get clock\n");
1035
1036 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1037 fe_reg_w32(1, FE_REG_FE_RST_GL);
1038 fe_reg_w32(0, FE_REG_FE_RST_GL);
1039 }
1040
1041 return 0;
1042 }
1043
1044 static int fe_open(struct net_device *dev)
1045 {
1046 struct fe_priv *priv = netdev_priv(dev);
1047 unsigned long flags;
1048 u32 val;
1049 int err;
1050
1051 err = fe_init_dma(priv);
1052 if (err)
1053 goto err_out;
1054
1055 spin_lock_irqsave(&priv->page_lock, flags);
1056 napi_enable(&priv->rx_napi);
1057
1058 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1059 val |= priv->soc->pdma_glo_cfg;
1060 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1061
1062 spin_unlock_irqrestore(&priv->page_lock, flags);
1063
1064 if (priv->phy)
1065 priv->phy->start(priv);
1066
1067 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1068 netif_carrier_on(dev);
1069
1070 netif_start_queue(dev);
1071 fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
1072
1073 return 0;
1074
1075 err_out:
1076 fe_free_dma(priv);
1077 return err;
1078 }
1079
1080 static int fe_stop(struct net_device *dev)
1081 {
1082 struct fe_priv *priv = netdev_priv(dev);
1083 unsigned long flags;
1084 int i;
1085
1086 fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
1087
1088 netif_tx_disable(dev);
1089
1090 if (priv->phy)
1091 priv->phy->stop(priv);
1092
1093 spin_lock_irqsave(&priv->page_lock, flags);
1094 napi_disable(&priv->rx_napi);
1095
1096 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1097 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1098 FE_REG_PDMA_GLO_CFG);
1099 spin_unlock_irqrestore(&priv->page_lock, flags);
1100
1101 /* wait dma stop */
1102 for (i = 0; i < 10; i++) {
1103 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1104 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1105 msleep(10);
1106 continue;
1107 }
1108 break;
1109 }
1110
1111 fe_free_dma(priv);
1112
1113 return 0;
1114 }
1115
1116 static int __init fe_init(struct net_device *dev)
1117 {
1118 struct fe_priv *priv = netdev_priv(dev);
1119 struct device_node *port;
1120 int err;
1121
1122 BUG_ON(!priv->soc->reset_fe);
1123 priv->soc->reset_fe();
1124
1125 if (priv->soc->switch_init)
1126 priv->soc->switch_init(priv);
1127
1128 memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
1129 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1130
1131 err = fe_mdio_init(priv);
1132 if (err)
1133 return err;
1134
1135 if (priv->soc->port_init)
1136 for_each_child_of_node(priv->device->of_node, port)
1137 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1138 priv->soc->port_init(priv, port);
1139
1140 if (priv->phy) {
1141 err = priv->phy->connect(priv);
1142 if (err)
1143 goto err_phy_disconnect;
1144 }
1145
1146 err = fe_hw_init(dev);
1147 if (err)
1148 goto err_phy_disconnect;
1149
1150 if (priv->soc->switch_config)
1151 priv->soc->switch_config(priv);
1152
1153 return 0;
1154
1155 err_phy_disconnect:
1156 if (priv->phy)
1157 priv->phy->disconnect(priv);
1158 fe_mdio_cleanup(priv);
1159
1160 return err;
1161 }
1162
1163 static void fe_uninit(struct net_device *dev)
1164 {
1165 struct fe_priv *priv = netdev_priv(dev);
1166
1167 if (priv->phy)
1168 priv->phy->disconnect(priv);
1169 fe_mdio_cleanup(priv);
1170
1171 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1172 free_irq(dev->irq, dev);
1173 }
1174
1175 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1176 {
1177 struct fe_priv *priv = netdev_priv(dev);
1178
1179 if (!priv->phy_dev)
1180 return -ENODEV;
1181
1182 switch (cmd) {
1183 case SIOCETHTOOL:
1184 return phy_ethtool_ioctl(priv->phy_dev,
1185 (void *) ifr->ifr_data);
1186 case SIOCGMIIPHY:
1187 case SIOCGMIIREG:
1188 case SIOCSMIIREG:
1189 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1190 default:
1191 break;
1192 }
1193
1194 return -EOPNOTSUPP;
1195 }
1196
1197 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1198 {
1199 struct fe_priv *priv = netdev_priv(dev);
1200 int frag_size, old_mtu;
1201 u32 fwd_cfg;
1202
1203 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1204 return eth_change_mtu(dev, new_mtu);
1205
1206 frag_size = fe_max_frag_size(new_mtu);
1207 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1208 return -EINVAL;
1209
1210 old_mtu = dev->mtu;
1211 dev->mtu = new_mtu;
1212
1213 /* return early if the buffer sizes will not change */
1214 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1215 return 0;
1216 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1217 return 0;
1218
1219 if (new_mtu <= ETH_DATA_LEN) {
1220 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1221 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1222 } else {
1223 priv->frag_size = PAGE_SIZE;
1224 priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
1225 }
1226
1227 if (!netif_running(dev))
1228 return 0;
1229
1230 fe_stop(dev);
1231 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1232 if (new_mtu <= ETH_DATA_LEN)
1233 fwd_cfg &= ~FE_GDM1_JMB_EN;
1234 else {
1235 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1236 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1237 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1238 }
1239 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1240
1241 return fe_open(dev);
1242 }
1243
1244 static const struct net_device_ops fe_netdev_ops = {
1245 .ndo_init = fe_init,
1246 .ndo_uninit = fe_uninit,
1247 .ndo_open = fe_open,
1248 .ndo_stop = fe_stop,
1249 .ndo_start_xmit = fe_start_xmit,
1250 .ndo_set_mac_address = fe_set_mac_address,
1251 .ndo_validate_addr = eth_validate_addr,
1252 .ndo_do_ioctl = fe_do_ioctl,
1253 .ndo_change_mtu = fe_change_mtu,
1254 .ndo_tx_timeout = fe_tx_timeout,
1255 .ndo_get_stats64 = fe_get_stats64,
1256 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1257 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1258 #ifdef CONFIG_NET_POLL_CONTROLLER
1259 .ndo_poll_controller = fe_poll_controller,
1260 #endif
1261 };
1262
1263 static int fe_probe(struct platform_device *pdev)
1264 {
1265 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1266 const struct of_device_id *match;
1267 struct fe_soc_data *soc;
1268 struct net_device *netdev;
1269 struct fe_priv *priv;
1270 struct clk *sysclk;
1271 int err;
1272
1273 device_reset(&pdev->dev);
1274
1275 match = of_match_device(of_fe_match, &pdev->dev);
1276 soc = (struct fe_soc_data *) match->data;
1277
1278 if (soc->reg_table)
1279 fe_reg_table = soc->reg_table;
1280 else
1281 soc->reg_table = fe_reg_table;
1282
1283 fe_base = devm_request_and_ioremap(&pdev->dev, res);
1284 if (!fe_base) {
1285 err = -EADDRNOTAVAIL;
1286 goto err_out;
1287 }
1288
1289 netdev = alloc_etherdev(sizeof(*priv));
1290 if (!netdev) {
1291 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1292 err = -ENOMEM;
1293 goto err_iounmap;
1294 }
1295
1296 SET_NETDEV_DEV(netdev, &pdev->dev);
1297 netdev->netdev_ops = &fe_netdev_ops;
1298 netdev->base_addr = (unsigned long) fe_base;
1299 netdev->watchdog_timeo = TX_TIMEOUT;
1300
1301 netdev->irq = platform_get_irq(pdev, 0);
1302 if (netdev->irq < 0) {
1303 dev_err(&pdev->dev, "no IRQ resource found\n");
1304 err = -ENXIO;
1305 goto err_free_dev;
1306 }
1307
1308 if (soc->init_data)
1309 soc->init_data(soc, netdev);
1310 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1311 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1312 netdev->vlan_features = netdev->hw_features &
1313 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1314 netdev->features |= netdev->hw_features;
1315
1316 /* fake rx vlan filter func. to support tx vlan offload func */
1317 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1318 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1319
1320 priv = netdev_priv(netdev);
1321 spin_lock_init(&priv->page_lock);
1322 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1323 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1324 if (!priv->hw_stats) {
1325 err = -ENOMEM;
1326 goto err_free_dev;
1327 }
1328 spin_lock_init(&priv->hw_stats->stats_lock);
1329 }
1330
1331 sysclk = devm_clk_get(&pdev->dev, NULL);
1332 if (!IS_ERR(sysclk))
1333 priv->sysclk = clk_get_rate(sysclk);
1334
1335 priv->netdev = netdev;
1336 priv->device = &pdev->dev;
1337 priv->soc = soc;
1338 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1339 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1340 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1341 if (priv->frag_size > PAGE_SIZE) {
1342 dev_err(&pdev->dev, "error frag size.\n");
1343 err = -EINVAL;
1344 goto err_free_dev;
1345 }
1346
1347 netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
1348 fe_set_ethtool_ops(netdev);
1349
1350 err = register_netdev(netdev);
1351 if (err) {
1352 dev_err(&pdev->dev, "error bringing up device\n");
1353 goto err_free_dev;
1354 }
1355
1356 platform_set_drvdata(pdev, netdev);
1357
1358 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1359 netdev->base_addr, netdev->irq);
1360
1361 return 0;
1362
1363 err_free_dev:
1364 free_netdev(netdev);
1365 err_iounmap:
1366 devm_iounmap(&pdev->dev, fe_base);
1367 err_out:
1368 return err;
1369 }
1370
1371 static int fe_remove(struct platform_device *pdev)
1372 {
1373 struct net_device *dev = platform_get_drvdata(pdev);
1374 struct fe_priv *priv = netdev_priv(dev);
1375
1376 netif_napi_del(&priv->rx_napi);
1377 if (priv->hw_stats)
1378 kfree(priv->hw_stats);
1379
1380 unregister_netdev(dev);
1381 free_netdev(dev);
1382 platform_set_drvdata(pdev, NULL);
1383
1384 return 0;
1385 }
1386
1387 static struct platform_driver fe_driver = {
1388 .probe = fe_probe,
1389 .remove = fe_remove,
1390 .driver = {
1391 .name = "ralink_soc_eth",
1392 .owner = THIS_MODULE,
1393 .of_match_table = of_fe_match,
1394 },
1395 };
1396
1397 static int __init init_rtfe(void)
1398 {
1399 int ret;
1400
1401 ret = rtesw_init();
1402 if (ret)
1403 return ret;
1404
1405 ret = platform_driver_register(&fe_driver);
1406 if (ret)
1407 rtesw_exit();
1408
1409 return ret;
1410 }
1411
1412 static void __exit exit_rtfe(void)
1413 {
1414 platform_driver_unregister(&fe_driver);
1415 rtesw_exit();
1416 }
1417
1418 module_init(init_rtfe);
1419 module_exit(exit_rtfe);
1420
1421 MODULE_LICENSE("GPL");
1422 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1423 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1424 MODULE_VERSION(FE_DRV_VERSION);