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ramips: fix ethernet vlan tx offload support check when delete
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define MAX_RX_LENGTH 1536
44 #define FE_RX_HLEN (NET_SKB_PAD + VLAN_ETH_HLEN + VLAN_HLEN + \
45 + NET_IP_ALIGN + ETH_FCS_LEN)
46 #define DMA_DUMMY_DESC 0xffffffff
47 #define FE_DEFAULT_MSG_ENABLE \
48 (NETIF_MSG_DRV | \
49 NETIF_MSG_PROBE | \
50 NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_IFDOWN | \
53 NETIF_MSG_IFUP | \
54 NETIF_MSG_RX_ERR | \
55 NETIF_MSG_TX_ERR)
56
57 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
58 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
59 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (priv->tx_ring_size - 1))
60 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (priv->rx_ring_size - 1))
61
62 #define SYSC_REG_RSTCTRL 0x34
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
76 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
77 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
78 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
79 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
80 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
81 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
82 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
83 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
84 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
85 };
86
87 static const u16 *fe_reg_table = fe_reg_table_default;
88
89 struct fe_work_t {
90 int bitnr;
91 void (*action)(struct fe_priv *);
92 };
93
94 static void __iomem *fe_base = 0;
95
96 void fe_w32(u32 val, unsigned reg)
97 {
98 __raw_writel(val, fe_base + reg);
99 }
100
101 u32 fe_r32(unsigned reg)
102 {
103 return __raw_readl(fe_base + reg);
104 }
105
106 void fe_reg_w32(u32 val, enum fe_reg reg)
107 {
108 fe_w32(val, fe_reg_table[reg]);
109 }
110
111 u32 fe_reg_r32(enum fe_reg reg)
112 {
113 return fe_r32(fe_reg_table[reg]);
114 }
115
116 void fe_reset(u32 reset_bits)
117 {
118 u32 t;
119
120 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
121 t |= reset_bits;
122 rt_sysc_w32(t , SYSC_REG_RSTCTRL);
123 udelay(10);
124
125 t &= ~reset_bits;
126 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
127 udelay(10);
128 }
129
130 static inline void fe_int_disable(u32 mask)
131 {
132 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
133 FE_REG_FE_INT_ENABLE);
134 /* flush write */
135 fe_reg_r32(FE_REG_FE_INT_ENABLE);
136 }
137
138 static inline void fe_int_enable(u32 mask)
139 {
140 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
141 FE_REG_FE_INT_ENABLE);
142 /* flush write */
143 fe_reg_r32(FE_REG_FE_INT_ENABLE);
144 }
145
146 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
147 {
148 unsigned long flags;
149
150 spin_lock_irqsave(&priv->page_lock, flags);
151 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
152 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
153 FE_GDMA1_MAC_ADRL);
154 spin_unlock_irqrestore(&priv->page_lock, flags);
155 }
156
157 static int fe_set_mac_address(struct net_device *dev, void *p)
158 {
159 int ret = eth_mac_addr(dev, p);
160
161 if (!ret) {
162 struct fe_priv *priv = netdev_priv(dev);
163
164 if (priv->soc->set_mac)
165 priv->soc->set_mac(priv, dev->dev_addr);
166 else
167 fe_hw_set_macaddr(priv, p);
168 }
169
170 return ret;
171 }
172
173 static inline int fe_max_frag_size(int mtu)
174 {
175 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
176 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
177 }
178
179 static inline int fe_max_buf_size(int frag_size)
180 {
181 return frag_size - NET_SKB_PAD - NET_IP_ALIGN -
182 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
183 }
184
185 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
186 {
187 rxd->rxd1 = dma_rxd->rxd1;
188 rxd->rxd2 = dma_rxd->rxd2;
189 rxd->rxd3 = dma_rxd->rxd3;
190 rxd->rxd4 = dma_rxd->rxd4;
191 }
192
193 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
194 {
195 dma_txd->txd1 = txd->txd1;
196 dma_txd->txd3 = txd->txd3;
197 dma_txd->txd4 = txd->txd4;
198 /* clean dma done flag last */
199 dma_txd->txd2 = txd->txd2;
200 }
201
202 static void fe_clean_rx(struct fe_priv *priv)
203 {
204 int i;
205
206 if (priv->rx_data) {
207 for (i = 0; i < priv->rx_ring_size; i++)
208 if (priv->rx_data[i]) {
209 if (priv->rx_dma && priv->rx_dma[i].rxd1)
210 dma_unmap_single(&priv->netdev->dev,
211 priv->rx_dma[i].rxd1,
212 priv->rx_buf_size,
213 DMA_FROM_DEVICE);
214 put_page(virt_to_head_page(priv->rx_data[i]));
215 }
216
217 kfree(priv->rx_data);
218 priv->rx_data = NULL;
219 }
220
221 if (priv->rx_dma) {
222 dma_free_coherent(&priv->netdev->dev,
223 priv->rx_ring_size * sizeof(*priv->rx_dma),
224 priv->rx_dma,
225 priv->rx_phys);
226 priv->rx_dma = NULL;
227 }
228 }
229
230 static int fe_alloc_rx(struct fe_priv *priv)
231 {
232 struct net_device *netdev = priv->netdev;
233 int i, pad;
234
235 priv->rx_data = kcalloc(priv->rx_ring_size, sizeof(*priv->rx_data),
236 GFP_KERNEL);
237 if (!priv->rx_data)
238 goto no_rx_mem;
239
240 for (i = 0; i < priv->rx_ring_size; i++) {
241 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
242 if (!priv->rx_data[i])
243 goto no_rx_mem;
244 }
245
246 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
247 priv->rx_ring_size * sizeof(*priv->rx_dma),
248 &priv->rx_phys,
249 GFP_ATOMIC | __GFP_ZERO);
250 if (!priv->rx_dma)
251 goto no_rx_mem;
252
253 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
254 pad = 0;
255 else
256 pad = NET_IP_ALIGN;
257 for (i = 0; i < priv->rx_ring_size; i++) {
258 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
259 priv->rx_data[i] + NET_SKB_PAD + pad,
260 priv->rx_buf_size,
261 DMA_FROM_DEVICE);
262 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
263 goto no_rx_mem;
264 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
265
266 if (priv->flags & FE_FLAG_RX_SG_DMA)
267 priv->rx_dma[i].rxd2 = RX_DMA_PLEN0(priv->rx_buf_size);
268 else
269 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
270 }
271 wmb();
272
273 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
274 fe_reg_w32(priv->rx_ring_size, FE_REG_RX_MAX_CNT0);
275 fe_reg_w32((priv->rx_ring_size - 1), FE_REG_RX_CALC_IDX0);
276 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
277
278 return 0;
279
280 no_rx_mem:
281 return -ENOMEM;
282 }
283
284 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
285 {
286 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
287 dma_unmap_single(dev,
288 dma_unmap_addr(tx_buf, dma_addr0),
289 dma_unmap_len(tx_buf, dma_len0),
290 DMA_TO_DEVICE);
291 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
292 dma_unmap_page(dev,
293 dma_unmap_addr(tx_buf, dma_addr0),
294 dma_unmap_len(tx_buf, dma_len0),
295 DMA_TO_DEVICE);
296 }
297 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
298 dma_unmap_page(dev,
299 dma_unmap_addr(tx_buf, dma_addr1),
300 dma_unmap_len(tx_buf, dma_len1),
301 DMA_TO_DEVICE);
302
303 tx_buf->flags = 0;
304 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *) DMA_DUMMY_DESC)) {
305 dev_kfree_skb_any(tx_buf->skb);
306 }
307 tx_buf->skb = NULL;
308 }
309
310 static void fe_clean_tx(struct fe_priv *priv)
311 {
312 int i;
313
314 if (priv->tx_buf) {
315 for (i = 0; i < priv->tx_ring_size; i++)
316 fe_txd_unmap(&priv->netdev->dev, &priv->tx_buf[i]);
317 kfree(priv->tx_buf);
318 priv->tx_buf = NULL;
319 }
320
321 if (priv->tx_dma) {
322 dma_free_coherent(&priv->netdev->dev,
323 priv->tx_ring_size * sizeof(*priv->tx_dma),
324 priv->tx_dma,
325 priv->tx_phys);
326 priv->tx_dma = NULL;
327 }
328 }
329
330 static int fe_alloc_tx(struct fe_priv *priv)
331 {
332 int i;
333
334 priv->tx_free_idx = 0;
335
336 priv->tx_buf = kcalloc(priv->tx_ring_size, sizeof(*priv->tx_buf),
337 GFP_KERNEL);
338 if (!priv->tx_buf)
339 goto no_tx_mem;
340
341 priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
342 priv->tx_ring_size * sizeof(*priv->tx_dma),
343 &priv->tx_phys,
344 GFP_ATOMIC | __GFP_ZERO);
345 if (!priv->tx_dma)
346 goto no_tx_mem;
347
348 for (i = 0; i < priv->tx_ring_size; i++) {
349 if (priv->soc->tx_dma) {
350 priv->soc->tx_dma(&priv->tx_dma[i]);
351 }
352 priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
353 }
354 wmb();
355
356 fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
357 fe_reg_w32(priv->tx_ring_size, FE_REG_TX_MAX_CNT0);
358 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
359 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
360
361 return 0;
362
363 no_tx_mem:
364 return -ENOMEM;
365 }
366
367 static int fe_init_dma(struct fe_priv *priv)
368 {
369 int err;
370
371 err = fe_alloc_tx(priv);
372 if (err)
373 return err;
374
375 err = fe_alloc_rx(priv);
376 if (err)
377 return err;
378
379 return 0;
380 }
381
382 static void fe_free_dma(struct fe_priv *priv)
383 {
384 fe_clean_tx(priv);
385 fe_clean_rx(priv);
386
387 netdev_reset_queue(priv->netdev);
388 }
389
390 void fe_stats_update(struct fe_priv *priv)
391 {
392 struct fe_hw_stats *hwstats = priv->hw_stats;
393 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
394 u64 stats;
395
396 u64_stats_update_begin(&hwstats->syncp);
397
398 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
399 hwstats->rx_bytes += fe_r32(base);
400 stats = fe_r32(base + 0x04);
401 if (stats)
402 hwstats->rx_bytes += (stats << 32);
403 hwstats->rx_packets += fe_r32(base + 0x08);
404 hwstats->rx_overflow += fe_r32(base + 0x10);
405 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
406 hwstats->rx_short_errors += fe_r32(base + 0x18);
407 hwstats->rx_long_errors += fe_r32(base + 0x1c);
408 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
409 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
410 hwstats->tx_skip += fe_r32(base + 0x28);
411 hwstats->tx_collisions += fe_r32(base + 0x2c);
412 hwstats->tx_bytes += fe_r32(base + 0x30);
413 stats = fe_r32(base + 0x34);
414 if (stats)
415 hwstats->tx_bytes += (stats << 32);
416 hwstats->tx_packets += fe_r32(base + 0x38);
417 } else {
418 hwstats->tx_bytes += fe_r32(base);
419 hwstats->tx_packets += fe_r32(base + 0x04);
420 hwstats->tx_skip += fe_r32(base + 0x08);
421 hwstats->tx_collisions += fe_r32(base + 0x0c);
422 hwstats->rx_bytes += fe_r32(base + 0x20);
423 hwstats->rx_packets += fe_r32(base + 0x24);
424 hwstats->rx_overflow += fe_r32(base + 0x28);
425 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
426 hwstats->rx_short_errors += fe_r32(base + 0x30);
427 hwstats->rx_long_errors += fe_r32(base + 0x34);
428 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
429 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
430 }
431
432 u64_stats_update_end(&hwstats->syncp);
433 }
434
435 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
436 struct rtnl_link_stats64 *storage)
437 {
438 struct fe_priv *priv = netdev_priv(dev);
439 struct fe_hw_stats *hwstats = priv->hw_stats;
440 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
441 unsigned int start;
442
443 if (!base) {
444 netdev_stats_to_stats64(storage, &dev->stats);
445 return storage;
446 }
447
448 if (netif_running(dev) && netif_device_present(dev)) {
449 if (spin_trylock(&hwstats->stats_lock)) {
450 fe_stats_update(priv);
451 spin_unlock(&hwstats->stats_lock);
452 }
453 }
454
455 do {
456 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
457 storage->rx_packets = hwstats->rx_packets;
458 storage->tx_packets = hwstats->tx_packets;
459 storage->rx_bytes = hwstats->rx_bytes;
460 storage->tx_bytes = hwstats->tx_bytes;
461 storage->collisions = hwstats->tx_collisions;
462 storage->rx_length_errors = hwstats->rx_short_errors +
463 hwstats->rx_long_errors;
464 storage->rx_over_errors = hwstats->rx_overflow;
465 storage->rx_crc_errors = hwstats->rx_fcs_errors;
466 storage->rx_errors = hwstats->rx_checksum_errors;
467 storage->tx_aborted_errors = hwstats->tx_skip;
468 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
469
470 storage->tx_errors = priv->netdev->stats.tx_errors;
471 storage->rx_dropped = priv->netdev->stats.rx_dropped;
472 storage->tx_dropped = priv->netdev->stats.tx_dropped;
473
474 return storage;
475 }
476
477 static int fe_vlan_rx_add_vid(struct net_device *dev,
478 __be16 proto, u16 vid)
479 {
480 struct fe_priv *priv = netdev_priv(dev);
481 u32 idx = (vid & 0xf);
482 u32 vlan_cfg;
483
484 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
485 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
486 return 0;
487
488 if (test_bit(idx, &priv->vlan_map)) {
489 netdev_warn(dev, "disable tx vlan offload\n");
490 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
491 netdev_update_features(dev);
492 } else {
493 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
494 ((idx >> 1) << 2));
495 if (idx & 0x1) {
496 vlan_cfg &= 0xffff;
497 vlan_cfg |= (vid << 16);
498 } else {
499 vlan_cfg &= 0xffff0000;
500 vlan_cfg |= vid;
501 }
502 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
503 ((idx >> 1) << 2));
504 set_bit(idx, &priv->vlan_map);
505 }
506
507 return 0;
508 }
509
510 static int fe_vlan_rx_kill_vid(struct net_device *dev,
511 __be16 proto, u16 vid)
512 {
513 struct fe_priv *priv = netdev_priv(dev);
514 u32 idx = (vid & 0xf);
515
516 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
517 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
518 return 0;
519
520 clear_bit(idx, &priv->vlan_map);
521
522 return 0;
523 }
524
525 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
526 int idx, int tx_num)
527 {
528 struct fe_priv *priv = netdev_priv(dev);
529 struct skb_frag_struct *frag;
530 struct fe_tx_dma txd, *ptxd;
531 struct fe_tx_buf *tx_buf;
532 dma_addr_t mapped_addr;
533 unsigned int nr_frags;
534 u32 def_txd4;
535 int i, j, k, frag_size, frag_map_size, offset;
536
537 tx_buf = &priv->tx_buf[idx];
538 memset(tx_buf, 0, sizeof(*tx_buf));
539 memset(&txd, 0, sizeof(txd));
540 nr_frags = skb_shinfo(skb)->nr_frags;
541
542 /* init tx descriptor */
543 if (priv->soc->tx_dma)
544 priv->soc->tx_dma(&txd);
545 else
546 txd.txd4 = TX_DMA_DESP4_DEF;
547 def_txd4 = txd.txd4;
548
549 /* TX Checksum offload */
550 if (skb->ip_summed == CHECKSUM_PARTIAL)
551 txd.txd4 |= TX_DMA_CHKSUM;
552
553 /* VLAN header offload */
554 if (vlan_tx_tag_present(skb)) {
555 if (IS_ENABLED(CONFIG_SOC_MT7621))
556 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
557 else
558 txd.txd4 |= TX_DMA_INS_VLAN |
559 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
560 (vlan_tx_tag_get(skb) & 0xF);
561 }
562
563 /* TSO: fill MSS info in tcp checksum field */
564 if (skb_is_gso(skb)) {
565 if (skb_cow_head(skb, 0)) {
566 netif_warn(priv, tx_err, dev,
567 "GSO expand head fail.\n");
568 goto err_out;
569 }
570 if (skb_shinfo(skb)->gso_type &
571 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
572 txd.txd4 |= TX_DMA_TSO;
573 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
574 }
575 }
576
577 mapped_addr = dma_map_single(&dev->dev, skb->data,
578 skb_headlen(skb), DMA_TO_DEVICE);
579 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
580 goto err_out;
581 txd.txd1 = mapped_addr;
582 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
583
584 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
585 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
586 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
587
588 /* TX SG offload */
589 j = idx;
590 k = 0;
591 for (i = 0; i < nr_frags; i++) {
592 offset = 0;
593 frag = &skb_shinfo(skb)->frags[i];
594 frag_size = skb_frag_size(frag);
595
596 while (frag_size > 0) {
597 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
598 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
599 frag_map_size, DMA_TO_DEVICE);
600 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
601 goto err_dma;
602
603 if (k & 0x1) {
604 j = NEXT_TX_DESP_IDX(j);
605 txd.txd1 = mapped_addr;
606 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
607 txd.txd4 = def_txd4;
608
609 tx_buf = &priv->tx_buf[j];
610 memset(tx_buf, 0, sizeof(*tx_buf));
611
612 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
613 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
614 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
615 } else {
616 txd.txd3 = mapped_addr;
617 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
618
619 tx_buf->skb = (struct sk_buff *) DMA_DUMMY_DESC;
620 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
621 dma_unmap_addr_set(tx_buf, dma_addr1, mapped_addr);
622 dma_unmap_len_set(tx_buf, dma_len1, frag_map_size);
623
624 if (!((i == (nr_frags -1)) &&
625 (frag_map_size == frag_size))) {
626 fe_set_txd(&txd, &priv->tx_dma[j]);
627 memset(&txd, 0, sizeof(txd));
628 }
629 }
630 frag_size -= frag_map_size;
631 offset += frag_map_size;
632 k++;
633 }
634 }
635
636 /* set last segment */
637 if (k & 0x1)
638 txd.txd2 |= TX_DMA_LS1;
639 else
640 txd.txd2 |= TX_DMA_LS0;
641 fe_set_txd(&txd, &priv->tx_dma[j]);
642
643 /* store skb to cleanup */
644 tx_buf->skb = skb;
645
646 netdev_sent_queue(dev, skb->len);
647 skb_tx_timestamp(skb);
648
649 j = NEXT_TX_DESP_IDX(j);
650 wmb();
651 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
652
653 return 0;
654
655 err_dma:
656 j = idx;
657 for (i = 0; i < tx_num; i++) {
658 ptxd = &priv->tx_dma[j];
659 tx_buf = &priv->tx_buf[j];
660
661 /* unmap dma */
662 fe_txd_unmap(&dev->dev, tx_buf);
663
664 ptxd->txd2 = TX_DMA_DESP2_DEF;
665 j = NEXT_TX_DESP_IDX(j);
666 }
667 wmb();
668
669 err_out:
670 return -1;
671 }
672
673 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
674 unsigned int len;
675 int ret;
676
677 ret = 0;
678 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
679 if ((priv->flags & FE_FLAG_PADDING_64B) &&
680 !(priv->flags & FE_FLAG_PADDING_BUG))
681 return ret;
682
683 if (vlan_tx_tag_present(skb))
684 len = ETH_ZLEN;
685 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
686 len = VLAN_ETH_ZLEN;
687 else if(!(priv->flags & FE_FLAG_PADDING_64B))
688 len = ETH_ZLEN;
689 else
690 return ret;
691
692 if (skb->len < len) {
693 if ((ret = skb_pad(skb, len - skb->len)) < 0)
694 return ret;
695 skb->len = len;
696 skb_set_tail_pointer(skb, len);
697 }
698 }
699
700 return ret;
701 }
702
703 static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
704 {
705 return (u32)(priv->tx_ring_size - ((tx_fill_idx - priv->tx_free_idx) &
706 (priv->tx_ring_size - 1)));
707 }
708
709 static inline int fe_cal_txd_req(struct sk_buff *skb)
710 {
711 int i, nfrags;
712 struct skb_frag_struct *frag;
713
714 nfrags = 1;
715 if (skb_is_gso(skb)) {
716 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
717 frag = &skb_shinfo(skb)->frags[i];
718 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
719 }
720 } else {
721 nfrags += skb_shinfo(skb)->nr_frags;
722 }
723
724 return DIV_ROUND_UP(nfrags, 2);
725 }
726
727 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
728 {
729 struct fe_priv *priv = netdev_priv(dev);
730 struct net_device_stats *stats = &dev->stats;
731 u32 tx;
732 int tx_num;
733 int len = skb->len;
734
735 if (fe_skb_padto(skb, priv)) {
736 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
737 return NETDEV_TX_OK;
738 }
739
740 tx_num = fe_cal_txd_req(skb);
741 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
742 if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
743 {
744 netif_stop_queue(dev);
745 netif_err(priv, tx_queued,dev,
746 "Tx Ring full when queue awake!\n");
747 return NETDEV_TX_BUSY;
748 }
749
750 if (fe_tx_map_dma(skb, dev, tx, tx_num) < 0) {
751 stats->tx_dropped++;
752 } else {
753 stats->tx_packets++;
754 stats->tx_bytes += len;
755 }
756
757 return NETDEV_TX_OK;
758 }
759
760 static inline void fe_rx_vlan(struct sk_buff *skb)
761 {
762 struct ethhdr *ehdr;
763 u16 vlanid;
764
765 if (!__vlan_get_tag(skb, &vlanid)) {
766 /* pop the vlan tag */
767 ehdr = (struct ethhdr *)skb->data;
768 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
769 skb_pull(skb, VLAN_HLEN);
770 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
771 }
772 }
773
774 static int fe_poll_rx(struct napi_struct *napi, int budget,
775 struct fe_priv *priv, u32 rx_intr)
776 {
777 struct net_device *netdev = priv->netdev;
778 struct net_device_stats *stats = &netdev->stats;
779 struct fe_soc_data *soc = priv->soc;
780 u32 checksum_bit;
781 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
782 struct sk_buff *skb;
783 u8 *data, *new_data;
784 struct fe_rx_dma *rxd, trxd;
785 int done = 0, pad;
786 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
787
788 if (netdev->features & NETIF_F_RXCSUM)
789 checksum_bit = soc->checksum_bit;
790 else
791 checksum_bit = 0;
792
793 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
794 pad = 0;
795 else
796 pad = NET_IP_ALIGN;
797
798 while (done < budget) {
799 unsigned int pktlen;
800 dma_addr_t dma_addr;
801 idx = NEXT_RX_DESP_IDX(idx);
802 rxd = &priv->rx_dma[idx];
803 data = priv->rx_data[idx];
804
805 fe_get_rxd(&trxd, rxd);
806 if (!(trxd.rxd2 & RX_DMA_DONE))
807 break;
808
809 /* alloc new buffer */
810 new_data = netdev_alloc_frag(priv->frag_size);
811 if (unlikely(!new_data)) {
812 stats->rx_dropped++;
813 goto release_desc;
814 }
815 dma_addr = dma_map_single(&netdev->dev,
816 new_data + NET_SKB_PAD + pad,
817 priv->rx_buf_size,
818 DMA_FROM_DEVICE);
819 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
820 put_page(virt_to_head_page(new_data));
821 goto release_desc;
822 }
823
824 /* receive data */
825 skb = build_skb(data, priv->frag_size);
826 if (unlikely(!skb)) {
827 put_page(virt_to_head_page(new_data));
828 goto release_desc;
829 }
830 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
831
832 dma_unmap_single(&netdev->dev, trxd.rxd1,
833 priv->rx_buf_size, DMA_FROM_DEVICE);
834 pktlen = RX_DMA_PLEN0(trxd.rxd2);
835 skb->dev = netdev;
836 skb_put(skb, pktlen);
837 if (trxd.rxd4 & checksum_bit) {
838 skb->ip_summed = CHECKSUM_UNNECESSARY;
839 } else {
840 skb_checksum_none_assert(skb);
841 }
842 if (rx_vlan)
843 fe_rx_vlan(skb);
844 skb->protocol = eth_type_trans(skb, netdev);
845
846 stats->rx_packets++;
847 stats->rx_bytes += pktlen;
848
849 napi_gro_receive(napi, skb);
850
851 priv->rx_data[idx] = new_data;
852 rxd->rxd1 = (unsigned int) dma_addr;
853
854 release_desc:
855 if (priv->flags & FE_FLAG_RX_SG_DMA)
856 rxd->rxd2 = RX_DMA_PLEN0(priv->rx_buf_size);
857 else
858 rxd->rxd2 = RX_DMA_LSO;
859
860 wmb();
861 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
862 done++;
863 }
864
865 if (done < budget)
866 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
867
868 return done;
869 }
870
871 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr)
872 {
873 struct net_device *netdev = priv->netdev;
874 struct device *dev = &netdev->dev;
875 unsigned int bytes_compl = 0;
876 struct sk_buff *skb;
877 struct fe_tx_buf *tx_buf;
878 int done = 0;
879 u32 idx, hwidx;
880
881 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
882 idx = priv->tx_free_idx;
883
884 txpoll_again:
885 while ((idx != hwidx) && budget) {
886 tx_buf = &priv->tx_buf[idx];
887 skb = tx_buf->skb;
888
889 if (!skb)
890 break;
891
892 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
893 bytes_compl += skb->len;
894 done++;
895 budget--;
896 }
897 fe_txd_unmap(dev, tx_buf);
898 idx = NEXT_TX_DESP_IDX(idx);
899 }
900 priv->tx_free_idx = idx;
901
902 if (budget) {
903 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
904 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
905 if (idx != hwidx)
906 goto txpoll_again;
907 }
908
909 if (!done)
910 return 0;
911
912 netdev_completed_queue(netdev, done, bytes_compl);
913 if (unlikely(netif_queue_stopped(netdev) &&
914 netif_carrier_ok(netdev))) {
915 netif_wake_queue(netdev);
916 }
917
918 return done;
919 }
920
921 static int fe_poll(struct napi_struct *napi, int budget)
922 {
923 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
924 struct fe_hw_stats *hwstat = priv->hw_stats;
925 int tx_done, rx_done;
926 u32 status, fe_status, status_reg, mask;
927 u32 tx_intr, rx_intr, status_intr;
928
929 fe_status = status = fe_reg_r32(FE_REG_FE_INT_STATUS);
930 tx_intr = priv->soc->tx_int;
931 rx_intr = priv->soc->rx_int;
932 status_intr = priv->soc->status_int;
933 tx_done = rx_done = 0;
934
935 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
936 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
937 status_reg = FE_REG_FE_INT_STATUS2;
938 } else
939 status_reg = FE_REG_FE_INT_STATUS;
940
941 if (status & tx_intr)
942 tx_done = fe_poll_tx(priv, budget, tx_intr);
943
944 if (status & rx_intr)
945 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
946
947 if (unlikely(fe_status & status_intr)) {
948 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
949 fe_stats_update(priv);
950 spin_unlock(&hwstat->stats_lock);
951 }
952 fe_reg_w32(status_intr, status_reg);
953 }
954
955 if (unlikely(netif_msg_intr(priv))) {
956 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
957 netdev_info(priv->netdev,
958 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
959 tx_done, rx_done, status, mask);
960 }
961
962 if ((tx_done < budget) && (rx_done < budget)) {
963 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
964 if (status & (tx_intr | rx_intr ))
965 goto poll_again;
966
967 napi_complete(napi);
968 fe_int_enable(tx_intr | rx_intr);
969 }
970
971 poll_again:
972 return rx_done;
973 }
974
975 static void fe_tx_timeout(struct net_device *dev)
976 {
977 struct fe_priv *priv = netdev_priv(dev);
978
979 priv->netdev->stats.tx_errors++;
980 netif_err(priv, tx_err, dev,
981 "transmit timed out\n");
982 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
983 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
984 netif_info(priv, drv, dev, "tx_ring=%d, " \
985 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%d\n", 0,
986 fe_reg_r32(FE_REG_TX_BASE_PTR0),
987 fe_reg_r32(FE_REG_TX_MAX_CNT0),
988 fe_reg_r32(FE_REG_TX_CTX_IDX0),
989 fe_reg_r32(FE_REG_TX_DTX_IDX0),
990 priv->tx_free_idx
991 );
992 netif_info(priv, drv, dev, "rx_ring=%d, " \
993 "base=%08x, max=%u, calc=%u, drx=%u\n", 0,
994 fe_reg_r32(FE_REG_RX_BASE_PTR0),
995 fe_reg_r32(FE_REG_RX_MAX_CNT0),
996 fe_reg_r32(FE_REG_RX_CALC_IDX0),
997 fe_reg_r32(FE_REG_RX_DRX_IDX0)
998 );
999
1000 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1001 schedule_work(&priv->pending_work);
1002 }
1003
1004 static irqreturn_t fe_handle_irq(int irq, void *dev)
1005 {
1006 struct fe_priv *priv = netdev_priv(dev);
1007 u32 status, int_mask;
1008
1009 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1010
1011 if (unlikely(!status))
1012 return IRQ_NONE;
1013
1014 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1015 if (likely(status & int_mask)) {
1016 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1017 fe_int_disable(int_mask);
1018 __napi_schedule(&priv->rx_napi);
1019 }
1020 } else {
1021 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1022 }
1023
1024 return IRQ_HANDLED;
1025 }
1026
1027 #ifdef CONFIG_NET_POLL_CONTROLLER
1028 static void fe_poll_controller(struct net_device *dev)
1029 {
1030 struct fe_priv *priv = netdev_priv(dev);
1031 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1032
1033 fe_int_disable(int_mask);
1034 fe_handle_irq(dev->irq, dev);
1035 fe_int_enable(int_mask);
1036 }
1037 #endif
1038
1039 int fe_set_clock_cycle(struct fe_priv *priv)
1040 {
1041 unsigned long sysclk = priv->sysclk;
1042
1043 if (!sysclk) {
1044 return -EINVAL;
1045 }
1046
1047 sysclk /= FE_US_CYC_CNT_DIVISOR;
1048 sysclk <<= FE_US_CYC_CNT_SHIFT;
1049
1050 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1051 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1052 sysclk,
1053 FE_FE_GLO_CFG);
1054 return 0;
1055 }
1056
1057 void fe_fwd_config(struct fe_priv *priv)
1058 {
1059 u32 fwd_cfg;
1060
1061 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1062
1063 /* disable jumbo frame */
1064 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1065 fwd_cfg &= ~FE_GDM1_JMB_EN;
1066
1067 /* set unicast/multicast/broadcast frame to cpu */
1068 fwd_cfg &= ~0xffff;
1069
1070 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1071 }
1072
1073 static void fe_rxcsum_config(bool enable)
1074 {
1075 if (enable)
1076 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1077 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1078 FE_GDMA1_FWD_CFG);
1079 else
1080 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1081 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1082 FE_GDMA1_FWD_CFG);
1083 }
1084
1085 static void fe_txcsum_config(bool enable)
1086 {
1087 if (enable)
1088 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1089 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1090 FE_CDMA_CSG_CFG);
1091 else
1092 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1093 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1094 FE_CDMA_CSG_CFG);
1095 }
1096
1097 void fe_csum_config(struct fe_priv *priv)
1098 {
1099 struct net_device *dev = priv_netdev(priv);
1100
1101 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1102 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1103 }
1104
1105 static int fe_hw_init(struct net_device *dev)
1106 {
1107 struct fe_priv *priv = netdev_priv(dev);
1108 int i, err;
1109
1110 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1111 dev_name(priv->device), dev);
1112 if (err)
1113 return err;
1114
1115 if (priv->soc->set_mac)
1116 priv->soc->set_mac(priv, dev->dev_addr);
1117 else
1118 fe_hw_set_macaddr(priv, dev->dev_addr);
1119
1120 /* disable delay interrupt */
1121 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1122
1123 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1124
1125 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1126 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1127 for (i = 0; i < 16; i += 2)
1128 fe_w32(((i + 1) << 16) + i,
1129 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1130 (i * 2));
1131
1132 BUG_ON(!priv->soc->fwd_config);
1133 if (priv->soc->fwd_config(priv))
1134 netdev_err(dev, "unable to get clock\n");
1135
1136 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1137 fe_reg_w32(1, FE_REG_FE_RST_GL);
1138 fe_reg_w32(0, FE_REG_FE_RST_GL);
1139 }
1140
1141 return 0;
1142 }
1143
1144 static int fe_open(struct net_device *dev)
1145 {
1146 struct fe_priv *priv = netdev_priv(dev);
1147 unsigned long flags;
1148 u32 val;
1149 int err;
1150
1151 err = fe_init_dma(priv);
1152 if (err)
1153 goto err_out;
1154
1155 spin_lock_irqsave(&priv->page_lock, flags);
1156 napi_enable(&priv->rx_napi);
1157
1158 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1159 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1160 val |= FE_RX_2B_OFFSET;
1161 val |= priv->soc->pdma_glo_cfg;
1162 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1163
1164 spin_unlock_irqrestore(&priv->page_lock, flags);
1165
1166 if (priv->phy)
1167 priv->phy->start(priv);
1168
1169 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1170 netif_carrier_on(dev);
1171
1172 netif_start_queue(dev);
1173 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1174
1175 return 0;
1176
1177 err_out:
1178 fe_free_dma(priv);
1179 return err;
1180 }
1181
1182 static int fe_stop(struct net_device *dev)
1183 {
1184 struct fe_priv *priv = netdev_priv(dev);
1185 unsigned long flags;
1186 int i;
1187
1188 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1189
1190 netif_tx_disable(dev);
1191
1192 if (priv->phy)
1193 priv->phy->stop(priv);
1194
1195 spin_lock_irqsave(&priv->page_lock, flags);
1196 napi_disable(&priv->rx_napi);
1197
1198 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1199 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1200 FE_REG_PDMA_GLO_CFG);
1201 spin_unlock_irqrestore(&priv->page_lock, flags);
1202
1203 /* wait dma stop */
1204 for (i = 0; i < 10; i++) {
1205 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1206 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1207 msleep(10);
1208 continue;
1209 }
1210 break;
1211 }
1212
1213 fe_free_dma(priv);
1214
1215 return 0;
1216 }
1217
1218 static int __init fe_init(struct net_device *dev)
1219 {
1220 struct fe_priv *priv = netdev_priv(dev);
1221 struct device_node *port;
1222 int err;
1223
1224 BUG_ON(!priv->soc->reset_fe);
1225 priv->soc->reset_fe();
1226
1227 if (priv->soc->switch_init)
1228 priv->soc->switch_init(priv);
1229
1230 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1231 /*If the mac address is invalid, use random mac address */
1232 if (!is_valid_ether_addr(dev->dev_addr)) {
1233 random_ether_addr(dev->dev_addr);
1234 dev_err(priv->device, "generated random MAC address %pM\n",
1235 dev->dev_addr);
1236 }
1237
1238 err = fe_mdio_init(priv);
1239 if (err)
1240 return err;
1241
1242 if (priv->soc->port_init)
1243 for_each_child_of_node(priv->device->of_node, port)
1244 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1245 priv->soc->port_init(priv, port);
1246
1247 if (priv->phy) {
1248 err = priv->phy->connect(priv);
1249 if (err)
1250 goto err_phy_disconnect;
1251 }
1252
1253 err = fe_hw_init(dev);
1254 if (err)
1255 goto err_phy_disconnect;
1256
1257 if (priv->soc->switch_config)
1258 priv->soc->switch_config(priv);
1259
1260 return 0;
1261
1262 err_phy_disconnect:
1263 if (priv->phy)
1264 priv->phy->disconnect(priv);
1265 fe_mdio_cleanup(priv);
1266
1267 return err;
1268 }
1269
1270 static void fe_uninit(struct net_device *dev)
1271 {
1272 struct fe_priv *priv = netdev_priv(dev);
1273
1274 if (priv->phy)
1275 priv->phy->disconnect(priv);
1276 fe_mdio_cleanup(priv);
1277
1278 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1279 free_irq(dev->irq, dev);
1280 }
1281
1282 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1283 {
1284 struct fe_priv *priv = netdev_priv(dev);
1285
1286 if (!priv->phy_dev)
1287 return -ENODEV;
1288
1289 switch (cmd) {
1290 case SIOCETHTOOL:
1291 return phy_ethtool_ioctl(priv->phy_dev,
1292 (void *) ifr->ifr_data);
1293 case SIOCGMIIPHY:
1294 case SIOCGMIIREG:
1295 case SIOCSMIIREG:
1296 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1297 default:
1298 break;
1299 }
1300
1301 return -EOPNOTSUPP;
1302 }
1303
1304 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1305 {
1306 struct fe_priv *priv = netdev_priv(dev);
1307 int frag_size, old_mtu;
1308 u32 fwd_cfg;
1309
1310 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1311 return eth_change_mtu(dev, new_mtu);
1312
1313 frag_size = fe_max_frag_size(new_mtu);
1314 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1315 return -EINVAL;
1316
1317 old_mtu = dev->mtu;
1318 dev->mtu = new_mtu;
1319
1320 /* return early if the buffer sizes will not change */
1321 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1322 return 0;
1323 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1324 return 0;
1325
1326 if (new_mtu <= ETH_DATA_LEN)
1327 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1328 else
1329 priv->frag_size = PAGE_SIZE;
1330 priv->rx_buf_size = fe_max_buf_size(priv->frag_size);
1331
1332 if (!netif_running(dev))
1333 return 0;
1334
1335 fe_stop(dev);
1336 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1337 if (new_mtu <= ETH_DATA_LEN)
1338 fwd_cfg &= ~FE_GDM1_JMB_EN;
1339 else {
1340 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1341 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1342 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1343 }
1344 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1345
1346 return fe_open(dev);
1347 }
1348
1349 static const struct net_device_ops fe_netdev_ops = {
1350 .ndo_init = fe_init,
1351 .ndo_uninit = fe_uninit,
1352 .ndo_open = fe_open,
1353 .ndo_stop = fe_stop,
1354 .ndo_start_xmit = fe_start_xmit,
1355 .ndo_set_mac_address = fe_set_mac_address,
1356 .ndo_validate_addr = eth_validate_addr,
1357 .ndo_do_ioctl = fe_do_ioctl,
1358 .ndo_change_mtu = fe_change_mtu,
1359 .ndo_tx_timeout = fe_tx_timeout,
1360 .ndo_get_stats64 = fe_get_stats64,
1361 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1362 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1363 #ifdef CONFIG_NET_POLL_CONTROLLER
1364 .ndo_poll_controller = fe_poll_controller,
1365 #endif
1366 };
1367
1368 static void fe_reset_pending(struct fe_priv *priv)
1369 {
1370 struct net_device *dev = priv->netdev;
1371 int err;
1372
1373 rtnl_lock();
1374 fe_stop(dev);
1375
1376 err = fe_open(dev);
1377 if (err)
1378 goto error;
1379 rtnl_unlock();
1380
1381 return;
1382 error:
1383 netif_alert(priv, ifup, dev,
1384 "Driver up/down cycle failed, closing device.\n");
1385 dev_close(dev);
1386 rtnl_unlock();
1387 }
1388
1389 static const struct fe_work_t fe_work[] = {
1390 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1391 };
1392
1393 static void fe_pending_work(struct work_struct *work)
1394 {
1395 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1396 int i;
1397 bool pending;
1398
1399 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1400 pending = test_and_clear_bit(fe_work[i].bitnr,
1401 priv->pending_flags);
1402 if (pending)
1403 fe_work[i].action(priv);
1404 }
1405 }
1406
1407 static int fe_probe(struct platform_device *pdev)
1408 {
1409 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1410 const struct of_device_id *match;
1411 struct fe_soc_data *soc;
1412 struct net_device *netdev;
1413 struct fe_priv *priv;
1414 struct clk *sysclk;
1415 int err, napi_weight;
1416
1417 device_reset(&pdev->dev);
1418
1419 match = of_match_device(of_fe_match, &pdev->dev);
1420 soc = (struct fe_soc_data *) match->data;
1421
1422 if (soc->reg_table)
1423 fe_reg_table = soc->reg_table;
1424 else
1425 soc->reg_table = fe_reg_table;
1426
1427 fe_base = devm_ioremap_resource(&pdev->dev, res);
1428 if (!fe_base) {
1429 err = -EADDRNOTAVAIL;
1430 goto err_out;
1431 }
1432
1433 netdev = alloc_etherdev(sizeof(*priv));
1434 if (!netdev) {
1435 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1436 err = -ENOMEM;
1437 goto err_iounmap;
1438 }
1439
1440 SET_NETDEV_DEV(netdev, &pdev->dev);
1441 netdev->netdev_ops = &fe_netdev_ops;
1442 netdev->base_addr = (unsigned long) fe_base;
1443
1444 netdev->irq = platform_get_irq(pdev, 0);
1445 if (netdev->irq < 0) {
1446 dev_err(&pdev->dev, "no IRQ resource found\n");
1447 err = -ENXIO;
1448 goto err_free_dev;
1449 }
1450
1451 if (soc->init_data)
1452 soc->init_data(soc, netdev);
1453 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1454 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1455 netdev->vlan_features = netdev->hw_features &
1456 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1457 netdev->features |= netdev->hw_features;
1458
1459 /* fake rx vlan filter func. to support tx vlan offload func */
1460 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1461 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1462
1463 priv = netdev_priv(netdev);
1464 spin_lock_init(&priv->page_lock);
1465 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1466 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1467 if (!priv->hw_stats) {
1468 err = -ENOMEM;
1469 goto err_free_dev;
1470 }
1471 spin_lock_init(&priv->hw_stats->stats_lock);
1472 }
1473
1474 sysclk = devm_clk_get(&pdev->dev, NULL);
1475 if (!IS_ERR(sysclk))
1476 priv->sysclk = clk_get_rate(sysclk);
1477
1478 priv->netdev = netdev;
1479 priv->device = &pdev->dev;
1480 priv->soc = soc;
1481 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1482 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1483 priv->rx_buf_size = fe_max_buf_size(priv->frag_size);
1484 priv->tx_ring_size = priv->rx_ring_size = NUM_DMA_DESC;
1485 INIT_WORK(&priv->pending_work, fe_pending_work);
1486
1487 napi_weight = 32;
1488 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1489 napi_weight *= 4;
1490 priv->tx_ring_size *= 4;
1491 priv->rx_ring_size *= 4;
1492 }
1493 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1494 fe_set_ethtool_ops(netdev);
1495
1496 err = register_netdev(netdev);
1497 if (err) {
1498 dev_err(&pdev->dev, "error bringing up device\n");
1499 goto err_free_dev;
1500 }
1501
1502 platform_set_drvdata(pdev, netdev);
1503
1504 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1505 netdev->base_addr, netdev->irq);
1506
1507 return 0;
1508
1509 err_free_dev:
1510 free_netdev(netdev);
1511 err_iounmap:
1512 devm_iounmap(&pdev->dev, fe_base);
1513 err_out:
1514 return err;
1515 }
1516
1517 static int fe_remove(struct platform_device *pdev)
1518 {
1519 struct net_device *dev = platform_get_drvdata(pdev);
1520 struct fe_priv *priv = netdev_priv(dev);
1521
1522 netif_napi_del(&priv->rx_napi);
1523 if (priv->hw_stats)
1524 kfree(priv->hw_stats);
1525
1526 cancel_work_sync(&priv->pending_work);
1527
1528 unregister_netdev(dev);
1529 free_netdev(dev);
1530 platform_set_drvdata(pdev, NULL);
1531
1532 return 0;
1533 }
1534
1535 static struct platform_driver fe_driver = {
1536 .probe = fe_probe,
1537 .remove = fe_remove,
1538 .driver = {
1539 .name = "ralink_soc_eth",
1540 .owner = THIS_MODULE,
1541 .of_match_table = of_fe_match,
1542 },
1543 };
1544
1545 static int __init init_rtfe(void)
1546 {
1547 int ret;
1548
1549 ret = rtesw_init();
1550 if (ret)
1551 return ret;
1552
1553 ret = platform_driver_register(&fe_driver);
1554 if (ret)
1555 rtesw_exit();
1556
1557 return ret;
1558 }
1559
1560 static void __exit exit_rtfe(void)
1561 {
1562 platform_driver_unregister(&fe_driver);
1563 rtesw_exit();
1564 }
1565
1566 module_init(init_rtfe);
1567 module_exit(exit_rtfe);
1568
1569 MODULE_LICENSE("GPL");
1570 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1571 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1572 MODULE_VERSION(FE_DRV_VERSION);
OpenWrt Source Repository