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ralink: reduce access to uncached tx/rx dma ring buffer
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define TX_TIMEOUT (2 * HZ)
44 #define MAX_RX_LENGTH 1536
45 #define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
46 #define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
47 ETH_FCS_LEN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u32 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
79 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
80 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
81 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
82 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
83 };
84
85 static const u32 *fe_reg_table = fe_reg_table_default;
86
87 static void __iomem *fe_base = 0;
88
89 void fe_w32(u32 val, unsigned reg)
90 {
91 __raw_writel(val, fe_base + reg);
92 }
93
94 u32 fe_r32(unsigned reg)
95 {
96 return __raw_readl(fe_base + reg);
97 }
98
99 void fe_reg_w32(u32 val, enum fe_reg reg)
100 {
101 fe_w32(val, fe_reg_table[reg]);
102 }
103
104 u32 fe_reg_r32(enum fe_reg reg)
105 {
106 return fe_r32(fe_reg_table[reg]);
107 }
108
109 static inline void fe_int_disable(u32 mask)
110 {
111 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
112 FE_REG_FE_INT_ENABLE);
113 /* flush write */
114 fe_reg_r32(FE_REG_FE_INT_ENABLE);
115 }
116
117 static inline void fe_int_enable(u32 mask)
118 {
119 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
120 FE_REG_FE_INT_ENABLE);
121 /* flush write */
122 fe_reg_r32(FE_REG_FE_INT_ENABLE);
123 }
124
125 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
126 {
127 unsigned long flags;
128
129 spin_lock_irqsave(&priv->page_lock, flags);
130 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
131 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
132 FE_GDMA1_MAC_ADRL);
133 spin_unlock_irqrestore(&priv->page_lock, flags);
134 }
135
136 static int fe_set_mac_address(struct net_device *dev, void *p)
137 {
138 int ret = eth_mac_addr(dev, p);
139
140 if (!ret) {
141 struct fe_priv *priv = netdev_priv(dev);
142
143 if (priv->soc->set_mac)
144 priv->soc->set_mac(priv, dev->dev_addr);
145 else
146 fe_hw_set_macaddr(priv, p);
147 }
148
149 return ret;
150 }
151
152 static inline int fe_max_frag_size(int mtu)
153 {
154 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
155 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
156 }
157
158 static inline int fe_max_buf_size(int frag_size)
159 {
160 return frag_size - FE_RX_HLEN -
161 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
162 }
163
164 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
165 {
166 rxd->rxd1 = dma_rxd->rxd1;
167 rxd->rxd2 = dma_rxd->rxd2;
168 rxd->rxd3 = dma_rxd->rxd3;
169 rxd->rxd4 = dma_rxd->rxd4;
170 }
171
172 static inline void fe_get_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
173 {
174 txd->txd1 = dma_txd->txd1;
175 txd->txd2 = dma_txd->txd2;
176 txd->txd3 = dma_txd->txd3;
177 txd->txd4 = dma_txd->txd4;
178 }
179
180 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
181 {
182 dma_txd->txd1 = txd->txd1;
183 dma_txd->txd3 = txd->txd3;
184 dma_txd->txd4 = txd->txd4;
185 /* clean dma done flag last */
186 dma_txd->txd2 = txd->txd2;
187 }
188
189 static void fe_clean_rx(struct fe_priv *priv)
190 {
191 int i;
192
193 if (priv->rx_data) {
194 for (i = 0; i < NUM_DMA_DESC; i++)
195 if (priv->rx_data[i]) {
196 if (priv->rx_dma && priv->rx_dma[i].rxd1)
197 dma_unmap_single(&priv->netdev->dev,
198 priv->rx_dma[i].rxd1,
199 priv->rx_buf_size,
200 DMA_FROM_DEVICE);
201 put_page(virt_to_head_page(priv->rx_data[i]));
202 }
203
204 kfree(priv->rx_data);
205 priv->rx_data = NULL;
206 }
207
208 if (priv->rx_dma) {
209 dma_free_coherent(&priv->netdev->dev,
210 NUM_DMA_DESC * sizeof(*priv->rx_dma),
211 priv->rx_dma,
212 priv->rx_phys);
213 priv->rx_dma = NULL;
214 }
215 }
216
217 static int fe_alloc_rx(struct fe_priv *priv)
218 {
219 struct net_device *netdev = priv->netdev;
220 int i;
221
222 priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
223 GFP_KERNEL);
224 if (!priv->rx_data)
225 goto no_rx_mem;
226
227 for (i = 0; i < NUM_DMA_DESC; i++) {
228 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
229 if (!priv->rx_data[i])
230 goto no_rx_mem;
231 }
232
233 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
234 NUM_DMA_DESC * sizeof(*priv->rx_dma),
235 &priv->rx_phys,
236 GFP_ATOMIC | __GFP_ZERO);
237 if (!priv->rx_dma)
238 goto no_rx_mem;
239
240 for (i = 0; i < NUM_DMA_DESC; i++) {
241 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
242 priv->rx_data[i] + FE_RX_OFFSET,
243 priv->rx_buf_size,
244 DMA_FROM_DEVICE);
245 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
246 goto no_rx_mem;
247 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
248
249 if (priv->soc->rx_dma)
250 priv->soc->rx_dma(&priv->rx_dma[i], priv->rx_buf_size);
251 else
252 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
253 }
254 wmb();
255
256 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
257 fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
258 fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
259 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
260
261 return 0;
262
263 no_rx_mem:
264 return -ENOMEM;
265 }
266
267 static void fe_clean_tx(struct fe_priv *priv)
268 {
269 int i;
270
271 if (priv->tx_skb) {
272 for (i = 0; i < NUM_DMA_DESC; i++) {
273 if (priv->tx_skb[i])
274 dev_kfree_skb_any(priv->tx_skb[i]);
275 }
276 kfree(priv->tx_skb);
277 priv->tx_skb = NULL;
278 }
279
280 if (priv->tx_dma) {
281 dma_free_coherent(&priv->netdev->dev,
282 NUM_DMA_DESC * sizeof(*priv->tx_dma),
283 priv->tx_dma,
284 priv->tx_phys);
285 priv->tx_dma = NULL;
286 }
287 }
288
289 static int fe_alloc_tx(struct fe_priv *priv)
290 {
291 int i;
292
293 priv->tx_free_idx = 0;
294
295 priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
296 GFP_KERNEL);
297 if (!priv->tx_skb)
298 goto no_tx_mem;
299
300 priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
301 NUM_DMA_DESC * sizeof(*priv->tx_dma),
302 &priv->tx_phys,
303 GFP_ATOMIC | __GFP_ZERO);
304 if (!priv->tx_dma)
305 goto no_tx_mem;
306
307 for (i = 0; i < NUM_DMA_DESC; i++) {
308 if (priv->soc->tx_dma) {
309 priv->soc->tx_dma(&priv->tx_dma[i]);
310 continue;
311 }
312 priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
313 }
314 wmb();
315
316 fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
317 fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
318 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
319 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
320
321 return 0;
322
323 no_tx_mem:
324 return -ENOMEM;
325 }
326
327 static int fe_init_dma(struct fe_priv *priv)
328 {
329 int err;
330
331 err = fe_alloc_tx(priv);
332 if (err)
333 return err;
334
335 err = fe_alloc_rx(priv);
336 if (err)
337 return err;
338
339 return 0;
340 }
341
342 static void fe_free_dma(struct fe_priv *priv)
343 {
344 fe_clean_tx(priv);
345 fe_clean_rx(priv);
346
347 netdev_reset_queue(priv->netdev);
348 }
349
350 static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
351 {
352 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
353 dma_unmap_single(dev, txd->txd1,
354 TX_DMA_GET_PLEN0(txd->txd2),
355 DMA_TO_DEVICE);
356 }
357
358 static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
359 {
360 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
361 dma_unmap_page(dev, txd->txd1,
362 TX_DMA_GET_PLEN0(txd->txd2),
363 DMA_TO_DEVICE);
364 }
365
366 static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
367 {
368 if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
369 dma_unmap_page(dev, txd->txd3,
370 TX_DMA_GET_PLEN1(txd->txd2),
371 DMA_TO_DEVICE);
372 }
373
374 void fe_stats_update(struct fe_priv *priv)
375 {
376 struct fe_hw_stats *hwstats = priv->hw_stats;
377 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
378
379 u64_stats_update_begin(&hwstats->syncp);
380
381 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
382 hwstats->rx_bytes += fe_r32(base);
383 hwstats->rx_packets += fe_r32(base + 0x08);
384 hwstats->rx_overflow += fe_r32(base + 0x10);
385 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
386 hwstats->rx_short_errors += fe_r32(base + 0x18);
387 hwstats->rx_long_errors += fe_r32(base + 0x1c);
388 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
389 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
390 hwstats->tx_skip += fe_r32(base + 0x28);
391 hwstats->tx_collisions += fe_r32(base + 0x2c);
392 hwstats->tx_bytes += fe_r32(base + 0x30);
393 hwstats->tx_packets += fe_r32(base + 0x38);
394 } else {
395 hwstats->tx_bytes += fe_r32(base);
396 hwstats->tx_packets += fe_r32(base + 0x04);
397 hwstats->tx_skip += fe_r32(base + 0x08);
398 hwstats->tx_collisions += fe_r32(base + 0x0c);
399 hwstats->rx_bytes += fe_r32(base + 0x20);
400 hwstats->rx_packets += fe_r32(base + 0x24);
401 hwstats->rx_overflow += fe_r32(base + 0x28);
402 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
403 hwstats->rx_short_errors += fe_r32(base + 0x30);
404 hwstats->rx_long_errors += fe_r32(base + 0x34);
405 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
406 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
407 }
408
409 u64_stats_update_end(&hwstats->syncp);
410 }
411
412 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
413 struct rtnl_link_stats64 *storage)
414 {
415 struct fe_priv *priv = netdev_priv(dev);
416 struct fe_hw_stats *hwstats = priv->hw_stats;
417 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
418 unsigned int start;
419
420 if (!base) {
421 netdev_stats_to_stats64(storage, &dev->stats);
422 return storage;
423 }
424
425 if (netif_running(dev) && netif_device_present(dev)) {
426 if (spin_trylock(&hwstats->stats_lock)) {
427 fe_stats_update(priv);
428 spin_unlock(&hwstats->stats_lock);
429 }
430 }
431
432 do {
433 start = u64_stats_fetch_begin_bh(&hwstats->syncp);
434 storage->rx_packets = hwstats->rx_packets;
435 storage->tx_packets = hwstats->tx_packets;
436 storage->rx_bytes = hwstats->rx_bytes;
437 storage->tx_bytes = hwstats->tx_bytes;
438 storage->collisions = hwstats->tx_collisions;
439 storage->rx_length_errors = hwstats->rx_short_errors +
440 hwstats->rx_long_errors;
441 storage->rx_over_errors = hwstats->rx_overflow;
442 storage->rx_crc_errors = hwstats->rx_fcs_errors;
443 storage->rx_errors = hwstats->rx_checksum_errors;
444 storage->tx_aborted_errors = hwstats->tx_skip;
445 } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
446
447 storage->tx_errors = priv->netdev->stats.tx_errors;
448 storage->rx_dropped = priv->netdev->stats.rx_dropped;
449 storage->tx_dropped = priv->netdev->stats.tx_dropped;
450
451 return storage;
452 }
453
454 static int fe_vlan_rx_add_vid(struct net_device *dev,
455 __be16 proto, u16 vid)
456 {
457 struct fe_priv *priv = netdev_priv(dev);
458 u32 idx = (vid & 0xf);
459 u32 vlan_cfg;
460
461 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
462 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
463 return 0;
464
465 if (test_bit(idx, &priv->vlan_map)) {
466 netdev_warn(dev, "disable tx vlan offload\n");
467 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
468 netdev_update_features(dev);
469 } else {
470 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
471 ((idx >> 1) << 2));
472 if (idx & 0x1) {
473 vlan_cfg &= 0xffff;
474 vlan_cfg |= (vid << 16);
475 } else {
476 vlan_cfg &= 0xffff0000;
477 vlan_cfg |= vid;
478 }
479 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
480 ((idx >> 1) << 2));
481 set_bit(idx, &priv->vlan_map);
482 }
483
484 return 0;
485 }
486
487 static int fe_vlan_rx_kill_vid(struct net_device *dev,
488 __be16 proto, u16 vid)
489 {
490 struct fe_priv *priv = netdev_priv(dev);
491 u32 idx = (vid & 0xf);
492
493 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
494 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
495 return 0;
496
497 clear_bit(idx, &priv->vlan_map);
498
499 return 0;
500 }
501
502 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
503 int idx)
504 {
505 struct fe_priv *priv = netdev_priv(dev);
506 struct skb_frag_struct *frag;
507 struct fe_tx_dma txd, *ptxd;
508 dma_addr_t mapped_addr;
509 unsigned int nr_frags;
510 u32 def_txd4;
511 int i, j, unmap_idx, tx_num;
512
513 memset(&txd, 0, sizeof(txd));
514 nr_frags = skb_shinfo(skb)->nr_frags;
515 tx_num = 1 + (nr_frags >> 1);
516
517 /* init tx descriptor */
518 if (priv->soc->tx_dma)
519 priv->soc->tx_dma(&txd);
520 else
521 txd.txd4 = TX_DMA_DESP4_DEF;
522 def_txd4 = txd.txd4;
523
524 /* use dma_unmap_single to free it */
525 txd.txd4 |= priv->soc->tx_udf_bit;
526
527 /* TX Checksum offload */
528 if (skb->ip_summed == CHECKSUM_PARTIAL)
529 txd.txd4 |= TX_DMA_CHKSUM;
530
531 /* VLAN header offload */
532 if (vlan_tx_tag_present(skb)) {
533 if (IS_ENABLED(CONFIG_SOC_MT7621))
534 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
535 else
536 txd.txd4 |= TX_DMA_INS_VLAN |
537 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
538 (vlan_tx_tag_get(skb) & 0xF);
539 }
540
541 /* TSO: fill MSS info in tcp checksum field */
542 if (skb_is_gso(skb)) {
543 if (skb_cow_head(skb, 0)) {
544 netif_warn(priv, tx_err, dev,
545 "GSO expand head fail.\n");
546 goto err_out;
547 }
548 if (skb_shinfo(skb)->gso_type &
549 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
550 txd.txd4 |= TX_DMA_TSO;
551 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
552 }
553 }
554
555 mapped_addr = dma_map_single(&dev->dev, skb->data,
556 skb_headlen(skb), DMA_TO_DEVICE);
557 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
558 goto err_out;
559 txd.txd1 = mapped_addr;
560 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
561
562 /* TX SG offload */
563 j = idx;
564 for (i = 0; i < nr_frags; i++) {
565
566 frag = &skb_shinfo(skb)->frags[i];
567 mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
568 skb_frag_size(frag), DMA_TO_DEVICE);
569 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
570 goto err_dma;
571
572 if (i & 0x1) {
573 j = NEXT_TX_DESP_IDX(j);
574 txd.txd1 = mapped_addr;
575 txd.txd2 = TX_DMA_PLEN0(frag->size);
576 txd.txd4 = def_txd4;
577 } else {
578 txd.txd3 = mapped_addr;
579 txd.txd2 |= TX_DMA_PLEN1(frag->size);
580 if (i != (nr_frags -1)) {
581 fe_set_txd(&txd, &priv->tx_dma[j]);
582 memset(&txd, 0, sizeof(txd));
583 }
584 priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
585 }
586 }
587
588 /* set last segment */
589 if (nr_frags & 0x1)
590 txd.txd2 |= TX_DMA_LS1;
591 else
592 txd.txd2 |= TX_DMA_LS0;
593 fe_set_txd(&txd, &priv->tx_dma[j]);
594
595 /* store skb to cleanup */
596 priv->tx_skb[j] = skb;
597
598 netdev_sent_queue(dev, skb->len);
599 skb_tx_timestamp(skb);
600
601 wmb();
602 j = NEXT_TX_DESP_IDX(j);
603 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
604
605 return 0;
606
607 err_dma:
608 /* unmap dma */
609 ptxd = &priv->tx_dma[idx];
610 txd_unmap_single(&dev->dev, ptxd);
611
612 j = idx;
613 unmap_idx = i;
614 for (i = 0; i < unmap_idx; i++) {
615 if (i & 0x1) {
616 j = NEXT_TX_DESP_IDX(j);
617 ptxd = &priv->tx_dma[j];
618 txd_unmap_page0(&dev->dev, ptxd);
619 } else {
620 txd_unmap_page1(&dev->dev, ptxd);
621 }
622 }
623
624 err_out:
625 /* reinit descriptors and skb */
626 j = idx;
627 for (i = 0; i < tx_num; i++) {
628 priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
629 priv->tx_skb[j] = NULL;
630 j = NEXT_TX_DESP_IDX(j);
631 }
632 wmb();
633
634 return -1;
635 }
636
637 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
638 unsigned int len;
639 int ret;
640
641 ret = 0;
642 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
643 if ((priv->flags & FE_FLAG_PADDING_64B) &&
644 !(priv->flags & FE_FLAG_PADDING_BUG))
645 return ret;
646
647 if (vlan_tx_tag_present(skb))
648 len = ETH_ZLEN;
649 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
650 len = VLAN_ETH_ZLEN;
651 else if(!(priv->flags & FE_FLAG_PADDING_64B))
652 len = ETH_ZLEN;
653 else
654 return ret;
655
656 if (skb->len < len) {
657 if ((ret = skb_pad(skb, len - skb->len)) < 0)
658 return ret;
659 skb->len = len;
660 skb_set_tail_pointer(skb, len);
661 }
662 }
663
664 return ret;
665 }
666
667 static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
668 {
669 return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
670 (NUM_DMA_DESC - 1)));
671 }
672
673 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
674 {
675 struct fe_priv *priv = netdev_priv(dev);
676 struct net_device_stats *stats = &dev->stats;
677 u32 tx;
678 int tx_num;
679 int len = skb->len;
680
681 if (fe_skb_padto(skb, priv)) {
682 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
683 return NETDEV_TX_OK;
684 }
685
686 spin_lock(&priv->page_lock);
687 tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
688 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
689 if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
690 {
691 netif_stop_queue(dev);
692 spin_unlock(&priv->page_lock);
693 netif_err(priv, tx_queued,dev,
694 "Tx Ring full when queue awake!\n");
695 return NETDEV_TX_BUSY;
696 }
697
698 if (fe_tx_map_dma(skb, dev, tx) < 0) {
699 kfree_skb(skb);
700
701 stats->tx_dropped++;
702 } else {
703 stats->tx_packets++;
704 stats->tx_bytes += len;
705 }
706
707 spin_unlock(&priv->page_lock);
708
709 return NETDEV_TX_OK;
710 }
711
712 static inline void fe_rx_vlan(struct sk_buff *skb)
713 {
714 struct ethhdr *ehdr;
715 u16 vlanid;
716
717 if (!__vlan_get_tag(skb, &vlanid)) {
718 /* pop the vlan tag */
719 ehdr = (struct ethhdr *)skb->data;
720 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
721 skb_pull(skb, VLAN_HLEN);
722 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
723 }
724 }
725
726 static int fe_poll_rx(struct napi_struct *napi, int budget,
727 struct fe_priv *priv)
728 {
729 struct net_device *netdev = priv->netdev;
730 struct net_device_stats *stats = &netdev->stats;
731 struct fe_soc_data *soc = priv->soc;
732 u32 checksum_bit;
733 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
734 struct sk_buff *skb;
735 u8 *data, *new_data;
736 struct fe_rx_dma *rxd, trxd;
737 int done = 0;
738 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
739
740 if (netdev->features & NETIF_F_RXCSUM)
741 checksum_bit = soc->checksum_bit;
742 else
743 checksum_bit = 0;
744
745 while (done < budget) {
746 unsigned int pktlen;
747 dma_addr_t dma_addr;
748 idx = NEXT_RX_DESP_IDX(idx);
749 rxd = &priv->rx_dma[idx];
750 data = priv->rx_data[idx];
751
752 fe_get_rxd(&trxd, rxd);
753 if (!(trxd.rxd2 & RX_DMA_DONE))
754 break;
755
756 /* alloc new buffer */
757 new_data = netdev_alloc_frag(priv->frag_size);
758 if (unlikely(!new_data)) {
759 stats->rx_dropped++;
760 goto release_desc;
761 }
762 dma_addr = dma_map_single(&netdev->dev,
763 new_data + FE_RX_OFFSET,
764 priv->rx_buf_size,
765 DMA_FROM_DEVICE);
766 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
767 put_page(virt_to_head_page(new_data));
768 goto release_desc;
769 }
770
771 /* receive data */
772 skb = build_skb(data, priv->frag_size);
773 if (unlikely(!skb)) {
774 put_page(virt_to_head_page(new_data));
775 goto release_desc;
776 }
777 skb_reserve(skb, FE_RX_OFFSET);
778
779 dma_unmap_single(&netdev->dev, trxd.rxd1,
780 priv->rx_buf_size, DMA_FROM_DEVICE);
781 pktlen = RX_DMA_PLEN0(trxd.rxd2);
782 skb_put(skb, pktlen);
783 skb->dev = netdev;
784 if (trxd.rxd4 & checksum_bit) {
785 skb->ip_summed = CHECKSUM_UNNECESSARY;
786 } else {
787 skb_checksum_none_assert(skb);
788 }
789 if (rx_vlan)
790 fe_rx_vlan(skb);
791 skb->protocol = eth_type_trans(skb, netdev);
792
793 stats->rx_packets++;
794 stats->rx_bytes += pktlen;
795
796 if (skb->ip_summed == CHECKSUM_NONE)
797 netif_receive_skb(skb);
798 else
799 napi_gro_receive(napi, skb);
800
801 priv->rx_data[idx] = new_data;
802 rxd->rxd1 = (unsigned int) dma_addr;
803
804 release_desc:
805 if (soc->rx_dma)
806 soc->rx_dma(rxd, priv->rx_buf_size);
807 else
808 rxd->rxd2 = RX_DMA_LSO;
809
810 wmb();
811 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
812 done++;
813 }
814
815 return done;
816 }
817
818 static int fe_poll_tx(struct fe_priv *priv, int budget)
819 {
820 struct net_device *netdev = priv->netdev;
821 struct device *dev = &netdev->dev;
822 unsigned int bytes_compl = 0;
823 struct sk_buff *skb;
824 struct fe_tx_dma txd;
825 int done = 0, idx;
826 u32 udf_bit = priv->soc->tx_udf_bit;
827
828 idx = priv->tx_free_idx;
829 while (done < budget) {
830 fe_get_txd(&txd, &priv->tx_dma[idx]);
831 skb = priv->tx_skb[idx];
832
833 if (!(txd.txd2 & TX_DMA_DONE) || !skb)
834 break;
835
836 txd_unmap_page1(dev, &txd);
837
838 if (txd.txd4 & udf_bit)
839 txd_unmap_single(dev, &txd);
840 else
841 txd_unmap_page0(dev, &txd);
842
843 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
844 bytes_compl += skb->len;
845 dev_kfree_skb_any(skb);
846 done++;
847 }
848 priv->tx_skb[idx] = NULL;
849 idx = NEXT_TX_DESP_IDX(idx);
850 }
851 priv->tx_free_idx = idx;
852
853 if (!done)
854 return 0;
855
856 netdev_completed_queue(netdev, done, bytes_compl);
857 if (unlikely(netif_queue_stopped(netdev) &&
858 netif_carrier_ok(netdev))) {
859 netif_wake_queue(netdev);
860 }
861
862 return done;
863 }
864
865 static int fe_poll(struct napi_struct *napi, int budget)
866 {
867 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
868 struct fe_hw_stats *hwstat = priv->hw_stats;
869 int tx_done, rx_done;
870 u32 status, mask;
871 u32 tx_intr, rx_intr;
872
873 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
874 tx_intr = priv->soc->tx_int;
875 rx_intr = priv->soc->rx_int;
876 tx_done = rx_done = 0;
877
878 poll_again:
879 if (status & tx_intr) {
880 tx_done += fe_poll_tx(priv, budget - tx_done);
881 if (tx_done < budget) {
882 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
883 }
884 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
885 }
886
887 if (status & rx_intr) {
888 rx_done += fe_poll_rx(napi, budget - rx_done, priv);
889 if (rx_done < budget) {
890 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
891 }
892 }
893
894 if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
895 if (spin_trylock(&hwstat->stats_lock)) {
896 fe_stats_update(priv);
897 spin_unlock(&hwstat->stats_lock);
898 }
899 fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
900 }
901
902 if (unlikely(netif_msg_intr(priv))) {
903 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
904 netdev_info(priv->netdev,
905 "done tx %d, rx %d, intr 0x%x/0x%x\n",
906 tx_done, rx_done, status, mask);
907 }
908
909 if ((tx_done < budget) && (rx_done < budget)) {
910 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
911 if (status & (tx_intr | rx_intr )) {
912 goto poll_again;
913 }
914 napi_complete(napi);
915 fe_int_enable(tx_intr | rx_intr);
916 }
917
918 return rx_done;
919 }
920
921 static void fe_tx_timeout(struct net_device *dev)
922 {
923 struct fe_priv *priv = netdev_priv(dev);
924
925 priv->netdev->stats.tx_errors++;
926 netif_err(priv, tx_err, dev,
927 "transmit timed out, waking up the queue\n");
928 netif_info(priv, drv, dev, ": dma_cfg:%08x, free_idx:%d, " \
929 "dma_ctx_idx=%u, dma_crx_idx=%u\n",
930 fe_reg_r32(FE_REG_PDMA_GLO_CFG), priv->tx_free_idx,
931 fe_reg_r32(FE_REG_TX_CTX_IDX0),
932 fe_reg_r32(FE_REG_RX_CALC_IDX0));
933 netif_wake_queue(dev);
934 }
935
936 static irqreturn_t fe_handle_irq(int irq, void *dev)
937 {
938 struct fe_priv *priv = netdev_priv(dev);
939 u32 status, int_mask;
940
941 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
942
943 if (unlikely(!status))
944 return IRQ_NONE;
945
946 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
947 if (likely(status & int_mask)) {
948 fe_int_disable(int_mask);
949 napi_schedule(&priv->rx_napi);
950 } else {
951 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
952 }
953
954 return IRQ_HANDLED;
955 }
956
957 #ifdef CONFIG_NET_POLL_CONTROLLER
958 static void fe_poll_controller(struct net_device *dev)
959 {
960 struct fe_priv *priv = netdev_priv(dev);
961 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
962
963 fe_int_disable(int_mask);
964 fe_handle_irq(dev->irq, dev);
965 fe_int_enable(int_mask);
966 }
967 #endif
968
969 int fe_set_clock_cycle(struct fe_priv *priv)
970 {
971 unsigned long sysclk = priv->sysclk;
972
973 if (!sysclk) {
974 return -EINVAL;
975 }
976
977 sysclk /= FE_US_CYC_CNT_DIVISOR;
978 sysclk <<= FE_US_CYC_CNT_SHIFT;
979
980 fe_w32((fe_r32(FE_FE_GLO_CFG) &
981 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
982 sysclk,
983 FE_FE_GLO_CFG);
984 return 0;
985 }
986
987 void fe_fwd_config(struct fe_priv *priv)
988 {
989 u32 fwd_cfg;
990
991 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
992
993 /* disable jumbo frame */
994 if (priv->flags & FE_FLAG_JUMBO_FRAME)
995 fwd_cfg &= ~FE_GDM1_JMB_EN;
996
997 /* set unicast/multicast/broadcast frame to cpu */
998 fwd_cfg &= ~0xffff;
999
1000 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1001 }
1002
1003 static void fe_rxcsum_config(bool enable)
1004 {
1005 if (enable)
1006 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1007 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1008 FE_GDMA1_FWD_CFG);
1009 else
1010 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1011 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1012 FE_GDMA1_FWD_CFG);
1013 }
1014
1015 static void fe_txcsum_config(bool enable)
1016 {
1017 if (enable)
1018 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1019 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1020 FE_CDMA_CSG_CFG);
1021 else
1022 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1023 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1024 FE_CDMA_CSG_CFG);
1025 }
1026
1027 void fe_csum_config(struct fe_priv *priv)
1028 {
1029 struct net_device *dev = priv_netdev(priv);
1030
1031 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1032 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1033 }
1034
1035 static int fe_hw_init(struct net_device *dev)
1036 {
1037 struct fe_priv *priv = netdev_priv(dev);
1038 int i, err;
1039
1040 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1041 dev_name(priv->device), dev);
1042 if (err)
1043 return err;
1044
1045 if (priv->soc->set_mac)
1046 priv->soc->set_mac(priv, dev->dev_addr);
1047 else
1048 fe_hw_set_macaddr(priv, dev->dev_addr);
1049
1050 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1051
1052 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1053 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1054 for (i = 0; i < 16; i += 2)
1055 fe_w32(((i + 1) << 16) + i,
1056 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1057 (i * 2));
1058
1059 BUG_ON(!priv->soc->fwd_config);
1060 if (priv->soc->fwd_config(priv))
1061 netdev_err(dev, "unable to get clock\n");
1062
1063 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1064 fe_reg_w32(1, FE_REG_FE_RST_GL);
1065 fe_reg_w32(0, FE_REG_FE_RST_GL);
1066 }
1067
1068 return 0;
1069 }
1070
1071 static int fe_open(struct net_device *dev)
1072 {
1073 struct fe_priv *priv = netdev_priv(dev);
1074 unsigned long flags;
1075 u32 val;
1076 int err;
1077
1078 err = fe_init_dma(priv);
1079 if (err)
1080 goto err_out;
1081
1082 spin_lock_irqsave(&priv->page_lock, flags);
1083 napi_enable(&priv->rx_napi);
1084
1085 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1086 val |= priv->soc->pdma_glo_cfg;
1087 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1088
1089 spin_unlock_irqrestore(&priv->page_lock, flags);
1090
1091 if (priv->phy)
1092 priv->phy->start(priv);
1093
1094 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1095 netif_carrier_on(dev);
1096
1097 netif_start_queue(dev);
1098 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1099
1100 return 0;
1101
1102 err_out:
1103 fe_free_dma(priv);
1104 return err;
1105 }
1106
1107 static int fe_stop(struct net_device *dev)
1108 {
1109 struct fe_priv *priv = netdev_priv(dev);
1110 unsigned long flags;
1111 int i;
1112
1113 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1114
1115 netif_tx_disable(dev);
1116
1117 if (priv->phy)
1118 priv->phy->stop(priv);
1119
1120 spin_lock_irqsave(&priv->page_lock, flags);
1121 napi_disable(&priv->rx_napi);
1122
1123 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1124 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1125 FE_REG_PDMA_GLO_CFG);
1126 spin_unlock_irqrestore(&priv->page_lock, flags);
1127
1128 /* wait dma stop */
1129 for (i = 0; i < 10; i++) {
1130 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1131 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1132 msleep(10);
1133 continue;
1134 }
1135 break;
1136 }
1137
1138 fe_free_dma(priv);
1139
1140 return 0;
1141 }
1142
1143 static int __init fe_init(struct net_device *dev)
1144 {
1145 struct fe_priv *priv = netdev_priv(dev);
1146 struct device_node *port;
1147 int err;
1148
1149 BUG_ON(!priv->soc->reset_fe);
1150 priv->soc->reset_fe();
1151
1152 if (priv->soc->switch_init)
1153 priv->soc->switch_init(priv);
1154
1155 memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
1156 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1157
1158 err = fe_mdio_init(priv);
1159 if (err)
1160 return err;
1161
1162 if (priv->soc->port_init)
1163 for_each_child_of_node(priv->device->of_node, port)
1164 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1165 priv->soc->port_init(priv, port);
1166
1167 if (priv->phy) {
1168 err = priv->phy->connect(priv);
1169 if (err)
1170 goto err_phy_disconnect;
1171 }
1172
1173 err = fe_hw_init(dev);
1174 if (err)
1175 goto err_phy_disconnect;
1176
1177 if (priv->soc->switch_config)
1178 priv->soc->switch_config(priv);
1179
1180 return 0;
1181
1182 err_phy_disconnect:
1183 if (priv->phy)
1184 priv->phy->disconnect(priv);
1185 fe_mdio_cleanup(priv);
1186
1187 return err;
1188 }
1189
1190 static void fe_uninit(struct net_device *dev)
1191 {
1192 struct fe_priv *priv = netdev_priv(dev);
1193
1194 if (priv->phy)
1195 priv->phy->disconnect(priv);
1196 fe_mdio_cleanup(priv);
1197
1198 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1199 free_irq(dev->irq, dev);
1200 }
1201
1202 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1203 {
1204 struct fe_priv *priv = netdev_priv(dev);
1205
1206 if (!priv->phy_dev)
1207 return -ENODEV;
1208
1209 switch (cmd) {
1210 case SIOCETHTOOL:
1211 return phy_ethtool_ioctl(priv->phy_dev,
1212 (void *) ifr->ifr_data);
1213 case SIOCGMIIPHY:
1214 case SIOCGMIIREG:
1215 case SIOCSMIIREG:
1216 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1217 default:
1218 break;
1219 }
1220
1221 return -EOPNOTSUPP;
1222 }
1223
1224 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1225 {
1226 struct fe_priv *priv = netdev_priv(dev);
1227 int frag_size, old_mtu;
1228 u32 fwd_cfg;
1229
1230 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1231 return eth_change_mtu(dev, new_mtu);
1232
1233 frag_size = fe_max_frag_size(new_mtu);
1234 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1235 return -EINVAL;
1236
1237 old_mtu = dev->mtu;
1238 dev->mtu = new_mtu;
1239
1240 /* return early if the buffer sizes will not change */
1241 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1242 return 0;
1243 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1244 return 0;
1245
1246 if (new_mtu <= ETH_DATA_LEN) {
1247 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1248 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1249 } else {
1250 priv->frag_size = PAGE_SIZE;
1251 priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
1252 }
1253
1254 if (!netif_running(dev))
1255 return 0;
1256
1257 fe_stop(dev);
1258 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1259 if (new_mtu <= ETH_DATA_LEN)
1260 fwd_cfg &= ~FE_GDM1_JMB_EN;
1261 else {
1262 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1263 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1264 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1265 }
1266 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1267
1268 return fe_open(dev);
1269 }
1270
1271 static const struct net_device_ops fe_netdev_ops = {
1272 .ndo_init = fe_init,
1273 .ndo_uninit = fe_uninit,
1274 .ndo_open = fe_open,
1275 .ndo_stop = fe_stop,
1276 .ndo_start_xmit = fe_start_xmit,
1277 .ndo_set_mac_address = fe_set_mac_address,
1278 .ndo_validate_addr = eth_validate_addr,
1279 .ndo_do_ioctl = fe_do_ioctl,
1280 .ndo_change_mtu = fe_change_mtu,
1281 .ndo_tx_timeout = fe_tx_timeout,
1282 .ndo_get_stats64 = fe_get_stats64,
1283 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1284 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1285 #ifdef CONFIG_NET_POLL_CONTROLLER
1286 .ndo_poll_controller = fe_poll_controller,
1287 #endif
1288 };
1289
1290 static int fe_probe(struct platform_device *pdev)
1291 {
1292 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293 const struct of_device_id *match;
1294 struct fe_soc_data *soc;
1295 struct net_device *netdev;
1296 struct fe_priv *priv;
1297 struct clk *sysclk;
1298 int err;
1299
1300 device_reset(&pdev->dev);
1301
1302 match = of_match_device(of_fe_match, &pdev->dev);
1303 soc = (struct fe_soc_data *) match->data;
1304
1305 if (soc->reg_table)
1306 fe_reg_table = soc->reg_table;
1307 else
1308 soc->reg_table = fe_reg_table;
1309
1310 fe_base = devm_request_and_ioremap(&pdev->dev, res);
1311 if (!fe_base) {
1312 err = -EADDRNOTAVAIL;
1313 goto err_out;
1314 }
1315
1316 netdev = alloc_etherdev(sizeof(*priv));
1317 if (!netdev) {
1318 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1319 err = -ENOMEM;
1320 goto err_iounmap;
1321 }
1322
1323 SET_NETDEV_DEV(netdev, &pdev->dev);
1324 netdev->netdev_ops = &fe_netdev_ops;
1325 netdev->base_addr = (unsigned long) fe_base;
1326 netdev->watchdog_timeo = TX_TIMEOUT;
1327
1328 netdev->irq = platform_get_irq(pdev, 0);
1329 if (netdev->irq < 0) {
1330 dev_err(&pdev->dev, "no IRQ resource found\n");
1331 err = -ENXIO;
1332 goto err_free_dev;
1333 }
1334
1335 if (soc->init_data)
1336 soc->init_data(soc, netdev);
1337 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1338 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1339 netdev->vlan_features = netdev->hw_features &
1340 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1341 netdev->features |= netdev->hw_features;
1342
1343 /* fake rx vlan filter func. to support tx vlan offload func */
1344 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1345 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1346
1347 priv = netdev_priv(netdev);
1348 spin_lock_init(&priv->page_lock);
1349 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1350 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1351 if (!priv->hw_stats) {
1352 err = -ENOMEM;
1353 goto err_free_dev;
1354 }
1355 spin_lock_init(&priv->hw_stats->stats_lock);
1356 }
1357
1358 sysclk = devm_clk_get(&pdev->dev, NULL);
1359 if (!IS_ERR(sysclk))
1360 priv->sysclk = clk_get_rate(sysclk);
1361
1362 priv->netdev = netdev;
1363 priv->device = &pdev->dev;
1364 priv->soc = soc;
1365 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1366 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1367 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1368 if (priv->frag_size > PAGE_SIZE) {
1369 dev_err(&pdev->dev, "error frag size.\n");
1370 err = -EINVAL;
1371 goto err_free_dev;
1372 }
1373
1374 netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
1375 fe_set_ethtool_ops(netdev);
1376
1377 err = register_netdev(netdev);
1378 if (err) {
1379 dev_err(&pdev->dev, "error bringing up device\n");
1380 goto err_free_dev;
1381 }
1382
1383 platform_set_drvdata(pdev, netdev);
1384
1385 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1386 netdev->base_addr, netdev->irq);
1387
1388 return 0;
1389
1390 err_free_dev:
1391 free_netdev(netdev);
1392 err_iounmap:
1393 devm_iounmap(&pdev->dev, fe_base);
1394 err_out:
1395 return err;
1396 }
1397
1398 static int fe_remove(struct platform_device *pdev)
1399 {
1400 struct net_device *dev = platform_get_drvdata(pdev);
1401 struct fe_priv *priv = netdev_priv(dev);
1402
1403 netif_napi_del(&priv->rx_napi);
1404 if (priv->hw_stats)
1405 kfree(priv->hw_stats);
1406
1407 unregister_netdev(dev);
1408 free_netdev(dev);
1409 platform_set_drvdata(pdev, NULL);
1410
1411 return 0;
1412 }
1413
1414 static struct platform_driver fe_driver = {
1415 .probe = fe_probe,
1416 .remove = fe_remove,
1417 .driver = {
1418 .name = "ralink_soc_eth",
1419 .owner = THIS_MODULE,
1420 .of_match_table = of_fe_match,
1421 },
1422 };
1423
1424 static int __init init_rtfe(void)
1425 {
1426 int ret;
1427
1428 ret = rtesw_init();
1429 if (ret)
1430 return ret;
1431
1432 ret = platform_driver_register(&fe_driver);
1433 if (ret)
1434 rtesw_exit();
1435
1436 return ret;
1437 }
1438
1439 static void __exit exit_rtfe(void)
1440 {
1441 platform_driver_unregister(&fe_driver);
1442 rtesw_exit();
1443 }
1444
1445 module_init(init_rtfe);
1446 module_exit(exit_rtfe);
1447
1448 MODULE_LICENSE("GPL");
1449 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1450 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1451 MODULE_VERSION(FE_DRV_VERSION);
OpenWrt Source Repository