target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   based on Ralink SDK3.3
  16  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  17  */
  18
  19 #ifndef FE_ETH_H
  20 #define FE_ETH_H
  21
  22 #include <linux/mii.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/phy.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/version.h>
  29
  30 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,15,0)
  31 #define u64_stats_fetch_retry_irq u64_stats_fetch_retry_bh
  32 #define u64_stats_fetch_begin_irq u64_stats_fetch_begin_bh
  33 #endif
  34
  35 enum fe_reg {
  36         FE_REG_PDMA_GLO_CFG = 0,
  37         FE_REG_PDMA_RST_CFG,
  38         FE_REG_DLY_INT_CFG,
  39         FE_REG_TX_BASE_PTR0,
  40         FE_REG_TX_MAX_CNT0,
  41         FE_REG_TX_CTX_IDX0,
  42         FE_REG_TX_DTX_IDX0,
  43         FE_REG_RX_BASE_PTR0,
  44         FE_REG_RX_MAX_CNT0,
  45         FE_REG_RX_CALC_IDX0,
  46         FE_REG_RX_DRX_IDX0,
  47         FE_REG_FE_INT_ENABLE,
  48         FE_REG_FE_INT_STATUS,
  49         FE_REG_FE_DMA_VID_BASE,
  50         FE_REG_FE_COUNTER_BASE,
  51         FE_REG_FE_RST_GL,
  52         FE_REG_FE_INT_STATUS2,
  53         FE_REG_COUNT
  54 };
  55
  56 enum fe_work_flag {
  57         FE_FLAG_RESET_PENDING,
  58         FE_FLAG_MAX
  59 };
  60
  61 #define FE_DRV_VERSION          "0.1.2"
  62
  63 /* power of 2 to let NEXT_TX_DESP_IDX work */
  64 #define NUM_DMA_DESC            (1 << 7)
  65 #define MAX_DMA_DESC            0xfff
  66
  67 #define FE_DELAY_EN_INT         0x80
  68 #define FE_DELAY_MAX_INT        0x04
  69 #define FE_DELAY_MAX_TOUT       0x04
  70 #define FE_DELAY_TIME           20
  71 #define FE_DELAY_CHAN           (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
  72 #define FE_DELAY_INIT           ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
  73 #define FE_PSE_FQFC_CFG_INIT    0x80504000
  74 #define FE_PSE_FQFC_CFG_256Q    0xff908000
  75
  76 /* interrupt bits */
  77 #define FE_CNT_PPE_AF           BIT(31)
  78 #define FE_CNT_GDM_AF           BIT(29)
  79 #define FE_PSE_P2_FC            BIT(26)
  80 #define FE_PSE_BUF_DROP         BIT(24)
  81 #define FE_GDM_OTHER_DROP       BIT(23)
  82 #define FE_PSE_P1_FC            BIT(22)
  83 #define FE_PSE_P0_FC            BIT(21)
  84 #define FE_PSE_FQ_EMPTY         BIT(20)
  85 #define FE_GE1_STA_CHG          BIT(18)
  86 #define FE_TX_COHERENT          BIT(17)
  87 #define FE_RX_COHERENT          BIT(16)
  88 #define FE_TX_DONE_INT3         BIT(11)
  89 #define FE_TX_DONE_INT2         BIT(10)
  90 #define FE_TX_DONE_INT1         BIT(9)
  91 #define FE_TX_DONE_INT0         BIT(8)
  92 #define FE_RX_DONE_INT0         BIT(2)
  93 #define FE_TX_DLY_INT           BIT(1)
  94 #define FE_RX_DLY_INT           BIT(0)
  95
  96 #define FE_RX_DONE_INT          FE_RX_DONE_INT0
  97 #define FE_TX_DONE_INT          (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
  98                                  FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
  99
 100 #define RT5350_RX_DLY_INT       BIT(30)
 101 #define RT5350_TX_DLY_INT       BIT(28)
 102 #define RT5350_RX_DONE_INT1     BIT(17)
 103 #define RT5350_RX_DONE_INT0     BIT(16)
 104 #define RT5350_TX_DONE_INT3     BIT(3)
 105 #define RT5350_TX_DONE_INT2     BIT(2)
 106 #define RT5350_TX_DONE_INT1     BIT(1)
 107 #define RT5350_TX_DONE_INT0     BIT(0)
 108
 109 #define RT5350_RX_DONE_INT      (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
 110 #define RT5350_TX_DONE_INT      (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
 111                                  RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
 112
 113 /* registers */
 114 #define FE_FE_OFFSET            0x0000
 115 #define FE_GDMA_OFFSET          0x0020
 116 #define FE_PSE_OFFSET           0x0040
 117 #define FE_GDMA2_OFFSET         0x0060
 118 #define FE_CDMA_OFFSET          0x0080
 119 #define FE_DMA_VID0             0x00a8
 120 #define FE_PDMA_OFFSET          0x0100
 121 #define FE_PPE_OFFSET           0x0200
 122 #define FE_CMTABLE_OFFSET       0x0400
 123 #define FE_POLICYTABLE_OFFSET   0x1000
 124
 125 #define RT5350_PDMA_OFFSET      0x0800
 126 #define RT5350_SDM_OFFSET       0x0c00
 127
 128 #define FE_MDIO_ACCESS          (FE_FE_OFFSET + 0x00)
 129 #define FE_MDIO_CFG             (FE_FE_OFFSET + 0x04)
 130 #define FE_FE_GLO_CFG           (FE_FE_OFFSET + 0x08)
 131 #define FE_FE_RST_GL            (FE_FE_OFFSET + 0x0C)
 132 #define FE_FE_INT_STATUS        (FE_FE_OFFSET + 0x10)
 133 #define FE_FE_INT_ENABLE        (FE_FE_OFFSET + 0x14)
 134 #define FE_MDIO_CFG2            (FE_FE_OFFSET + 0x18)
 135 #define FE_FOC_TS_T             (FE_FE_OFFSET + 0x1C)
 136
 137 #define FE_GDMA1_FWD_CFG        (FE_GDMA_OFFSET + 0x00)
 138 #define FE_GDMA1_SCH_CFG        (FE_GDMA_OFFSET + 0x04)
 139 #define FE_GDMA1_SHPR_CFG       (FE_GDMA_OFFSET + 0x08)
 140 #define FE_GDMA1_MAC_ADRL       (FE_GDMA_OFFSET + 0x0C)
 141 #define FE_GDMA1_MAC_ADRH       (FE_GDMA_OFFSET + 0x10)
 142
 143 #define FE_GDMA2_FWD_CFG        (FE_GDMA2_OFFSET + 0x00)
 144 #define FE_GDMA2_SCH_CFG        (FE_GDMA2_OFFSET + 0x04)
 145 #define FE_GDMA2_SHPR_CFG       (FE_GDMA2_OFFSET + 0x08)
 146 #define FE_GDMA2_MAC_ADRL       (FE_GDMA2_OFFSET + 0x0C)
 147 #define FE_GDMA2_MAC_ADRH       (FE_GDMA2_OFFSET + 0x10)
 148
 149 #define FE_PSE_FQ_CFG           (FE_PSE_OFFSET + 0x00)
 150 #define FE_CDMA_FC_CFG          (FE_PSE_OFFSET + 0x04)
 151 #define FE_GDMA1_FC_CFG         (FE_PSE_OFFSET + 0x08)
 152 #define FE_GDMA2_FC_CFG         (FE_PSE_OFFSET + 0x0C)
 153
 154 #define FE_CDMA_CSG_CFG         (FE_CDMA_OFFSET + 0x00)
 155 #define FE_CDMA_SCH_CFG         (FE_CDMA_OFFSET + 0x04)
 156
 157 #ifdef CONFIG_SOC_MT7621
 158 #define MT7620A_GDMA_OFFSET             0x0500
 159 #else
 160 #define MT7620A_GDMA_OFFSET             0x0600
 161 #endif
 162 #define MT7620A_GDMA1_FWD_CFG           (MT7620A_GDMA_OFFSET + 0x00)
 163 #define MT7620A_FE_GDMA1_SCH_CFG        (MT7620A_GDMA_OFFSET + 0x04)
 164 #define MT7620A_FE_GDMA1_SHPR_CFG       (MT7620A_GDMA_OFFSET + 0x08)
 165 #define MT7620A_FE_GDMA1_MAC_ADRL       (MT7620A_GDMA_OFFSET + 0x0C)
 166 #define MT7620A_FE_GDMA1_MAC_ADRH       (MT7620A_GDMA_OFFSET + 0x10)
 167
 168 #define RT5350_TX_BASE_PTR0     (RT5350_PDMA_OFFSET + 0x00)
 169 #define RT5350_TX_MAX_CNT0      (RT5350_PDMA_OFFSET + 0x04)
 170 #define RT5350_TX_CTX_IDX0      (RT5350_PDMA_OFFSET + 0x08)
 171 #define RT5350_TX_DTX_IDX0      (RT5350_PDMA_OFFSET + 0x0C)
 172 #define RT5350_TX_BASE_PTR1     (RT5350_PDMA_OFFSET + 0x10)
 173 #define RT5350_TX_MAX_CNT1      (RT5350_PDMA_OFFSET + 0x14)
 174 #define RT5350_TX_CTX_IDX1      (RT5350_PDMA_OFFSET + 0x18)
 175 #define RT5350_TX_DTX_IDX1      (RT5350_PDMA_OFFSET + 0x1C)
 176 #define RT5350_TX_BASE_PTR2     (RT5350_PDMA_OFFSET + 0x20)
 177 #define RT5350_TX_MAX_CNT2      (RT5350_PDMA_OFFSET + 0x24)
 178 #define RT5350_TX_CTX_IDX2      (RT5350_PDMA_OFFSET + 0x28)
 179 #define RT5350_TX_DTX_IDX2      (RT5350_PDMA_OFFSET + 0x2C)
 180 #define RT5350_TX_BASE_PTR3     (RT5350_PDMA_OFFSET + 0x30)
 181 #define RT5350_TX_MAX_CNT3      (RT5350_PDMA_OFFSET + 0x34)
 182 #define RT5350_TX_CTX_IDX3      (RT5350_PDMA_OFFSET + 0x38)
 183 #define RT5350_TX_DTX_IDX3      (RT5350_PDMA_OFFSET + 0x3C)
 184 #define RT5350_RX_BASE_PTR0     (RT5350_PDMA_OFFSET + 0x100)
 185 #define RT5350_RX_MAX_CNT0      (RT5350_PDMA_OFFSET + 0x104)
 186 #define RT5350_RX_CALC_IDX0     (RT5350_PDMA_OFFSET + 0x108)
 187 #define RT5350_RX_DRX_IDX0      (RT5350_PDMA_OFFSET + 0x10C)
 188 #define RT5350_RX_BASE_PTR1     (RT5350_PDMA_OFFSET + 0x110)
 189 #define RT5350_RX_MAX_CNT1      (RT5350_PDMA_OFFSET + 0x114)
 190 #define RT5350_RX_CALC_IDX1     (RT5350_PDMA_OFFSET + 0x118)
 191 #define RT5350_RX_DRX_IDX1      (RT5350_PDMA_OFFSET + 0x11C)
 192 #define RT5350_PDMA_GLO_CFG     (RT5350_PDMA_OFFSET + 0x204)
 193 #define RT5350_PDMA_RST_CFG     (RT5350_PDMA_OFFSET + 0x208)
 194 #define RT5350_DLY_INT_CFG      (RT5350_PDMA_OFFSET + 0x20c)
 195 #define RT5350_FE_INT_STATUS    (RT5350_PDMA_OFFSET + 0x220)
 196 #define RT5350_FE_INT_ENABLE    (RT5350_PDMA_OFFSET + 0x228)
 197 #define RT5350_PDMA_SCH_CFG     (RT5350_PDMA_OFFSET + 0x280)
 198
 199 #define FE_PDMA_GLO_CFG         (FE_PDMA_OFFSET + 0x00)
 200 #define FE_PDMA_RST_CFG         (FE_PDMA_OFFSET + 0x04)
 201 #define FE_PDMA_SCH_CFG         (FE_PDMA_OFFSET + 0x08)
 202 #define FE_DLY_INT_CFG          (FE_PDMA_OFFSET + 0x0C)
 203 #define FE_TX_BASE_PTR0         (FE_PDMA_OFFSET + 0x10)
 204 #define FE_TX_MAX_CNT0          (FE_PDMA_OFFSET + 0x14)
 205 #define FE_TX_CTX_IDX0          (FE_PDMA_OFFSET + 0x18)
 206 #define FE_TX_DTX_IDX0          (FE_PDMA_OFFSET + 0x1C)
 207 #define FE_TX_BASE_PTR1         (FE_PDMA_OFFSET + 0x20)
 208 #define FE_TX_MAX_CNT1          (FE_PDMA_OFFSET + 0x24)
 209 #define FE_TX_CTX_IDX1          (FE_PDMA_OFFSET + 0x28)
 210 #define FE_TX_DTX_IDX1          (FE_PDMA_OFFSET + 0x2C)
 211 #define FE_RX_BASE_PTR0         (FE_PDMA_OFFSET + 0x30)
 212 #define FE_RX_MAX_CNT0          (FE_PDMA_OFFSET + 0x34)
 213 #define FE_RX_CALC_IDX0         (FE_PDMA_OFFSET + 0x38)
 214 #define FE_RX_DRX_IDX0          (FE_PDMA_OFFSET + 0x3C)
 215 #define FE_TX_BASE_PTR2         (FE_PDMA_OFFSET + 0x40)
 216 #define FE_TX_MAX_CNT2          (FE_PDMA_OFFSET + 0x44)
 217 #define FE_TX_CTX_IDX2          (FE_PDMA_OFFSET + 0x48)
 218 #define FE_TX_DTX_IDX2          (FE_PDMA_OFFSET + 0x4C)
 219 #define FE_TX_BASE_PTR3         (FE_PDMA_OFFSET + 0x50)
 220 #define FE_TX_MAX_CNT3          (FE_PDMA_OFFSET + 0x54)
 221 #define FE_TX_CTX_IDX3          (FE_PDMA_OFFSET + 0x58)
 222 #define FE_TX_DTX_IDX3          (FE_PDMA_OFFSET + 0x5C)
 223 #define FE_RX_BASE_PTR1         (FE_PDMA_OFFSET + 0x60)
 224 #define FE_RX_MAX_CNT1          (FE_PDMA_OFFSET + 0x64)
 225 #define FE_RX_CALC_IDX1         (FE_PDMA_OFFSET + 0x68)
 226 #define FE_RX_DRX_IDX1          (FE_PDMA_OFFSET + 0x6C)
 227
 228 #define RT5350_SDM_CFG          (RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
 229 #define RT5350_SDM_RRING        (RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
 230 #define RT5350_SDM_TRING        (RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
 231 #define RT5350_SDM_MAC_ADRL     (RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
 232 #define RT5350_SDM_MAC_ADRH     (RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
 233 #define RT5350_SDM_TPCNT        (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
 234 #define RT5350_SDM_TBCNT        (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
 235 #define RT5350_SDM_RPCNT        (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
 236 #define RT5350_SDM_RBCNT        (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
 237 #define RT5350_SDM_CS_ERR       (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
 238
 239 #define RT5350_SDM_ICS_EN       BIT(16)
 240 #define RT5350_SDM_TCS_EN       BIT(17)
 241 #define RT5350_SDM_UCS_EN       BIT(18)
 242
 243
 244 /* MDIO_CFG register bits */
 245 #define FE_MDIO_CFG_AUTO_POLL_EN        BIT(29)
 246 #define FE_MDIO_CFG_GP1_BP_EN           BIT(16)
 247 #define FE_MDIO_CFG_GP1_FRC_EN          BIT(15)
 248 #define FE_MDIO_CFG_GP1_SPEED_10        (0 << 13)
 249 #define FE_MDIO_CFG_GP1_SPEED_100       (1 << 13)
 250 #define FE_MDIO_CFG_GP1_SPEED_1000      (2 << 13)
 251 #define FE_MDIO_CFG_GP1_DUPLEX          BIT(12)
 252 #define FE_MDIO_CFG_GP1_FC_TX           BIT(11)
 253 #define FE_MDIO_CFG_GP1_FC_RX           BIT(10)
 254 #define FE_MDIO_CFG_GP1_LNK_DWN         BIT(9)
 255 #define FE_MDIO_CFG_GP1_AN_FAIL         BIT(8)
 256 #define FE_MDIO_CFG_MDC_CLK_DIV_1       (0 << 6)
 257 #define FE_MDIO_CFG_MDC_CLK_DIV_2       (1 << 6)
 258 #define FE_MDIO_CFG_MDC_CLK_DIV_4       (2 << 6)
 259 #define FE_MDIO_CFG_MDC_CLK_DIV_8       (3 << 6)
 260 #define FE_MDIO_CFG_TURBO_MII_FREQ      BIT(5)
 261 #define FE_MDIO_CFG_TURBO_MII_MODE      BIT(4)
 262 #define FE_MDIO_CFG_RX_CLK_SKEW_0       (0 << 2)
 263 #define FE_MDIO_CFG_RX_CLK_SKEW_200     (1 << 2)
 264 #define FE_MDIO_CFG_RX_CLK_SKEW_400     (2 << 2)
 265 #define FE_MDIO_CFG_RX_CLK_SKEW_INV     (3 << 2)
 266 #define FE_MDIO_CFG_TX_CLK_SKEW_0       0
 267 #define FE_MDIO_CFG_TX_CLK_SKEW_200     1
 268 #define FE_MDIO_CFG_TX_CLK_SKEW_400     2
 269 #define FE_MDIO_CFG_TX_CLK_SKEW_INV     3
 270
 271 /* uni-cast port */
 272 #define FE_GDM1_JMB_LEN_MASK    0xf
 273 #define FE_GDM1_JMB_LEN_SHIFT   28
 274 #define FE_GDM1_ICS_EN          BIT(22)
 275 #define FE_GDM1_TCS_EN          BIT(21)
 276 #define FE_GDM1_UCS_EN          BIT(20)
 277 #define FE_GDM1_JMB_EN          BIT(19)
 278 #define FE_GDM1_STRPCRC         BIT(16)
 279 #define FE_GDM1_UFRC_P_CPU      (0 << 12)
 280 #define FE_GDM1_UFRC_P_GDMA1    (1 << 12)
 281 #define FE_GDM1_UFRC_P_PPE      (6 << 12)
 282
 283 /* checksums */
 284 #define FE_ICS_GEN_EN           BIT(2)
 285 #define FE_UCS_GEN_EN           BIT(1)
 286 #define FE_TCS_GEN_EN           BIT(0)
 287
 288 /* dma ring */
 289 #define FE_PST_DRX_IDX0         BIT(16)
 290 #define FE_PST_DTX_IDX3         BIT(3)
 291 #define FE_PST_DTX_IDX2         BIT(2)
 292 #define FE_PST_DTX_IDX1         BIT(1)
 293 #define FE_PST_DTX_IDX0         BIT(0)
 294
 295 #define FE_RX_2B_OFFSET         BIT(31)
 296 #define FE_TX_WB_DDONE          BIT(6)
 297 #define FE_RX_DMA_BUSY          BIT(3)
 298 #define FE_TX_DMA_BUSY          BIT(1)
 299 #define FE_RX_DMA_EN            BIT(2)
 300 #define FE_TX_DMA_EN            BIT(0)
 301
 302 #define FE_PDMA_SIZE_4DWORDS    (0 << 4)
 303 #define FE_PDMA_SIZE_8DWORDS    (1 << 4)
 304 #define FE_PDMA_SIZE_16DWORDS   (2 << 4)
 305
 306 #define FE_US_CYC_CNT_MASK      0xff
 307 #define FE_US_CYC_CNT_SHIFT     0x8
 308 #define FE_US_CYC_CNT_DIVISOR   1000000
 309
 310 /* rxd2 */
 311 #define RX_DMA_DONE             BIT(31)
 312 #define RX_DMA_LSO              BIT(30)
 313 #define RX_DMA_PLEN0(_x)        (((_x) & 0x3fff) << 16)
 314 #define RX_DMA_GET_PLEN0(_x)    (((_x) >> 16) & 0x3fff)
 315 #define RX_DMA_TAG              BIT(15)
 316 /* rxd3 */
 317 #define RX_DMA_TPID(_x)         (((_x) >> 16) & 0xffff)
 318 #define RX_DMA_VID(_x)          ((_x) & 0xffff)
 319 /* rxd4 */
 320 #define RX_DMA_L4VALID          BIT(30)
 321
 322 struct fe_rx_dma {
 323         unsigned int rxd1;
 324         unsigned int rxd2;
 325         unsigned int rxd3;
 326         unsigned int rxd4;
 327 } __packed __aligned(4);
 328
 329 #define TX_DMA_BUF_LEN          0x3fff
 330 #define TX_DMA_PLEN0_MASK       (TX_DMA_BUF_LEN << 16)
 331 #define TX_DMA_PLEN0(_x)        (((_x) & TX_DMA_BUF_LEN) << 16)
 332 #define TX_DMA_PLEN1(_x)        ((_x) & TX_DMA_BUF_LEN)
 333 #define TX_DMA_GET_PLEN0(_x)    (((_x) >> 16 ) & TX_DMA_BUF_LEN)
 334 #define TX_DMA_GET_PLEN1(_x)    ((_x) & TX_DMA_BUF_LEN)
 335 #define TX_DMA_LS1              BIT(14)
 336 #define TX_DMA_LS0              BIT(30)
 337 #define TX_DMA_DONE             BIT(31)
 338
 339 #define TX_DMA_INS_VLAN_MT7621  BIT(16)
 340 #define TX_DMA_INS_VLAN         BIT(7)
 341 #define TX_DMA_INS_PPPOE        BIT(12)
 342 #define TX_DMA_QN(_x)           ((_x) << 16)
 343 #define TX_DMA_PN(_x)           ((_x) << 24)
 344 #define TX_DMA_QN_MASK          TX_DMA_QN(0x7)
 345 #define TX_DMA_PN_MASK          TX_DMA_PN(0x7)
 346 #define TX_DMA_UDF              BIT(20)
 347 #define TX_DMA_CHKSUM           (0x7 << 29)
 348 #define TX_DMA_TSO              BIT(28)
 349
 350 /* frame engine counters */
 351 #define FE_PPE_AC_BCNT0         (FE_CMTABLE_OFFSET + 0x00)
 352 #define FE_GDMA1_TX_GBCNT       (FE_CMTABLE_OFFSET + 0x300)
 353 #define FE_GDMA2_TX_GBCNT       (FE_GDMA1_TX_GBCNT + 0x40)
 354
 355 /* phy device flags */
 356 #define FE_PHY_FLAG_PORT        BIT(0)
 357 #define FE_PHY_FLAG_ATTACH      BIT(1)
 358
 359 struct fe_tx_dma {
 360         unsigned int txd1;
 361         unsigned int txd2;
 362         unsigned int txd3;
 363         unsigned int txd4;
 364 } __packed __aligned(4);
 365
 366 struct fe_priv;
 367
 368 struct fe_phy {
 369         struct phy_device       *phy[8];
 370         struct device_node      *phy_node[8];
 371         const __be32            *phy_fixed[8];
 372         int                     duplex[8];
 373         int                     speed[8];
 374         int                     tx_fc[8];
 375         int                     rx_fc[8];
 376         spinlock_t              lock;
 377
 378         int (*connect)(struct fe_priv *priv);
 379         void (*disconnect)(struct fe_priv *priv);
 380         void (*start)(struct fe_priv *priv);
 381         void (*stop)(struct fe_priv *priv);
 382 };
 383
 384 struct fe_soc_data
 385 {
 386         const u16 *reg_table;
 387
 388         void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
 389         void (*reset_fe)(void);
 390         void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
 391         int (*fwd_config)(struct fe_priv *priv);
 392         void (*tx_dma)(struct fe_tx_dma *txd);
 393         int (*switch_init)(struct fe_priv *priv);
 394         int (*switch_config)(struct fe_priv *priv);
 395         void (*port_init)(struct fe_priv *priv, struct device_node *port);
 396         int (*has_carrier)(struct fe_priv *priv);
 397         int (*mdio_init)(struct fe_priv *priv);
 398         void (*mdio_cleanup)(struct fe_priv *priv);
 399         int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
 400         int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
 401         void (*mdio_adjust_link)(struct fe_priv *priv, int port);
 402
 403         void *swpriv;
 404         u32 pdma_glo_cfg;
 405         u32 rx_int;
 406         u32 tx_int;
 407         u32 status_int;
 408         u32 checksum_bit;
 409 };
 410
 411 #define FE_FLAG_PADDING_64B             BIT(0)
 412 #define FE_FLAG_PADDING_BUG             BIT(1)
 413 #define FE_FLAG_JUMBO_FRAME             BIT(2)
 414 #define FE_FLAG_RX_2B_OFFSET            BIT(3)
 415 #define FE_FLAG_RX_SG_DMA               BIT(4)
 416 #define FE_FLAG_RX_VLAN_CTAG            BIT(5)
 417 #define FE_FLAG_NAPI_WEIGHT             BIT(6)
 418
 419 #define FE_STAT_REG_DECLARE             \
 420         _FE(tx_bytes)                   \
 421         _FE(tx_packets)                 \
 422         _FE(tx_skip)                    \
 423         _FE(tx_collisions)              \
 424         _FE(rx_bytes)                   \
 425         _FE(rx_packets)                 \
 426         _FE(rx_overflow)                \
 427         _FE(rx_fcs_errors)              \
 428         _FE(rx_short_errors)            \
 429         _FE(rx_long_errors)             \
 430         _FE(rx_checksum_errors)         \
 431         _FE(rx_flow_control_packets)
 432
 433 struct fe_hw_stats
 434 {
 435         spinlock_t stats_lock;
 436         struct u64_stats_sync syncp;
 437 #define _FE(x) u64 x;
 438 FE_STAT_REG_DECLARE
 439 #undef _FE
 440 };
 441
 442 enum fe_tx_flags {
 443         FE_TX_FLAGS_SINGLE0     = 0x01,
 444         FE_TX_FLAGS_PAGE0       = 0x02,
 445         FE_TX_FLAGS_PAGE1       = 0x04,
 446 };
 447
 448 struct fe_tx_buf
 449 {
 450         struct sk_buff *skb;
 451         u32 flags;
 452         DEFINE_DMA_UNMAP_ADDR(dma_addr0);
 453         DEFINE_DMA_UNMAP_LEN(dma_len0);
 454         DEFINE_DMA_UNMAP_ADDR(dma_addr1);
 455         DEFINE_DMA_UNMAP_LEN(dma_len1);
 456 };
 457
 458 struct fe_tx_ring
 459 {
 460         struct fe_tx_dma *tx_dma;
 461         struct fe_tx_buf *tx_buf;
 462         dma_addr_t tx_phys;
 463         u16 tx_ring_size;
 464         u16 tx_free_idx;
 465         u16 tx_next_idx;
 466         u16 tx_thresh;
 467 };
 468
 469 struct fe_rx_ring
 470 {
 471         struct fe_rx_dma *rx_dma;
 472         u8 **rx_data;
 473         dma_addr_t rx_phys;
 474         u16 rx_ring_size;
 475         u16 frag_size;
 476         u16 rx_buf_size;
 477         u16 rx_calc_idx;
 478 };
 479
 480 struct fe_priv
 481 {
 482         spinlock_t                      page_lock;
 483
 484         struct fe_soc_data              *soc;
 485         struct net_device               *netdev;
 486         u32                             msg_enable;
 487         u32                             flags;
 488
 489         struct device                   *device;
 490         unsigned long                   sysclk;
 491
 492         struct fe_rx_ring               rx_ring;
 493         struct napi_struct              rx_napi;
 494
 495         struct fe_tx_ring               tx_ring;
 496
 497         struct fe_phy                   *phy;
 498         struct mii_bus                  *mii_bus;
 499         struct phy_device               *phy_dev;
 500         u32                             phy_flags;
 501
 502         int                             link[8];
 503
 504         struct fe_hw_stats              *hw_stats;
 505         unsigned long                   vlan_map;
 506         struct work_struct              pending_work;
 507         DECLARE_BITMAP(pending_flags, FE_FLAG_MAX);
 508 };
 509
 510 extern const struct of_device_id of_fe_match[];
 511
 512 void fe_w32(u32 val, unsigned reg);
 513 u32 fe_r32(unsigned reg);
 514
 515 int fe_set_clock_cycle(struct fe_priv *priv);
 516 void fe_csum_config(struct fe_priv *priv);
 517 void fe_stats_update(struct fe_priv *priv);
 518 void fe_fwd_config(struct fe_priv *priv);
 519 void fe_reg_w32(u32 val, enum fe_reg reg);
 520 u32 fe_reg_r32(enum fe_reg reg);
 521
 522 void fe_reset(u32 reset_bits);
 523
 524 static inline void *priv_netdev(struct fe_priv *priv)
 525 {
 526         return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
 527 }
 528
 529 #endif /* FE_ETH_H */