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[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.h
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * based on Ralink SDK3.3
16 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
17 */
18
19 #ifndef FE_ETH_H
20 #define FE_ETH_H
21
22 #include <linux/mii.h>
23 #include <linux/interrupt.h>
24 #include <linux/netdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/phy.h>
27 #include <linux/ethtool.h>
28
29 enum fe_reg {
30 FE_REG_PDMA_GLO_CFG = 0,
31 FE_REG_PDMA_RST_CFG,
32 FE_REG_DLY_INT_CFG,
33 FE_REG_TX_BASE_PTR0,
34 FE_REG_TX_MAX_CNT0,
35 FE_REG_TX_CTX_IDX0,
36 FE_REG_RX_BASE_PTR0,
37 FE_REG_RX_MAX_CNT0,
38 FE_REG_RX_CALC_IDX0,
39 FE_REG_FE_INT_ENABLE,
40 FE_REG_FE_INT_STATUS,
41 FE_REG_FE_DMA_VID_BASE,
42 FE_REG_FE_COUNTER_BASE,
43 FE_REG_FE_RST_GL,
44 FE_REG_COUNT
45 };
46
47 #define FE_DRV_VERSION "0.1.0"
48
49 /* power of 2 to let NEXT_TX_DESP_IDX work */
50 #define NUM_DMA_DESC (1 << 7)
51 #define MAX_DMA_DESC 0xfff
52
53 #define FE_DELAY_EN_INT 0x80
54 #define FE_DELAY_MAX_INT 0x04
55 #define FE_DELAY_MAX_TOUT 0x04
56 #define FE_DELAY_TIME 20
57 #define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
58 #define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
59 #define FE_PSE_FQFC_CFG_INIT 0x80504000
60 #define FE_PSE_FQFC_CFG_256Q 0xff908000
61
62 /* interrupt bits */
63 #define FE_CNT_PPE_AF BIT(31)
64 #define FE_CNT_GDM_AF BIT(29)
65 #define FE_PSE_P2_FC BIT(26)
66 #define FE_PSE_BUF_DROP BIT(24)
67 #define FE_GDM_OTHER_DROP BIT(23)
68 #define FE_PSE_P1_FC BIT(22)
69 #define FE_PSE_P0_FC BIT(21)
70 #define FE_PSE_FQ_EMPTY BIT(20)
71 #define FE_GE1_STA_CHG BIT(18)
72 #define FE_TX_COHERENT BIT(17)
73 #define FE_RX_COHERENT BIT(16)
74 #define FE_TX_DONE_INT3 BIT(11)
75 #define FE_TX_DONE_INT2 BIT(10)
76 #define FE_TX_DONE_INT1 BIT(9)
77 #define FE_TX_DONE_INT0 BIT(8)
78 #define FE_RX_DONE_INT0 BIT(2)
79 #define FE_TX_DLY_INT BIT(1)
80 #define FE_RX_DLY_INT BIT(0)
81
82 #define RT5350_RX_DLY_INT BIT(30)
83 #define RT5350_TX_DLY_INT BIT(28)
84
85 /* registers */
86 #define FE_FE_OFFSET 0x0000
87 #define FE_GDMA_OFFSET 0x0020
88 #define FE_PSE_OFFSET 0x0040
89 #define FE_GDMA2_OFFSET 0x0060
90 #define FE_CDMA_OFFSET 0x0080
91 #define FE_DMA_VID0 0x00a8
92 #define FE_PDMA_OFFSET 0x0100
93 #define FE_PPE_OFFSET 0x0200
94 #define FE_CMTABLE_OFFSET 0x0400
95 #define FE_POLICYTABLE_OFFSET 0x1000
96
97 #define RT5350_PDMA_OFFSET 0x0800
98 #define RT5350_SDM_OFFSET 0x0c00
99
100 #define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
101 #define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
102 #define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
103 #define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
104 #define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
105 #define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
106 #define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
107 #define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
108
109 #define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
110 #define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
111 #define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
112 #define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
113 #define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
114
115 #define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
116 #define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
117 #define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
118 #define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
119 #define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
120
121 #define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
122 #define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
123 #define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
124 #define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
125
126 #define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
127 #define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
128
129 #ifdef CONFIG_SOC_MT7621
130 #define MT7620A_GDMA_OFFSET 0x0500
131 #else
132 #define MT7620A_GDMA_OFFSET 0x0600
133 #endif
134 #define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
135 #define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
136 #define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
137 #define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
138 #define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
139
140 #define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
141 #define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
142 #define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
143 #define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
144 #define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
145 #define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
146 #define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
147 #define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
148 #define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
149 #define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
150 #define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
151 #define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
152 #define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
153 #define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
154 #define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
155 #define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
156 #define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
157 #define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
158 #define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
159 #define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
160 #define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
161 #define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
162 #define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
163 #define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
164 #define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
165 #define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
166 #define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
167 #define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
168 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
169 #define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
170
171 #define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
172 #define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
173 #define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
174 #define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
175 #define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
176 #define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
177 #define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
178 #define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
179 #define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
180 #define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
181 #define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
182 #define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
183 #define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
184 #define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
185 #define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
186 #define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
187 #define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
188 #define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
189 #define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
190 #define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
191 #define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
192 #define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
193 #define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
194 #define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
195 #define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
196 #define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
197 #define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
198 #define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
199
200 #define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
201 #define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
202 #define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
203 #define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
204 #define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
205 #define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
206 #define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
207 #define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
208 #define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
209 #define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
210
211 #define RT5350_SDM_ICS_EN BIT(16)
212 #define RT5350_SDM_TCS_EN BIT(17)
213 #define RT5350_SDM_UCS_EN BIT(18)
214
215
216 /* MDIO_CFG register bits */
217 #define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
218 #define FE_MDIO_CFG_GP1_BP_EN BIT(16)
219 #define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
220 #define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
221 #define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
222 #define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
223 #define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
224 #define FE_MDIO_CFG_GP1_FC_TX BIT(11)
225 #define FE_MDIO_CFG_GP1_FC_RX BIT(10)
226 #define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
227 #define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
228 #define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
229 #define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
230 #define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
231 #define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
232 #define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
233 #define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
234 #define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
235 #define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
236 #define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
237 #define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
238 #define FE_MDIO_CFG_TX_CLK_SKEW_0 0
239 #define FE_MDIO_CFG_TX_CLK_SKEW_200 1
240 #define FE_MDIO_CFG_TX_CLK_SKEW_400 2
241 #define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
242
243 /* uni-cast port */
244 #define FE_GDM1_JMB_LEN_MASK 0xf
245 #define FE_GDM1_JMB_LEN_SHIFT 28
246 #define FE_GDM1_ICS_EN BIT(22)
247 #define FE_GDM1_TCS_EN BIT(21)
248 #define FE_GDM1_UCS_EN BIT(20)
249 #define FE_GDM1_JMB_EN BIT(19)
250 #define FE_GDM1_STRPCRC BIT(16)
251 #define FE_GDM1_UFRC_P_CPU (0 << 12)
252 #define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
253 #define FE_GDM1_UFRC_P_PPE (6 << 12)
254
255 /* checksums */
256 #define FE_ICS_GEN_EN BIT(2)
257 #define FE_UCS_GEN_EN BIT(1)
258 #define FE_TCS_GEN_EN BIT(0)
259
260 /* dma ring */
261 #define FE_PST_DRX_IDX0 BIT(16)
262 #define FE_PST_DTX_IDX3 BIT(3)
263 #define FE_PST_DTX_IDX2 BIT(2)
264 #define FE_PST_DTX_IDX1 BIT(1)
265 #define FE_PST_DTX_IDX0 BIT(0)
266
267 #define FE_TX_WB_DDONE BIT(6)
268 #define FE_RX_DMA_BUSY BIT(3)
269 #define FE_TX_DMA_BUSY BIT(1)
270 #define FE_RX_DMA_EN BIT(2)
271 #define FE_TX_DMA_EN BIT(0)
272
273 #define FE_PDMA_SIZE_4DWORDS (0 << 4)
274 #define FE_PDMA_SIZE_8DWORDS (1 << 4)
275 #define FE_PDMA_SIZE_16DWORDS (2 << 4)
276
277 #define FE_US_CYC_CNT_MASK 0xff
278 #define FE_US_CYC_CNT_SHIFT 0x8
279 #define FE_US_CYC_CNT_DIVISOR 1000000
280
281 #define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
282 #define RX_DMA_LSO BIT(30)
283 #define RX_DMA_DONE BIT(31)
284 #define RX_DMA_L4VALID BIT(30)
285
286 struct fe_rx_dma {
287 unsigned int rxd1;
288 unsigned int rxd2;
289 unsigned int rxd3;
290 unsigned int rxd4;
291 } __packed __aligned(4);
292
293 #define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
294 #define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
295 #define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
296 #define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & 0x3fff)
297 #define TX_DMA_GET_PLEN1(_x) ((_x) & 0x3fff)
298 #define TX_DMA_LS1 BIT(14)
299 #define TX_DMA_LS0 BIT(30)
300 #define TX_DMA_DONE BIT(31)
301
302 #define TX_DMA_INS_VLAN_MT7621 BIT(16)
303 #define TX_DMA_INS_VLAN BIT(7)
304 #define TX_DMA_INS_PPPOE BIT(12)
305 #define TX_DMA_QN(_x) ((_x) << 16)
306 #define TX_DMA_PN(_x) ((_x) << 24)
307 #define TX_DMA_QN_MASK TX_DMA_QN(0x7)
308 #define TX_DMA_PN_MASK TX_DMA_PN(0x7)
309 #define TX_DMA_UDF BIT(20)
310 #define TX_DMA_CHKSUM (0x7 << 29)
311 #define TX_DMA_TSO BIT(28)
312
313 /* frame engine counters */
314 #define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
315 #define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
316 #define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
317
318 /* phy device flags */
319 #define FE_PHY_FLAG_PORT BIT(0)
320 #define FE_PHY_FLAG_ATTACH BIT(1)
321
322 struct fe_tx_dma {
323 unsigned int txd1;
324 unsigned int txd2;
325 unsigned int txd3;
326 unsigned int txd4;
327 } __packed __aligned(4);
328
329 struct fe_priv;
330
331 struct fe_phy {
332 struct phy_device *phy[8];
333 struct device_node *phy_node[8];
334 const __be32 *phy_fixed[8];
335 int duplex[8];
336 int speed[8];
337 int tx_fc[8];
338 int rx_fc[8];
339 spinlock_t lock;
340
341 int (*connect)(struct fe_priv *priv);
342 void (*disconnect)(struct fe_priv *priv);
343 void (*start)(struct fe_priv *priv);
344 void (*stop)(struct fe_priv *priv);
345 };
346
347 struct fe_soc_data
348 {
349 unsigned char mac[6];
350 const u32 *reg_table;
351
352 void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
353 void (*reset_fe)(void);
354 void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
355 int (*fwd_config)(struct fe_priv *priv);
356 void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
357 void (*rx_dma)(struct fe_priv *priv, int idx, int len);
358 int (*switch_init)(struct fe_priv *priv);
359 int (*switch_config)(struct fe_priv *priv);
360 void (*port_init)(struct fe_priv *priv, struct device_node *port);
361 int (*has_carrier)(struct fe_priv *priv);
362 int (*mdio_init)(struct fe_priv *priv);
363 void (*mdio_cleanup)(struct fe_priv *priv);
364 int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
365 int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
366 void (*mdio_adjust_link)(struct fe_priv *priv, int port);
367
368 void *swpriv;
369 u32 pdma_glo_cfg;
370 u32 rx_dly_int;
371 u32 tx_dly_int;
372 u32 checksum_bit;
373 u32 tx_udf_bit;
374 };
375
376 #define FE_FLAG_PADDING_64B BIT(0)
377 #define FE_FLAG_PADDING_BUG BIT(1)
378 #define FE_FLAG_JUMBO_FRAME BIT(2)
379
380 #define FE_STAT_REG_DECLARE \
381 _FE(tx_bytes) \
382 _FE(tx_packets) \
383 _FE(tx_skip) \
384 _FE(tx_collisions) \
385 _FE(rx_bytes) \
386 _FE(rx_packets) \
387 _FE(rx_overflow) \
388 _FE(rx_fcs_errors) \
389 _FE(rx_short_errors) \
390 _FE(rx_long_errors) \
391 _FE(rx_checksum_errors) \
392 _FE(rx_flow_control_packets)
393
394 struct fe_hw_stats
395 {
396 spinlock_t stats_lock;
397 struct u64_stats_sync syncp;
398 #define _FE(x) u64 x;
399 FE_STAT_REG_DECLARE
400 #undef _FE
401 };
402
403 struct fe_priv
404 {
405 spinlock_t page_lock;
406
407 struct fe_soc_data *soc;
408 struct net_device *netdev;
409 u32 msg_enable;
410 u32 flags;
411
412 struct device *device;
413 unsigned long sysclk;
414
415 u16 frag_size;
416 u16 rx_buf_size;
417 struct fe_rx_dma *rx_dma;
418 u8 **rx_data;
419 dma_addr_t rx_phys;
420 struct napi_struct rx_napi;
421
422 struct fe_tx_dma *tx_dma;
423 struct sk_buff **tx_skb;
424 dma_addr_t tx_phys;
425 unsigned int tx_free_idx;
426
427 struct fe_phy *phy;
428 struct mii_bus *mii_bus;
429 struct phy_device *phy_dev;
430 u32 phy_flags;
431
432 int link[8];
433
434 struct fe_hw_stats *hw_stats;
435 unsigned long vlan_map;
436 };
437
438 extern const struct of_device_id of_fe_match[];
439
440 void fe_w32(u32 val, unsigned reg);
441 u32 fe_r32(unsigned reg);
442
443 int fe_set_clock_cycle(struct fe_priv *priv);
444 void fe_csum_config(struct fe_priv *priv);
445 void fe_stats_update(struct fe_priv *priv);
446 void fe_fwd_config(struct fe_priv *priv);
447 void fe_reg_w32(u32 val, enum fe_reg reg);
448 u32 fe_reg_r32(enum fe_reg reg);
449
450 static inline void *priv_netdev(struct fe_priv *priv)
451 {
452 return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
453 }
454
455 #endif /* FE_ETH_H */
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