60666e7886538f548dae896a9ea7db73ab988be9
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / soc_mt7620.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21
22 #include <asm/mach-ralink/ralink_regs.h>
23
24 #include <mt7620.h>
25 #include "ralink_soc_eth.h"
26 #include "gsw_mt7620a.h"
27
28 #define MT7620A_CDMA_CSG_CFG 0x400
29 #define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
30 #define MT7621_DMA_VID 0xa8
31 #define MT7620A_DMA_2B_OFFSET BIT(31)
32 #define MT7620A_RESET_FE BIT(21)
33 #define MT7621_RESET_FE BIT(6)
34 #define MT7620A_RESET_ESW BIT(23)
35 #define MT7620_L4_VALID BIT(23)
36 #define MT7621_L4_VALID BIT(24)
37
38 #define MT7620_TX_DMA_UDF BIT(15)
39 #define MT7621_TX_DMA_UDF BIT(19)
40 #define TX_DMA_FP_BMAP ((0xff) << 19)
41
42 #define SYSC_REG_RESET_CTRL 0x34
43
44 #define CDMA_ICS_EN BIT(2)
45 #define CDMA_UCS_EN BIT(1)
46 #define CDMA_TCS_EN BIT(0)
47
48 #define GDMA_ICS_EN BIT(22)
49 #define GDMA_TCS_EN BIT(21)
50 #define GDMA_UCS_EN BIT(20)
51
52 /* frame engine counters */
53 #define MT7620_REG_MIB_OFFSET 0x1000
54 #define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
55 #define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
56 #define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
57
58 #define MT7621_REG_MIB_OFFSET 0x2000
59 #define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
60 #define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
61 #define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
62
63 #define GSW_REG_GDMA1_MAC_ADRL 0x508
64 #define GSW_REG_GDMA1_MAC_ADRH 0x50C
65
66 #define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
67
68 static const u32 mt7620_reg_table[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
78 [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
79 [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
80 [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
81 [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
82 [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
83 };
84
85 static const u32 mt7621_reg_table[FE_REG_COUNT] = {
86 [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
87 [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
88 [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
89 [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
90 [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
91 [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
92 [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
93 [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
94 [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
95 [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
96 [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
97 [FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
98 [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
99 [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
100 };
101
102 static void mt7620_fe_reset(void)
103 {
104 u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
105
106 rt_sysc_w32(val | MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
107 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
108 }
109
110 static void mt7621_fe_reset(void)
111 {
112 u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
113
114 rt_sysc_w32(val | MT7621_RESET_FE, SYSC_REG_RESET_CTRL);
115 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
116 }
117
118 static void mt7620_rxcsum_config(bool enable)
119 {
120 if (enable)
121 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
122 GDMA_TCS_EN | GDMA_UCS_EN),
123 MT7620A_GDMA1_FWD_CFG);
124 else
125 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
126 GDMA_TCS_EN | GDMA_UCS_EN),
127 MT7620A_GDMA1_FWD_CFG);
128 }
129
130 static void mt7620_txcsum_config(bool enable)
131 {
132 if (enable)
133 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
134 CDMA_UCS_EN | CDMA_TCS_EN),
135 MT7620A_CDMA_CSG_CFG);
136 else
137 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
138 CDMA_UCS_EN | CDMA_TCS_EN),
139 MT7620A_CDMA_CSG_CFG);
140 }
141
142 static int mt7620_fwd_config(struct fe_priv *priv)
143 {
144 struct net_device *dev = priv_netdev(priv);
145
146 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
147
148 mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
149 mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
150
151 return 0;
152 }
153
154 static int mt7621_fwd_config(struct fe_priv *priv)
155 {
156 struct net_device *dev = priv_netdev(priv);
157
158 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
159
160 mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
161 mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
162
163 return 0;
164 }
165
166 static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
167 {
168 priv->tx_dma[idx].txd4 = 0;
169 }
170
171 static void mt7621_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
172 {
173 priv->tx_dma[idx].txd4 = BIT(25);
174 }
175
176 static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
177 {
178 priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
179 }
180
181 static void mt7620_init_data(struct fe_soc_data *data,
182 struct net_device *netdev)
183 {
184 struct fe_priv *priv = netdev_priv(netdev);
185
186 priv->flags = FE_FLAG_PADDING_64B;
187 netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
188 NETIF_F_HW_VLAN_CTAG_TX;
189
190 if (mt7620_get_eco() >= 5 || IS_ENABLED(CONFIG_SOC_MT7621))
191 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
192 NETIF_F_IPV6_CSUM;
193 }
194
195 static void mt7621_init_data(struct fe_soc_data *data,
196 struct net_device *netdev)
197 {
198 struct fe_priv *priv = netdev_priv(netdev);
199
200 priv->flags = FE_FLAG_PADDING_64B;
201 netdev->hw_features = NETIF_F_HW_VLAN_CTAG_TX;
202 }
203
204 static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
205 {
206 unsigned long flags;
207
208 spin_lock_irqsave(&priv->page_lock, flags);
209 fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
210 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
211 GSW_REG_GDMA1_MAC_ADRL);
212 spin_unlock_irqrestore(&priv->page_lock, flags);
213 }
214
215 static struct fe_soc_data mt7620_data = {
216 .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
217 .init_data = mt7620_init_data,
218 .reset_fe = mt7620_fe_reset,
219 .set_mac = mt7620_set_mac,
220 .fwd_config = mt7620_fwd_config,
221 .tx_dma = mt7620_tx_dma,
222 .rx_dma = mt7620_rx_dma,
223 .switch_init = mt7620_gsw_probe,
224 .switch_config = mt7620_gsw_config,
225 .port_init = mt7620_port_init,
226 .reg_table = mt7620_reg_table,
227 .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
228 .rx_dly_int = RT5350_RX_DLY_INT,
229 .tx_dly_int = RT5350_TX_DLY_INT,
230 .checksum_bit = MT7620_L4_VALID,
231 .tx_udf_bit = MT7620_TX_DMA_UDF,
232 .has_carrier = mt7620a_has_carrier,
233 .mdio_read = mt7620_mdio_read,
234 .mdio_write = mt7620_mdio_write,
235 .mdio_adjust_link = mt7620_mdio_link_adjust,
236 };
237
238 static struct fe_soc_data mt7621_data = {
239 .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
240 .init_data = mt7621_init_data,
241 .reset_fe = mt7621_fe_reset,
242 .set_mac = mt7621_set_mac,
243 .fwd_config = mt7621_fwd_config,
244 .tx_dma = mt7621_tx_dma,
245 .rx_dma = mt7620_rx_dma,
246 .switch_init = mt7620_gsw_probe,
247 .switch_config = mt7621_gsw_config,
248 .reg_table = mt7621_reg_table,
249 .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
250 .rx_dly_int = RT5350_RX_DLY_INT,
251 .tx_dly_int = RT5350_TX_DLY_INT,
252 .checksum_bit = MT7621_L4_VALID,
253 .tx_udf_bit = MT7621_TX_DMA_UDF,
254 .has_carrier = mt7620a_has_carrier,
255 .mdio_read = mt7620_mdio_read,
256 .mdio_write = mt7620_mdio_write,
257 .mdio_adjust_link = mt7620_mdio_link_adjust,
258 };
259
260 const struct of_device_id of_fe_match[] = {
261 { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
262 { .compatible = "ralink,mt7621-eth", .data = &mt7621_data },
263 {},
264 };
265
266 MODULE_DEVICE_TABLE(of, of_fe_match);