98323b3007340c3c6045fa5c28920e7cfe6da30d
[openwrt/openwrt.git] / target / linux / ramips / patches-3.10 / 0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
1 From ad11aedcc16574c0b3d3f5e40c67227d1846b94e Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 16/33] NET: MIPS: add ralink SoC ethernet driver
5
6 Add support for Ralink FE and ESW.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ralink/Kconfig | 31 +
15 drivers/net/ethernet/ralink/Makefile | 18 +
16 drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
17 drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
18 drivers/net/ethernet/ralink/gsw_mt7620a.c | 1027 ++++++++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.h | 29 +
20 drivers/net/ethernet/ralink/mdio.c | 245 ++++
21 drivers/net/ethernet/ralink/mdio.h | 29 +
22 drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
23 drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
24 drivers/net/ethernet/ralink/ralink_soc_eth.c | 735 ++++++++++
25 drivers/net/ethernet/ralink/ralink_soc_eth.h | 374 +++++
26 drivers/net/ethernet/ralink/soc_mt7620.c | 111 ++
27 drivers/net/ethernet/ralink/soc_rt2880.c | 51 +
28 drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
29 drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
30 20 files changed, 4606 insertions(+)
31 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
32 create mode 100644 drivers/net/ethernet/ralink/Kconfig
33 create mode 100644 drivers/net/ethernet/ralink/Makefile
34 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
35 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
36 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
37 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
38 create mode 100644 drivers/net/ethernet/ralink/mdio.c
39 create mode 100644 drivers/net/ethernet/ralink/mdio.h
40 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
41 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
42 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
43 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
44 create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
45 create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
46 create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
47 create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
48
49 Index: linux-3.10.18/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
50 ===================================================================
51 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
52 +++ linux-3.10.18/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h 2013-11-21 15:20:28.672444348 +0100
53 @@ -0,0 +1,27 @@
54 +/*
55 + * Ralink RT305x SoC platform device registration
56 + *
57 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
58 + *
59 + * This program is free software; you can redistribute it and/or modify it
60 + * under the terms of the GNU General Public License version 2 as published
61 + * by the Free Software Foundation.
62 + */
63 +
64 +#ifndef _RT305X_ESW_PLATFORM_H
65 +#define _RT305X_ESW_PLATFORM_H
66 +
67 +enum {
68 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
69 + RT305X_ESW_VLAN_CONFIG_LLLLW,
70 + RT305X_ESW_VLAN_CONFIG_WLLLL,
71 +};
72 +
73 +struct rt305x_esw_platform_data
74 +{
75 + u8 vlan_config;
76 + u32 reg_initval_fct2;
77 + u32 reg_initval_fpa2;
78 +};
79 +
80 +#endif /* _RT305X_ESW_PLATFORM_H */
81 Index: linux-3.10.18/arch/mips/ralink/rt305x.c
82 ===================================================================
83 --- linux-3.10.18.orig/arch/mips/ralink/rt305x.c 2013-11-04 13:31:29.000000000 +0100
84 +++ linux-3.10.18/arch/mips/ralink/rt305x.c 2013-11-21 19:39:11.280814230 +0100
85 @@ -221,6 +221,7 @@
86 }
87
88 ralink_clk_add("cpu", cpu_rate);
89 + ralink_clk_add("sys", sys_rate);
90 ralink_clk_add("10000b00.spi", sys_rate);
91 ralink_clk_add("10000100.timer", wdt_rate);
92 ralink_clk_add("10000120.watchdog", wdt_rate);
93 Index: linux-3.10.18/drivers/net/ethernet/Kconfig
94 ===================================================================
95 --- linux-3.10.18.orig/drivers/net/ethernet/Kconfig 2013-11-04 13:31:29.000000000 +0100
96 +++ linux-3.10.18/drivers/net/ethernet/Kconfig 2013-11-21 15:20:28.672444348 +0100
97 @@ -135,6 +135,7 @@
98 source "drivers/net/ethernet/packetengines/Kconfig"
99 source "drivers/net/ethernet/pasemi/Kconfig"
100 source "drivers/net/ethernet/qlogic/Kconfig"
101 +source "drivers/net/ethernet/ralink/Kconfig"
102 source "drivers/net/ethernet/realtek/Kconfig"
103 source "drivers/net/ethernet/renesas/Kconfig"
104 source "drivers/net/ethernet/rdc/Kconfig"
105 Index: linux-3.10.18/drivers/net/ethernet/Makefile
106 ===================================================================
107 --- linux-3.10.18.orig/drivers/net/ethernet/Makefile 2013-11-04 13:31:29.000000000 +0100
108 +++ linux-3.10.18/drivers/net/ethernet/Makefile 2013-11-21 15:20:28.672444348 +0100
109 @@ -53,6 +53,7 @@
110 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
111 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
112 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
113 +obj-$(CONFIG_NET_RALINK) += ralink/
114 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
115 obj-$(CONFIG_SH_ETH) += renesas/
116 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
117 Index: linux-3.10.18/drivers/net/ethernet/ralink/Kconfig
118 ===================================================================
119 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
120 +++ linux-3.10.18/drivers/net/ethernet/ralink/Kconfig 2013-11-21 15:20:28.672444348 +0100
121 @@ -0,0 +1,32 @@
122 +config NET_RALINK
123 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
124 + depends on RALINK
125 + help
126 + This driver supports the ethernet mac inside the ralink wisocs
127 +
128 +if NET_RALINK
129 +
130 +config NET_RALINK_MDIO
131 + def_bool NET_RALINK
132 + depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
133 + select PHYLIB
134 +
135 +config NET_RALINK_MDIO_RT2880
136 + def_bool NET_RALINK
137 + depends on (SOC_RT288X || SOC_RT3883)
138 + select NET_RALINK_MDIO
139 +
140 +config NET_RALINK_ESW_RT3052
141 + def_bool NET_RALINK
142 + depends on SOC_RT305X
143 + select PHYLIB
144 + select SWCONFIG
145 +
146 +config NET_RALINK_GSW_MT7620
147 + def_bool NET_RALINK
148 + depends on SOC_MT7620
149 + select INET_LRO
150 + select NET_RALINK_MDIO
151 + select PHYLIB
152 + select SWCONFIG
153 +endif
154 Index: linux-3.10.18/drivers/net/ethernet/ralink/Makefile
155 ===================================================================
156 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
157 +++ linux-3.10.18/drivers/net/ethernet/ralink/Makefile 2013-11-21 15:20:28.672444348 +0100
158 @@ -0,0 +1,18 @@
159 +#
160 +# Makefile for the Ralink SoCs built-in ethernet macs
161 +#
162 +
163 +ralink-eth-y += ralink_soc_eth.o
164 +
165 +ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
166 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
167 +
168 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
169 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o mt7530.o
170 +
171 +ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
172 +ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
173 +ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
174 +ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
175 +
176 +obj-$(CONFIG_NET_RALINK) += ralink-eth.o
177 Index: linux-3.10.18/drivers/net/ethernet/ralink/esw_rt3052.c
178 ===================================================================
179 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
180 +++ linux-3.10.18/drivers/net/ethernet/ralink/esw_rt3052.c 2013-11-21 15:20:28.676444348 +0100
181 @@ -0,0 +1,1463 @@
182 +/*
183 + * This program is free software; you can redistribute it and/or modify
184 + * it under the terms of the GNU General Public License as published by
185 + * the Free Software Foundation; version 2 of the License
186 + *
187 + * This program is distributed in the hope that it will be useful,
188 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
189 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
190 + * GNU General Public License for more details.
191 + *
192 + * You should have received a copy of the GNU General Public License
193 + * along with this program; if not, write to the Free Software
194 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
195 + *
196 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
197 + */
198 +
199 +#include <linux/module.h>
200 +#include <linux/kernel.h>
201 +#include <linux/types.h>
202 +#include <linux/dma-mapping.h>
203 +#include <linux/init.h>
204 +#include <linux/skbuff.h>
205 +#include <linux/etherdevice.h>
206 +#include <linux/ethtool.h>
207 +#include <linux/platform_device.h>
208 +#include <linux/of_device.h>
209 +#include <linux/clk.h>
210 +#include <linux/of_net.h>
211 +#include <linux/of_mdio.h>
212 +
213 +#include <asm/mach-ralink/ralink_regs.h>
214 +
215 +#include "ralink_soc_eth.h"
216 +
217 +#include <linux/ioport.h>
218 +#include <linux/switch.h>
219 +#include <linux/mii.h>
220 +
221 +#include <ralink_regs.h>
222 +#include <asm/mach-ralink/rt305x.h>
223 +#include <asm/mach-ralink/rt305x_esw_platform.h>
224 +
225 +/*
226 + * HW limitations for this switch:
227 + * - No large frame support (PKT_MAX_LEN at most 1536)
228 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
229 + * though this might be possible using the undocumented PPE.
230 + */
231 +
232 +#define RT305X_ESW_REG_ISR 0x00
233 +#define RT305X_ESW_REG_IMR 0x04
234 +#define RT305X_ESW_REG_FCT0 0x08
235 +#define RT305X_ESW_REG_PFC1 0x14
236 +#define RT305X_ESW_REG_ATS 0x24
237 +#define RT305X_ESW_REG_ATS0 0x28
238 +#define RT305X_ESW_REG_ATS1 0x2c
239 +#define RT305X_ESW_REG_ATS2 0x30
240 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
241 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
242 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
243 +#define RT305X_ESW_REG_POA 0x80
244 +#define RT305X_ESW_REG_FPA 0x84
245 +#define RT305X_ESW_REG_SOCPC 0x8c
246 +#define RT305X_ESW_REG_POC0 0x90
247 +#define RT305X_ESW_REG_POC1 0x94
248 +#define RT305X_ESW_REG_POC2 0x98
249 +#define RT305X_ESW_REG_SGC 0x9c
250 +#define RT305X_ESW_REG_STRT 0xa0
251 +#define RT305X_ESW_REG_PCR0 0xc0
252 +#define RT305X_ESW_REG_PCR1 0xc4
253 +#define RT305X_ESW_REG_FPA2 0xc8
254 +#define RT305X_ESW_REG_FCT2 0xcc
255 +#define RT305X_ESW_REG_SGC2 0xe4
256 +#define RT305X_ESW_REG_P0LED 0xa4
257 +#define RT305X_ESW_REG_P1LED 0xa8
258 +#define RT305X_ESW_REG_P2LED 0xac
259 +#define RT305X_ESW_REG_P3LED 0xb0
260 +#define RT305X_ESW_REG_P4LED 0xb4
261 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
262 +#define RT305X_ESW_REG_P1PC 0xec
263 +#define RT305X_ESW_REG_P2PC 0xf0
264 +#define RT305X_ESW_REG_P3PC 0xf4
265 +#define RT305X_ESW_REG_P4PC 0xf8
266 +#define RT305X_ESW_REG_P5PC 0xfc
267 +
268 +#define RT305X_ESW_LED_LINK 0
269 +#define RT305X_ESW_LED_100M 1
270 +#define RT305X_ESW_LED_DUPLEX 2
271 +#define RT305X_ESW_LED_ACTIVITY 3
272 +#define RT305X_ESW_LED_COLLISION 4
273 +#define RT305X_ESW_LED_LINKACT 5
274 +#define RT305X_ESW_LED_DUPLCOLL 6
275 +#define RT305X_ESW_LED_10MACT 7
276 +#define RT305X_ESW_LED_100MACT 8
277 +/* Additional led states not in datasheet: */
278 +#define RT305X_ESW_LED_BLINK 10
279 +#define RT305X_ESW_LED_ON 12
280 +
281 +#define RT305X_ESW_LINK_S 25
282 +#define RT305X_ESW_DUPLEX_S 9
283 +#define RT305X_ESW_SPD_S 0
284 +
285 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
286 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
287 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
288 +
289 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
290 +
291 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
292 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
293 +
294 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
295 +#define RT305X_ESW_PVIDC_PVID_S 12
296 +
297 +#define RT305X_ESW_VLANI_VID_M 0xfff
298 +#define RT305X_ESW_VLANI_VID_S 12
299 +
300 +#define RT305X_ESW_VMSC_MSC_M 0xff
301 +#define RT305X_ESW_VMSC_MSC_S 8
302 +
303 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
304 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
305 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
306 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
307 +
308 +#define RT305X_ESW_POC0_EN_BP_S 0
309 +#define RT305X_ESW_POC0_EN_FC_S 8
310 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
311 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
312 +#define RT305X_ESW_POC0_DIS_PORT_S 23
313 +
314 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
315 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
316 +#define RT305X_ESW_POC2_ENAGING_S 8
317 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
318 +
319 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
320 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
321 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
322 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
323 +
324 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
325 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
326 +#define RT305X_ESW_PFC1_EN_TOS_S 24
327 +
328 +#define RT305X_ESW_VLAN_NONE 0xfff
329 +
330 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
331 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
332 +
333 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
334 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
335 +
336 +#define RT305X_ESW_POA_LINK_MASK 0x1f
337 +#define RT305X_ESW_POA_LINK_SHIFT 25
338 +
339 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
340 +#define RT305X_ESW_PORT0 0
341 +#define RT305X_ESW_PORT1 1
342 +#define RT305X_ESW_PORT2 2
343 +#define RT305X_ESW_PORT3 3
344 +#define RT305X_ESW_PORT4 4
345 +#define RT305X_ESW_PORT5 5
346 +#define RT305X_ESW_PORT6 6
347 +
348 +#define RT305X_ESW_PORTS_NONE 0
349 +
350 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
351 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
352 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
353 +
354 +#define RT305X_ESW_PORTS_INTERNAL \
355 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
356 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
357 + BIT(RT305X_ESW_PORT4))
358 +
359 +#define RT305X_ESW_PORTS_NOCPU \
360 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
361 +
362 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
363 +
364 +#define RT305X_ESW_PORTS_ALL \
365 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
366 +
367 +#define RT305X_ESW_NUM_VLANS 16
368 +#define RT305X_ESW_NUM_VIDS 4096
369 +#define RT305X_ESW_NUM_PORTS 7
370 +#define RT305X_ESW_NUM_LANWAN 6
371 +#define RT305X_ESW_NUM_LEDS 5
372 +
373 +#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
374 +#define RT5350_EWS_REG_LED_POLARITY 0x168
375 +#define RT5350_RESET_EPHY BIT(24)
376 +#define SYSC_REG_RESET_CTRL 0x34
377 +
378 +enum {
379 + /* Global attributes. */
380 + RT305X_ESW_ATTR_ENABLE_VLAN,
381 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
382 + RT305X_ESW_ATTR_BC_STATUS,
383 + RT305X_ESW_ATTR_LED_FREQ,
384 + /* Port attributes. */
385 + RT305X_ESW_ATTR_PORT_DISABLE,
386 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
387 + RT305X_ESW_ATTR_PORT_UNTAG,
388 + RT305X_ESW_ATTR_PORT_LED,
389 + RT305X_ESW_ATTR_PORT_LAN,
390 + RT305X_ESW_ATTR_PORT_RECV_BAD,
391 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
392 + RT5350_ESW_ATTR_PORT_TR_BAD,
393 + RT5350_ESW_ATTR_PORT_TR_GOOD,
394 +};
395 +
396 +struct esw_port {
397 + bool disable;
398 + bool doubletag;
399 + bool untag;
400 + u8 led;
401 + u16 pvid;
402 +};
403 +
404 +struct esw_vlan {
405 + u8 ports;
406 + u16 vid;
407 +};
408 +
409 +struct rt305x_esw {
410 + struct device *dev;
411 + void __iomem *base;
412 + int irq;
413 + const struct rt305x_esw_platform_data *pdata;
414 + /* Protects against concurrent register rmw operations. */
415 + spinlock_t reg_rw_lock;
416 +
417 + unsigned char port_map;
418 + unsigned int reg_initval_fct2;
419 + unsigned int reg_initval_fpa2;
420 + unsigned int reg_led_polarity;
421 +
422 +
423 + struct switch_dev swdev;
424 + bool global_vlan_enable;
425 + bool alt_vlan_disable;
426 + int bc_storm_protect;
427 + int led_frequency;
428 + struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
429 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
430 +
431 +};
432 +
433 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
434 +{
435 + __raw_writel(val, esw->base + reg);
436 +}
437 +
438 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
439 +{
440 + return __raw_readl(esw->base + reg);
441 +}
442 +
443 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
444 + unsigned long val)
445 +{
446 + unsigned long t;
447 +
448 + t = __raw_readl(esw->base + reg) & ~mask;
449 + __raw_writel(t | val, esw->base + reg);
450 +}
451 +
452 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
453 + unsigned long val)
454 +{
455 + unsigned long flags;
456 +
457 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
458 + esw_rmw_raw(esw, reg, mask, val);
459 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
460 +}
461 +
462 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
463 + u32 write_data)
464 +{
465 + unsigned long t_start = jiffies;
466 + int ret = 0;
467 +
468 + while (1) {
469 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
470 + RT305X_ESW_PCR1_WT_DONE))
471 + break;
472 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
473 + ret = 1;
474 + goto out;
475 + }
476 + }
477 +
478 + write_data &= 0xffff;
479 + esw_w32(esw,
480 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
481 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
482 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
483 + RT305X_ESW_REG_PCR0);
484 +
485 + t_start = jiffies;
486 + while (1) {
487 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
488 + RT305X_ESW_PCR1_WT_DONE)
489 + break;
490 +
491 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
492 + ret = 1;
493 + break;
494 + }
495 + }
496 +out:
497 + if (ret)
498 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
499 + return ret;
500 +}
501 +
502 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
503 +{
504 + unsigned s;
505 + unsigned val;
506 +
507 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
508 + val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
509 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
510 +
511 + return val;
512 +}
513 +
514 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
515 +{
516 + unsigned s;
517 +
518 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
519 + esw_rmw(esw,
520 + RT305X_ESW_REG_VLANI(vlan / 2),
521 + RT305X_ESW_VLANI_VID_M << s,
522 + (vid & RT305X_ESW_VLANI_VID_M) << s);
523 +}
524 +
525 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
526 +{
527 + unsigned s, val;
528 +
529 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
530 + val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
531 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
532 +}
533 +
534 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
535 +{
536 + unsigned s;
537 +
538 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
539 + esw_rmw(esw,
540 + RT305X_ESW_REG_PVIDC(port / 2),
541 + RT305X_ESW_PVIDC_PVID_M << s,
542 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
543 +}
544 +
545 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
546 +{
547 + unsigned s, val;
548 +
549 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
550 + val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
551 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
552 +
553 + return val;
554 +}
555 +
556 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
557 +{
558 + unsigned s;
559 +
560 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
561 + esw_rmw(esw,
562 + RT305X_ESW_REG_VMSC(vlan / 4),
563 + RT305X_ESW_VMSC_MSC_M << s,
564 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
565 +}
566 +
567 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
568 +{
569 + unsigned reg;
570 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
571 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
572 + RT305X_ESW_POC0_DIS_PORT_M;
573 +}
574 +
575 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
576 +{
577 + unsigned old_mask;
578 + unsigned enable_mask;
579 + unsigned changed;
580 + int i;
581 +
582 + old_mask = esw_get_port_disable(esw);
583 + changed = old_mask ^ disable_mask;
584 + enable_mask = old_mask & disable_mask;
585 +
586 + /* enable before writing to MII */
587 + esw_rmw(esw, RT305X_ESW_REG_POC0,
588 + (RT305X_ESW_POC0_DIS_PORT_M <<
589 + RT305X_ESW_POC0_DIS_PORT_S),
590 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
591 +
592 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
593 + if (!(changed & (1 << i)))
594 + continue;
595 + if (disable_mask & (1 << i)) {
596 + /* disable */
597 + rt305x_mii_write(esw, i, MII_BMCR,
598 + BMCR_PDOWN);
599 + } else {
600 + /* enable */
601 + rt305x_mii_write(esw, i, MII_BMCR,
602 + BMCR_FULLDPLX |
603 + BMCR_ANENABLE |
604 + BMCR_ANRESTART |
605 + BMCR_SPEED100);
606 + }
607 + }
608 +
609 + /* disable after writing to MII */
610 + esw_rmw(esw, RT305X_ESW_REG_POC0,
611 + (RT305X_ESW_POC0_DIS_PORT_M <<
612 + RT305X_ESW_POC0_DIS_PORT_S),
613 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
614 +}
615 +
616 +static void esw_set_gsc(struct rt305x_esw *esw)
617 +{
618 + esw_rmw(esw, RT305X_ESW_REG_SGC,
619 + RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
620 + esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
621 + esw_rmw(esw, RT305X_ESW_REG_SGC,
622 + RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
623 + esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
624 +}
625 +
626 +static int esw_apply_config(struct switch_dev *dev);
627 +
628 +static void esw_hw_init(struct rt305x_esw *esw)
629 +{
630 + int i;
631 + u8 port_disable = 0;
632 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
633 +
634 + /* vodoo from original driver */
635 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
636 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
637 + /* Port priority 1 for all ports, vlan enabled. */
638 + esw_w32(esw, 0x00005555 |
639 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
640 + RT305X_ESW_REG_PFC1);
641 +
642 + /* Enable Back Pressure, and Flow Control */
643 + esw_w32(esw,
644 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
645 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
646 + RT305X_ESW_REG_POC0);
647 +
648 + /* Enable Aging, and VLAN TAG removal */
649 + esw_w32(esw,
650 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
651 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
652 + RT305X_ESW_REG_POC2);
653 +
654 + if (esw->reg_initval_fct2)
655 + esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
656 + else
657 + esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
658 +
659 + /*
660 + * 300s aging timer, max packet len 1536, broadcast storm prevention
661 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
662 + * pressure jam, GMII disable was_transmit, back pressure disabled,
663 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
664 + * ports.
665 + */
666 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
667 +
668 + /* Setup SoC Port control register */
669 + esw_w32(esw,
670 + (RT305X_ESW_SOCPC_CRC_PADDING |
671 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
672 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
673 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
674 + RT305X_ESW_REG_SOCPC);
675 +
676 + if (esw->reg_initval_fpa2)
677 + esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
678 + else
679 + esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
680 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
681 +
682 + /* Force Link/Activity on ports */
683 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
684 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
685 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
686 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
687 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
688 +
689 + /* Copy disabled port configuration from bootloader setup */
690 + port_disable = esw_get_port_disable(esw);
691 + for (i = 0; i < 6; i++)
692 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
693 +
694 + if (soc_is_rt3352()) {
695 + /* reset EPHY */
696 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
697 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
698 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
699 +
700 + rt305x_mii_write(esw, 0, 31, 0x8000);
701 + for (i = 0; i < 5; i++) {
702 + if (esw->ports[i].disable) {
703 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
704 + } else {
705 + rt305x_mii_write(esw, i, MII_BMCR,
706 + BMCR_FULLDPLX |
707 + BMCR_ANENABLE |
708 + BMCR_SPEED100);
709 + }
710 + /* TX10 waveform coefficient LSB=0 disable PHY */
711 + rt305x_mii_write(esw, i, 26, 0x1601);
712 + /* TX100/TX10 AD/DA current bias */
713 + rt305x_mii_write(esw, i, 29, 0x7016);
714 + /* TX100 slew rate control */
715 + rt305x_mii_write(esw, i, 30, 0x0038);
716 + }
717 +
718 + /* select global register */
719 + rt305x_mii_write(esw, 0, 31, 0x0);
720 + /* enlarge agcsel threshold 3 and threshold 2 */
721 + rt305x_mii_write(esw, 0, 1, 0x4a40);
722 + /* enlarge agcsel threshold 5 and threshold 4 */
723 + rt305x_mii_write(esw, 0, 2, 0x6254);
724 + /* enlarge agcsel threshold */
725 + rt305x_mii_write(esw, 0, 3, 0xa17f);
726 + rt305x_mii_write(esw, 0,12, 0x7eaa);
727 + /* longer TP_IDL tail length */
728 + rt305x_mii_write(esw, 0, 14, 0x65);
729 + /* increased squelch pulse count threshold. */
730 + rt305x_mii_write(esw, 0, 16, 0x0684);
731 + /* set TX10 signal amplitude threshold to minimum */
732 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
733 + /* set squelch amplitude to higher threshold */
734 + rt305x_mii_write(esw, 0, 18, 0x40ba);
735 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
736 + rt305x_mii_write(esw, 0, 22, 0x253f);
737 + /* set PLL/Receive bias current are calibrated */
738 + rt305x_mii_write(esw, 0, 27, 0x2fda);
739 + /* change PLL/Receive bias current to internal(RT3350) */
740 + rt305x_mii_write(esw, 0, 28, 0xc410);
741 + /* change PLL bias current to internal(RT3052_MP3) */
742 + rt305x_mii_write(esw, 0, 29, 0x598b);
743 + /* select local register */
744 + rt305x_mii_write(esw, 0, 31, 0x8000);
745 + } else if (soc_is_rt5350()) {
746 + /* reset EPHY */
747 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
748 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
749 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
750 +
751 + /* set the led polarity */
752 + esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
753 +
754 + /* local registers */
755 + rt305x_mii_write(esw, 0, 31, 0x8000);
756 + for (i = 0; i < 5; i++) {
757 + if (esw->ports[i].disable) {
758 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
759 + } else {
760 + rt305x_mii_write(esw, i, MII_BMCR,
761 + BMCR_FULLDPLX |
762 + BMCR_ANENABLE |
763 + BMCR_SPEED100);
764 + }
765 + /* TX10 waveform coefficient LSB=0 disable PHY */
766 + rt305x_mii_write(esw, i, 26, 0x1601);
767 + /* TX100/TX10 AD/DA current bias */
768 + rt305x_mii_write(esw, i, 29, 0x7015);
769 + /* TX100 slew rate control */
770 + rt305x_mii_write(esw, i, 30, 0x0038);
771 + }
772 +
773 + /* global registers */
774 + rt305x_mii_write(esw, 0, 31, 0x0);
775 + /* enlarge agcsel threshold 3 and threshold 2 */
776 + rt305x_mii_write(esw, 0, 1, 0x4a40);
777 + /* enlarge agcsel threshold 5 and threshold 4 */
778 + rt305x_mii_write(esw, 0, 2, 0x6254);
779 + /* enlarge agcsel threshold 6 */
780 + rt305x_mii_write(esw, 0, 3, 0xa17f);
781 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
782 + /* longer TP_IDL tail length */
783 + rt305x_mii_write(esw, 0, 14, 0x65);
784 + /* increased squelch pulse count threshold. */
785 + rt305x_mii_write(esw, 0, 16, 0x0684);
786 + /* set TX10 signal amplitude threshold to minimum */
787 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
788 + /* set squelch amplitude to higher threshold */
789 + rt305x_mii_write(esw, 0, 18, 0x40ba);
790 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
791 + rt305x_mii_write(esw, 0, 22, 0x253f);
792 + /* set PLL/Receive bias current are calibrated */
793 + rt305x_mii_write(esw, 0, 27, 0x2fda);
794 + /* change PLL/Receive bias current to internal(RT3350) */
795 + rt305x_mii_write(esw, 0, 28, 0xc410);
796 + /* change PLL bias current to internal(RT3052_MP3) */
797 + rt305x_mii_write(esw, 0, 29, 0x598b);
798 + /* select local register */
799 + rt305x_mii_write(esw, 0, 31, 0x8000);
800 + } else {
801 + rt305x_mii_write(esw, 0, 31, 0x8000);
802 + for (i = 0; i < 5; i++) {
803 + if (esw->ports[i].disable) {
804 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
805 + } else {
806 + rt305x_mii_write(esw, i, MII_BMCR,
807 + BMCR_FULLDPLX |
808 + BMCR_ANENABLE |
809 + BMCR_SPEED100);
810 + }
811 + /* TX10 waveform coefficient */
812 + rt305x_mii_write(esw, i, 26, 0x1601);
813 + /* TX100/TX10 AD/DA current bias */
814 + rt305x_mii_write(esw, i, 29, 0x7058);
815 + /* TX100 slew rate control */
816 + rt305x_mii_write(esw, i, 30, 0x0018);
817 + }
818 +
819 + /* PHY IOT */
820 + /* select global register */
821 + rt305x_mii_write(esw, 0, 31, 0x0);
822 + /* tune TP_IDL tail and head waveform */
823 + rt305x_mii_write(esw, 0, 22, 0x052f);
824 + /* set TX10 signal amplitude threshold to minimum */
825 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
826 + /* set squelch amplitude to higher threshold */
827 + rt305x_mii_write(esw, 0, 18, 0x40ba);
828 + /* longer TP_IDL tail length */
829 + rt305x_mii_write(esw, 0, 14, 0x65);
830 + /* select local register */
831 + rt305x_mii_write(esw, 0, 31, 0x8000);
832 + }
833 +
834 + if (esw->port_map)
835 + port_map = esw->port_map;
836 + else
837 + port_map = RT305X_ESW_PMAP_LLLLLL;
838 +
839 + /*
840 + * Unused HW feature, but still nice to be consistent here...
841 + * This is also exported to userspace ('lan' attribute) so it's
842 + * conveniently usable to decide which ports go into the wan vlan by
843 + * default.
844 + */
845 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
846 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
847 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
848 +
849 + /* make the switch leds blink */
850 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
851 + esw->ports[i].led = 0x05;
852 +
853 + /* Apply the empty config. */
854 + esw_apply_config(&esw->swdev);
855 +
856 + /* Only unmask the port change interrupt */
857 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
858 +}
859 +
860 +static irqreturn_t esw_interrupt(int irq, void *_esw)
861 +{
862 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
863 + u32 status;
864 +
865 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
866 + if (status & RT305X_ESW_PORT_ST_CHG) {
867 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
868 + link >>= RT305X_ESW_POA_LINK_SHIFT;
869 + link &= RT305X_ESW_POA_LINK_MASK;
870 + dev_info(esw->dev, "link changed 0x%02X\n", link);
871 + }
872 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
873 +
874 + return IRQ_HANDLED;
875 +}
876 +
877 +static int esw_apply_config(struct switch_dev *dev)
878 +{
879 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
880 + int i;
881 + u8 disable = 0;
882 + u8 doubletag = 0;
883 + u8 en_vlan = 0;
884 + u8 untag = 0;
885 +
886 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
887 + u32 vid, vmsc;
888 + if (esw->global_vlan_enable) {
889 + vid = esw->vlans[i].vid;
890 + vmsc = esw->vlans[i].ports;
891 + } else {
892 + vid = RT305X_ESW_VLAN_NONE;
893 + vmsc = RT305X_ESW_PORTS_NONE;
894 + }
895 + esw_set_vlan_id(esw, i, vid);
896 + esw_set_vmsc(esw, i, vmsc);
897 + }
898 +
899 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
900 + u32 pvid;
901 + disable |= esw->ports[i].disable << i;
902 + if (esw->global_vlan_enable) {
903 + doubletag |= esw->ports[i].doubletag << i;
904 + en_vlan |= 1 << i;
905 + untag |= esw->ports[i].untag << i;
906 + pvid = esw->ports[i].pvid;
907 + } else {
908 + int x = esw->alt_vlan_disable ? 0 : 1;
909 + doubletag |= x << i;
910 + en_vlan |= x << i;
911 + untag |= x << i;
912 + pvid = 0;
913 + }
914 + esw_set_pvid(esw, i, pvid);
915 + if (i < RT305X_ESW_NUM_LEDS)
916 + esw_w32(esw, esw->ports[i].led,
917 + RT305X_ESW_REG_P0LED + 4*i);
918 + }
919 +
920 + esw_set_gsc(esw);
921 + esw_set_port_disable(esw, disable);
922 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
923 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
924 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
925 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
926 + esw_rmw(esw, RT305X_ESW_REG_PFC1,
927 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
928 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
929 + esw_rmw(esw, RT305X_ESW_REG_POC2,
930 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
931 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
932 +
933 + if (!esw->global_vlan_enable) {
934 + /*
935 + * Still need to put all ports into vlan 0 or they'll be
936 + * isolated.
937 + * NOTE: vlan 0 is special, no vlan tag is prepended
938 + */
939 + esw_set_vlan_id(esw, 0, 0);
940 + esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
941 + }
942 +
943 + return 0;
944 +}
945 +
946 +static int esw_reset_switch(struct switch_dev *dev)
947 +{
948 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
949 +
950 + esw->global_vlan_enable = 0;
951 + memset(esw->ports, 0, sizeof(esw->ports));
952 + memset(esw->vlans, 0, sizeof(esw->vlans));
953 + esw_hw_init(esw);
954 +
955 + return 0;
956 +}
957 +
958 +static int esw_get_vlan_enable(struct switch_dev *dev,
959 + const struct switch_attr *attr,
960 + struct switch_val *val)
961 +{
962 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
963 +
964 + val->value.i = esw->global_vlan_enable;
965 +
966 + return 0;
967 +}
968 +
969 +static int esw_set_vlan_enable(struct switch_dev *dev,
970 + const struct switch_attr *attr,
971 + struct switch_val *val)
972 +{
973 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
974 +
975 + esw->global_vlan_enable = val->value.i != 0;
976 +
977 + return 0;
978 +}
979 +
980 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
981 + const struct switch_attr *attr,
982 + struct switch_val *val)
983 +{
984 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
985 +
986 + val->value.i = esw->alt_vlan_disable;
987 +
988 + return 0;
989 +}
990 +
991 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
992 + const struct switch_attr *attr,
993 + struct switch_val *val)
994 +{
995 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
996 +
997 + esw->alt_vlan_disable = val->value.i != 0;
998 +
999 + return 0;
1000 +}
1001 +
1002 +static int
1003 +rt305x_esw_set_bc_status(struct switch_dev *dev,
1004 + const struct switch_attr *attr,
1005 + struct switch_val *val)
1006 +{
1007 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1008 +
1009 + esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1010 +
1011 + return 0;
1012 +}
1013 +
1014 +static int
1015 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1016 + const struct switch_attr *attr,
1017 + struct switch_val *val)
1018 +{
1019 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1020 +
1021 + val->value.i = esw->bc_storm_protect;
1022 +
1023 + return 0;
1024 +}
1025 +
1026 +static int
1027 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1028 + const struct switch_attr *attr,
1029 + struct switch_val *val)
1030 +{
1031 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1032 +
1033 + esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1034 +
1035 + return 0;
1036 +}
1037 +
1038 +static int
1039 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1040 + const struct switch_attr *attr,
1041 + struct switch_val *val)
1042 +{
1043 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1044 +
1045 + val->value.i = esw->led_frequency;
1046 +
1047 + return 0;
1048 +}
1049 +
1050 +static int esw_get_port_link(struct switch_dev *dev,
1051 + int port,
1052 + struct switch_port_link *link)
1053 +{
1054 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1055 + u32 speed, poa;
1056 +
1057 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1058 + return -EINVAL;
1059 +
1060 + poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1061 +
1062 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1063 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1064 + if (port < RT305X_ESW_NUM_LEDS) {
1065 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
1066 + } else {
1067 + if (port == RT305X_ESW_NUM_PORTS - 1)
1068 + poa >>= 1;
1069 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
1070 + }
1071 + switch (speed) {
1072 + case 0:
1073 + link->speed = SWITCH_PORT_SPEED_10;
1074 + break;
1075 + case 1:
1076 + link->speed = SWITCH_PORT_SPEED_100;
1077 + break;
1078 + case 2:
1079 + case 3: /* forced gige speed can be 2 or 3 */
1080 + link->speed = SWITCH_PORT_SPEED_1000;
1081 + break;
1082 + default:
1083 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1084 + break;
1085 + }
1086 +
1087 + return 0;
1088 +}
1089 +
1090 +static int esw_get_port_bool(struct switch_dev *dev,
1091 + const struct switch_attr *attr,
1092 + struct switch_val *val)
1093 +{
1094 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1095 + int idx = val->port_vlan;
1096 + u32 x, reg, shift;
1097 +
1098 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1099 + return -EINVAL;
1100 +
1101 + switch (attr->id) {
1102 + case RT305X_ESW_ATTR_PORT_DISABLE:
1103 + reg = RT305X_ESW_REG_POC0;
1104 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1105 + break;
1106 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1107 + reg = RT305X_ESW_REG_SGC2;
1108 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1109 + break;
1110 + case RT305X_ESW_ATTR_PORT_UNTAG:
1111 + reg = RT305X_ESW_REG_POC2;
1112 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1113 + break;
1114 + case RT305X_ESW_ATTR_PORT_LAN:
1115 + reg = RT305X_ESW_REG_SGC2;
1116 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1117 + if (idx >= RT305X_ESW_NUM_LANWAN)
1118 + return -EINVAL;
1119 + break;
1120 + default:
1121 + return -EINVAL;
1122 + }
1123 +
1124 + x = esw_r32(esw, reg);
1125 + val->value.i = (x >> (idx + shift)) & 1;
1126 +
1127 + return 0;
1128 +}
1129 +
1130 +static int esw_set_port_bool(struct switch_dev *dev,
1131 + const struct switch_attr *attr,
1132 + struct switch_val *val)
1133 +{
1134 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1135 + int idx = val->port_vlan;
1136 +
1137 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1138 + val->value.i < 0 || val->value.i > 1)
1139 + return -EINVAL;
1140 +
1141 + switch (attr->id) {
1142 + case RT305X_ESW_ATTR_PORT_DISABLE:
1143 + esw->ports[idx].disable = val->value.i;
1144 + break;
1145 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1146 + esw->ports[idx].doubletag = val->value.i;
1147 + break;
1148 + case RT305X_ESW_ATTR_PORT_UNTAG:
1149 + esw->ports[idx].untag = val->value.i;
1150 + break;
1151 + default:
1152 + return -EINVAL;
1153 + }
1154 +
1155 + return 0;
1156 +}
1157 +
1158 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1159 + const struct switch_attr *attr,
1160 + struct switch_val *val)
1161 +{
1162 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1163 + int idx = val->port_vlan;
1164 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1165 + u32 reg;
1166 +
1167 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1168 + return -EINVAL;
1169 + reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1170 + val->value.i = (reg >> shift) & 0xffff;
1171 +
1172 + return 0;
1173 +}
1174 +
1175 +static int
1176 +esw_get_port_tr_badgood(struct switch_dev *dev,
1177 + const struct switch_attr *attr,
1178 + struct switch_val *val)
1179 +{
1180 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1181 +
1182 + int idx = val->port_vlan;
1183 + int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1184 + u32 reg;
1185 +
1186 + if (!soc_is_rt5350())
1187 + return -EINVAL;
1188 +
1189 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1190 + return -EINVAL;
1191 +
1192 + reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1193 + val->value.i = (reg >> shift) & 0xffff;
1194 +
1195 + return 0;
1196 +}
1197 +
1198 +static int esw_get_port_led(struct switch_dev *dev,
1199 + const struct switch_attr *attr,
1200 + struct switch_val *val)
1201 +{
1202 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1203 + int idx = val->port_vlan;
1204 +
1205 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1206 + idx >= RT305X_ESW_NUM_LEDS)
1207 + return -EINVAL;
1208 +
1209 + val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1210 +
1211 + return 0;
1212 +}
1213 +
1214 +static int esw_set_port_led(struct switch_dev *dev,
1215 + const struct switch_attr *attr,
1216 + struct switch_val *val)
1217 +{
1218 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1219 + int idx = val->port_vlan;
1220 +
1221 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1222 + return -EINVAL;
1223 +
1224 + esw->ports[idx].led = val->value.i;
1225 +
1226 + return 0;
1227 +}
1228 +
1229 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1230 +{
1231 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1232 +
1233 + if (port >= RT305X_ESW_NUM_PORTS)
1234 + return -EINVAL;
1235 +
1236 + *val = esw_get_pvid(esw, port);
1237 +
1238 + return 0;
1239 +}
1240 +
1241 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1242 +{
1243 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1244 +
1245 + if (port >= RT305X_ESW_NUM_PORTS)
1246 + return -EINVAL;
1247 +
1248 + esw->ports[port].pvid = val;
1249 +
1250 + return 0;
1251 +}
1252 +
1253 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1254 +{
1255 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1256 + u32 vmsc, poc2;
1257 + int vlan_idx = -1;
1258 + int i;
1259 +
1260 + val->len = 0;
1261 +
1262 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1263 + return -EINVAL;
1264 +
1265 + /* valid vlan? */
1266 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1267 + if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1268 + esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1269 + vlan_idx = i;
1270 + break;
1271 + }
1272 + }
1273 +
1274 + if (vlan_idx == -1)
1275 + return -EINVAL;
1276 +
1277 + vmsc = esw_get_vmsc(esw, vlan_idx);
1278 + poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1279 +
1280 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1281 + struct switch_port *p;
1282 + int port_mask = 1 << i;
1283 +
1284 + if (!(vmsc & port_mask))
1285 + continue;
1286 +
1287 + p = &val->value.ports[val->len++];
1288 + p->id = i;
1289 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1290 + p->flags = 0;
1291 + else
1292 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1293 + }
1294 +
1295 + return 0;
1296 +}
1297 +
1298 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1299 +{
1300 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1301 + int ports;
1302 + int vlan_idx = -1;
1303 + int i;
1304 +
1305 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1306 + val->len > RT305X_ESW_NUM_PORTS)
1307 + return -EINVAL;
1308 +
1309 + /* one of the already defined vlans? */
1310 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1311 + if (esw->vlans[i].vid == val->port_vlan &&
1312 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1313 + vlan_idx = i;
1314 + break;
1315 + }
1316 + }
1317 +
1318 + /* select a free slot */
1319 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1320 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1321 + vlan_idx = i;
1322 + }
1323 +
1324 + /* bail if all slots are in use */
1325 + if (vlan_idx == -1)
1326 + return -EINVAL;
1327 +
1328 + ports = RT305X_ESW_PORTS_NONE;
1329 + for (i = 0; i < val->len; i++) {
1330 + struct switch_port *p = &val->value.ports[i];
1331 + int port_mask = 1 << p->id;
1332 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1333 +
1334 + if (p->id >= RT305X_ESW_NUM_PORTS)
1335 + return -EINVAL;
1336 +
1337 + ports |= port_mask;
1338 + esw->ports[p->id].untag = untagged;
1339 + }
1340 + esw->vlans[vlan_idx].ports = ports;
1341 + if (ports == RT305X_ESW_PORTS_NONE)
1342 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1343 + else
1344 + esw->vlans[vlan_idx].vid = val->port_vlan;
1345 +
1346 + return 0;
1347 +}
1348 +
1349 +static const struct switch_attr esw_global[] = {
1350 + {
1351 + .type = SWITCH_TYPE_INT,
1352 + .name = "enable_vlan",
1353 + .description = "VLAN mode (1:enabled)",
1354 + .max = 1,
1355 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1356 + .get = esw_get_vlan_enable,
1357 + .set = esw_set_vlan_enable,
1358 + },
1359 + {
1360 + .type = SWITCH_TYPE_INT,
1361 + .name = "alternate_vlan_disable",
1362 + .description = "Use en_vlan instead of doubletag to disable"
1363 + " VLAN mode",
1364 + .max = 1,
1365 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1366 + .get = esw_get_alt_vlan_disable,
1367 + .set = esw_set_alt_vlan_disable,
1368 + },
1369 + {
1370 + .type = SWITCH_TYPE_INT,
1371 + .name = "bc_storm_protect",
1372 + .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1373 + .max = 3,
1374 + .id = RT305X_ESW_ATTR_BC_STATUS,
1375 + .get = rt305x_esw_get_bc_status,
1376 + .set = rt305x_esw_set_bc_status,
1377 + },
1378 + {
1379 + .type = SWITCH_TYPE_INT,
1380 + .name = "led_frequency",
1381 + .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1382 + .max = 3,
1383 + .id = RT305X_ESW_ATTR_LED_FREQ,
1384 + .get = rt305x_esw_get_led_freq,
1385 + .set = rt305x_esw_set_led_freq,
1386 + }
1387 +};
1388 +
1389 +static const struct switch_attr esw_port[] = {
1390 + {
1391 + .type = SWITCH_TYPE_INT,
1392 + .name = "disable",
1393 + .description = "Port state (1:disabled)",
1394 + .max = 1,
1395 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1396 + .get = esw_get_port_bool,
1397 + .set = esw_set_port_bool,
1398 + },
1399 + {
1400 + .type = SWITCH_TYPE_INT,
1401 + .name = "doubletag",
1402 + .description = "Double tagging for incoming vlan packets "
1403 + "(1:enabled)",
1404 + .max = 1,
1405 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1406 + .get = esw_get_port_bool,
1407 + .set = esw_set_port_bool,
1408 + },
1409 + {
1410 + .type = SWITCH_TYPE_INT,
1411 + .name = "untag",
1412 + .description = "Untag (1:strip outgoing vlan tag)",
1413 + .max = 1,
1414 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1415 + .get = esw_get_port_bool,
1416 + .set = esw_set_port_bool,
1417 + },
1418 + {
1419 + .type = SWITCH_TYPE_INT,
1420 + .name = "led",
1421 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1422 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1423 + " 8:100mact, 10:blink, 11:off, 12:on)",
1424 + .max = 15,
1425 + .id = RT305X_ESW_ATTR_PORT_LED,
1426 + .get = esw_get_port_led,
1427 + .set = esw_set_port_led,
1428 + },
1429 + {
1430 + .type = SWITCH_TYPE_INT,
1431 + .name = "lan",
1432 + .description = "HW port group (0:wan, 1:lan)",
1433 + .max = 1,
1434 + .id = RT305X_ESW_ATTR_PORT_LAN,
1435 + .get = esw_get_port_bool,
1436 + },
1437 + {
1438 + .type = SWITCH_TYPE_INT,
1439 + .name = "recv_bad",
1440 + .description = "Receive bad packet counter",
1441 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1442 + .get = esw_get_port_recv_badgood,
1443 + },
1444 + {
1445 + .type = SWITCH_TYPE_INT,
1446 + .name = "recv_good",
1447 + .description = "Receive good packet counter",
1448 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1449 + .get = esw_get_port_recv_badgood,
1450 + },
1451 + {
1452 + .type = SWITCH_TYPE_INT,
1453 + .name = "tr_bad",
1454 +
1455 + .description = "Transmit bad packet counter. rt5350 only",
1456 + .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1457 + .get = esw_get_port_tr_badgood,
1458 + },
1459 + {
1460 + .type = SWITCH_TYPE_INT,
1461 + .name = "tr_good",
1462 +
1463 + .description = "Transmit good packet counter. rt5350 only",
1464 + .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1465 + .get = esw_get_port_tr_badgood,
1466 + },
1467 +};
1468 +
1469 +static const struct switch_attr esw_vlan[] = {
1470 +};
1471 +
1472 +static const struct switch_dev_ops esw_ops = {
1473 + .attr_global = {
1474 + .attr = esw_global,
1475 + .n_attr = ARRAY_SIZE(esw_global),
1476 + },
1477 + .attr_port = {
1478 + .attr = esw_port,
1479 + .n_attr = ARRAY_SIZE(esw_port),
1480 + },
1481 + .attr_vlan = {
1482 + .attr = esw_vlan,
1483 + .n_attr = ARRAY_SIZE(esw_vlan),
1484 + },
1485 + .get_vlan_ports = esw_get_vlan_ports,
1486 + .set_vlan_ports = esw_set_vlan_ports,
1487 + .get_port_pvid = esw_get_port_pvid,
1488 + .set_port_pvid = esw_set_port_pvid,
1489 + .get_port_link = esw_get_port_link,
1490 + .apply_config = esw_apply_config,
1491 + .reset_switch = esw_reset_switch,
1492 +};
1493 +
1494 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1495 + /* All ports are LAN ports. */
1496 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1497 + .reg_initval_fct2 = 0x00d6500c,
1498 + /*
1499 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1500 + * turbo mii off, rgmi 3.3v off
1501 + * port5: disabled
1502 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1503 + */
1504 + .reg_initval_fpa2 = 0x3f502b28,
1505 +};
1506 +
1507 +static const struct of_device_id ralink_esw_match[] = {
1508 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1509 + {},
1510 +};
1511 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1512 +
1513 +static int esw_probe(struct platform_device *pdev)
1514 +{
1515 + struct device_node *np = pdev->dev.of_node;
1516 + const struct rt305x_esw_platform_data *pdata;
1517 + const __be32 *port_map, *reg_init;
1518 + struct rt305x_esw *esw;
1519 + struct switch_dev *swdev;
1520 + struct resource *res, *irq;
1521 + int err;
1522 +
1523 + pdata = pdev->dev.platform_data;
1524 + if (!pdata) {
1525 + const struct of_device_id *match;
1526 + match = of_match_device(ralink_esw_match, &pdev->dev);
1527 + if (match)
1528 + pdata = (struct rt305x_esw_platform_data *) match->data;
1529 + }
1530 + if (!pdata)
1531 + return -EINVAL;
1532 +
1533 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1534 + if (!res) {
1535 + dev_err(&pdev->dev, "no memory resource found\n");
1536 + return -ENOMEM;
1537 + }
1538 +
1539 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1540 + if (!irq) {
1541 + dev_err(&pdev->dev, "no irq resource found\n");
1542 + return -ENOMEM;
1543 + }
1544 +
1545 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1546 + if (!esw) {
1547 + dev_err(&pdev->dev, "no memory for private data\n");
1548 + return -ENOMEM;
1549 + }
1550 +
1551 + esw->dev = &pdev->dev;
1552 + esw->irq = irq->start;
1553 + esw->base = ioremap(res->start, resource_size(res));
1554 + if (!esw->base) {
1555 + dev_err(&pdev->dev, "ioremap failed\n");
1556 + err = -ENOMEM;
1557 + goto free_esw;
1558 + }
1559 +
1560 + port_map = of_get_property(np, "ralink,portmap", NULL);
1561 + if (port_map)
1562 + esw->port_map = be32_to_cpu(*port_map);
1563 +
1564 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1565 + if (reg_init)
1566 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1567 +
1568 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1569 + if (reg_init)
1570 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1571 +
1572 + reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1573 + if (reg_init)
1574 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
1575 +
1576 + swdev = &esw->swdev;
1577 + swdev->of_node = pdev->dev.of_node;
1578 + swdev->name = "rt305x-esw";
1579 + swdev->alias = "rt305x";
1580 + swdev->cpu_port = RT305X_ESW_PORT6;
1581 + swdev->ports = RT305X_ESW_NUM_PORTS;
1582 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1583 + swdev->ops = &esw_ops;
1584 +
1585 + err = register_switch(swdev, NULL);
1586 + if (err < 0) {
1587 + dev_err(&pdev->dev, "register_switch failed\n");
1588 + goto unmap_base;
1589 + }
1590 +
1591 + platform_set_drvdata(pdev, esw);
1592 +
1593 + esw->pdata = pdata;
1594 + spin_lock_init(&esw->reg_rw_lock);
1595 +
1596 + esw_hw_init(esw);
1597 +
1598 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1599 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1600 + request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1601 +
1602 + return 0;
1603 +
1604 +unmap_base:
1605 + iounmap(esw->base);
1606 +free_esw:
1607 + kfree(esw);
1608 + return err;
1609 +}
1610 +
1611 +static int esw_remove(struct platform_device *pdev)
1612 +{
1613 + struct rt305x_esw *esw;
1614 +
1615 + esw = platform_get_drvdata(pdev);
1616 + if (esw) {
1617 + unregister_switch(&esw->swdev);
1618 + platform_set_drvdata(pdev, NULL);
1619 + iounmap(esw->base);
1620 + kfree(esw);
1621 + }
1622 +
1623 + return 0;
1624 +}
1625 +
1626 +static struct platform_driver esw_driver = {
1627 + .probe = esw_probe,
1628 + .remove = esw_remove,
1629 + .driver = {
1630 + .name = "rt305x-esw",
1631 + .owner = THIS_MODULE,
1632 + .of_match_table = ralink_esw_match,
1633 + },
1634 +};
1635 +
1636 +int __init rtesw_init(void)
1637 +{
1638 + return platform_driver_register(&esw_driver);
1639 +}
1640 +
1641 +void rtesw_exit(void)
1642 +{
1643 + platform_driver_unregister(&esw_driver);
1644 +}
1645 Index: linux-3.10.18/drivers/net/ethernet/ralink/esw_rt3052.h
1646 ===================================================================
1647 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1648 +++ linux-3.10.18/drivers/net/ethernet/ralink/esw_rt3052.h 2013-11-21 15:20:28.676444348 +0100
1649 @@ -0,0 +1,32 @@
1650 +/*
1651 + * This program is free software; you can redistribute it and/or modify
1652 + * it under the terms of the GNU General Public License as published by
1653 + * the Free Software Foundation; version 2 of the License
1654 + *
1655 + * This program is distributed in the hope that it will be useful,
1656 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1657 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1658 + * GNU General Public License for more details.
1659 + *
1660 + * You should have received a copy of the GNU General Public License
1661 + * along with this program; if not, write to the Free Software
1662 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1663 + *
1664 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1665 + */
1666 +
1667 +#ifndef _RALINK_ESW_RT3052_H__
1668 +#define _RALINK_ESW_RT3052_H__
1669 +
1670 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1671 +
1672 +int __init rtesw_init(void);
1673 +void rtesw_exit(void);
1674 +
1675 +#else
1676 +
1677 +static inline int __init rtesw_init(void) { return 0; }
1678 +static inline void rtesw_exit(void) { }
1679 +
1680 +#endif
1681 +#endif
1682 Index: linux-3.10.18/drivers/net/ethernet/ralink/gsw_mt7620a.c
1683 ===================================================================
1684 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1685 +++ linux-3.10.18/drivers/net/ethernet/ralink/gsw_mt7620a.c 2013-11-21 15:20:28.676444348 +0100
1686 @@ -0,0 +1,566 @@
1687 +/*
1688 + * This program is free software; you can redistribute it and/or modify
1689 + * it under the terms of the GNU General Public License as published by
1690 + * the Free Software Foundation; version 2 of the License
1691 + *
1692 + * This program is distributed in the hope that it will be useful,
1693 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1694 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1695 + * GNU General Public License for more details.
1696 + *
1697 + * You should have received a copy of the GNU General Public License
1698 + * along with this program; if not, write to the Free Software
1699 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1700 + *
1701 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1702 + */
1703 +
1704 +#include <linux/module.h>
1705 +#include <linux/kernel.h>
1706 +#include <linux/types.h>
1707 +#include <linux/dma-mapping.h>
1708 +#include <linux/init.h>
1709 +#include <linux/skbuff.h>
1710 +#include <linux/etherdevice.h>
1711 +#include <linux/ethtool.h>
1712 +#include <linux/platform_device.h>
1713 +#include <linux/of_device.h>
1714 +#include <linux/clk.h>
1715 +#include <linux/of_net.h>
1716 +#include <linux/of_mdio.h>
1717 +#include <linux/of_irq.h>
1718 +#include <linux/of_address.h>
1719 +#include <linux/switch.h>
1720 +
1721 +#include <asm/mach-ralink/ralink_regs.h>
1722 +
1723 +#include "ralink_soc_eth.h"
1724 +
1725 +#include <linux/ioport.h>
1726 +#include <linux/switch.h>
1727 +#include <linux/mii.h>
1728 +
1729 +#include <ralink_regs.h>
1730 +#include <asm/mach-ralink/mt7620.h>
1731 +
1732 +#include "ralink_soc_eth.h"
1733 +#include "gsw_mt7620a.h"
1734 +#include "mt7530.h"
1735 +#include "mdio.h"
1736 +
1737 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
1738 +
1739 +#define MT7620A_GSW_REG_PIAC 0x7004
1740 +
1741 +#define GSW_NUM_VLANS 16
1742 +#define GSW_NUM_VIDS 4096
1743 +#define GSW_NUM_PORTS 7
1744 +#define GSW_PORT6 6
1745 +
1746 +#define GSW_MDIO_ACCESS BIT(31)
1747 +#define GSW_MDIO_READ BIT(19)
1748 +#define GSW_MDIO_WRITE BIT(18)
1749 +#define GSW_MDIO_START BIT(16)
1750 +#define GSW_MDIO_ADDR_SHIFT 20
1751 +#define GSW_MDIO_REG_SHIFT 25
1752 +
1753 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
1754 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1755 +#define GSW_REG_SMACCR0 0x3fE4
1756 +#define GSW_REG_SMACCR1 0x3fE8
1757 +#define GSW_REG_CKGCR 0x3ff0
1758 +
1759 +#define GSW_REG_IMR 0x7008
1760 +#define GSW_REG_ISR 0x700c
1761 +
1762 +#define SYSC_REG_CFG1 0x14
1763 +
1764 +#define PORT_IRQ_ST_CHG 0x7f
1765 +
1766 +#define SYSCFG1 0x14
1767 +
1768 +#define ESW_PHY_POLLING 0x7000
1769 +
1770 +#define PMCR_IPG BIT(18)
1771 +#define PMCR_MAC_MODE BIT(16)
1772 +#define PMCR_FORCE BIT(15)
1773 +#define PMCR_TX_EN BIT(14)
1774 +#define PMCR_RX_EN BIT(13)
1775 +#define PMCR_BACKOFF BIT(9)
1776 +#define PMCR_BACKPRES BIT(8)
1777 +#define PMCR_RX_FC BIT(5)
1778 +#define PMCR_TX_FC BIT(4)
1779 +#define PMCR_SPEED(_x) (_x << 2)
1780 +#define PMCR_DUPLEX BIT(1)
1781 +#define PMCR_LINK BIT(0)
1782 +
1783 +#define PHY_AN_EN BIT(31)
1784 +#define PHY_PRE_EN BIT(30)
1785 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
1786 +
1787 +enum {
1788 + /* Global attributes. */
1789 + GSW_ATTR_ENABLE_VLAN,
1790 + /* Port attributes. */
1791 + GSW_ATTR_PORT_UNTAG,
1792 +};
1793 +
1794 +enum {
1795 + PORT4_EPHY = 0,
1796 + PORT4_EXT,
1797 +};
1798 +
1799 +struct mt7620_gsw {
1800 + struct device *dev;
1801 + void __iomem *base;
1802 + int irq;
1803 + int port4;
1804 + long unsigned int autopoll;
1805 +};
1806 +
1807 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1808 +{
1809 + iowrite32(val, gsw->base + reg);
1810 +}
1811 +
1812 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1813 +{
1814 + return ioread32(gsw->base + reg);
1815 +}
1816 +
1817 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1818 +{
1819 + unsigned long t_start = jiffies;
1820 +
1821 + while (1) {
1822 + if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1823 + return 0;
1824 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1825 + break;
1826 + }
1827 + }
1828 +
1829 + printk(KERN_ERR "mdio: MDIO timeout\n");
1830 + return -1;
1831 +}
1832 +
1833 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1834 + u32 write_data)
1835 +{
1836 + if (mt7620_mii_busy_wait(gsw))
1837 + return -1;
1838 +
1839 + write_data &= 0xffff;
1840 +
1841 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1842 + (phy_register << GSW_MDIO_REG_SHIFT) |
1843 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1844 + MT7620A_GSW_REG_PIAC);
1845 +
1846 + if (mt7620_mii_busy_wait(gsw))
1847 + return -1;
1848 +
1849 + return 0;
1850 +}
1851 +
1852 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1853 +{
1854 + u32 d;
1855 +
1856 + if (mt7620_mii_busy_wait(gsw))
1857 + return 0xffff;
1858 +
1859 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1860 + (phy_reg << GSW_MDIO_REG_SHIFT) |
1861 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
1862 + MT7620A_GSW_REG_PIAC);
1863 +
1864 + if (mt7620_mii_busy_wait(gsw))
1865 + return 0xffff;
1866 +
1867 + d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1868 +
1869 + return d;
1870 +}
1871 +
1872 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1873 +{
1874 + struct fe_priv *priv = bus->priv;
1875 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1876 +
1877 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1878 +}
1879 +
1880 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1881 +{
1882 + struct fe_priv *priv = bus->priv;
1883 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1884 +
1885 + return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1886 +}
1887 +
1888 +static unsigned char *fe_speed_str(int speed)
1889 +{
1890 + switch (speed) {
1891 + case 2:
1892 + case SPEED_1000:
1893 + return "1000";
1894 + case 1:
1895 + case SPEED_100:
1896 + return "100";
1897 + case 0:
1898 + case SPEED_10:
1899 + return "10";
1900 + }
1901 +
1902 + return "? ";
1903 +}
1904 +
1905 +int mt7620a_has_carrier(struct fe_priv *priv)
1906 +{
1907 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1908 + int i;
1909 +
1910 + for (i = 0; i < GSW_PORT6; i++)
1911 + if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1912 + return 1;
1913 + return 0;
1914 +}
1915 +
1916 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1917 +{
1918 + if (!priv->phy)
1919 + return;
1920 +
1921 + if (mt7620a_has_carrier(priv))
1922 + netif_carrier_on(priv->netdev);
1923 + else
1924 + netif_carrier_off(priv->netdev);
1925 +}
1926 +
1927 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1928 +{
1929 + if (priv->link[port])
1930 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1931 + port, fe_speed_str(priv->phy->speed[port]),
1932 + (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1933 + else
1934 + netdev_info(priv->netdev, "port %d link down\n", port);
1935 + mt7620a_handle_carrier(priv);
1936 +}
1937 +
1938 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1939 +{
1940 + struct fe_priv *priv = (struct fe_priv *) _priv;
1941 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1942 + u32 status;
1943 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1944 +
1945 + status = gsw_r32(gsw, GSW_REG_ISR);
1946 + if (status & PORT_IRQ_ST_CHG)
1947 + for (i = 0; i <= max; i++) {
1948 + u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1949 + int link = status & 0x1;
1950 +
1951 + if (link != priv->link[i]) {
1952 + if (link)
1953 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1954 + i, fe_speed_str((status >> 2) & 3),
1955 + (status & 0x2) ? "Full" : "Half");
1956 + else
1957 + netdev_info(priv->netdev, "port %d link down\n", i);
1958 + }
1959 +
1960 + priv->link[i] = link;
1961 + }
1962 + mt7620a_handle_carrier(priv);
1963 +
1964 + gsw_w32(gsw, status, GSW_REG_ISR);
1965 +
1966 + return IRQ_HANDLED;
1967 +}
1968 +
1969 +static int mt7620_is_bga(void)
1970 +{
1971 + u32 bga = rt_sysc_r32(0x0c);
1972 +
1973 + return (bga >> 16) & 1;
1974 +}
1975 +
1976 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1977 +{
1978 + int phy;
1979 + int lsb = -1, msb = 0;
1980 +
1981 + for_each_set_bit(phy, &gsw->autopoll, 32) {
1982 + if (lsb < 0)
1983 + lsb = phy;
1984 + msb = phy;
1985 + }
1986 +
1987 + gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1988 +}
1989 +
1990 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
1991 +{
1992 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1993 + const __be32 *_id = of_get_property(np, "reg", NULL);
1994 + int phy_mode, size, id;
1995 + int shift = 12;
1996 + u32 val, mask = 0;
1997 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
1998 +
1999 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2000 + if (_id)
2001 + pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2002 + else
2003 + pr_err("%s: invalid port id\n", np->name);
2004 + return;
2005 + }
2006 +
2007 + id = be32_to_cpu(*_id);
2008 +
2009 + if (id == 4)
2010 + shift = 14;
2011 +
2012 + priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2013 + if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2014 + pr_err("%s: invalid fixed link property\n", np->name);
2015 + priv->phy->phy_fixed[id] = NULL;
2016 + return;
2017 + }
2018 +
2019 + phy_mode = of_get_phy_mode(np);
2020 + switch (phy_mode) {
2021 + case PHY_INTERFACE_MODE_RGMII:
2022 + mask = 0;
2023 + break;
2024 + case PHY_INTERFACE_MODE_MII:
2025 + mask = 1;
2026 + break;
2027 + case PHY_INTERFACE_MODE_RMII:
2028 + mask = 2;
2029 + break;
2030 + default:
2031 + dev_err(priv->device, "port %d - invalid phy mode\n", id);
2032 + return;
2033 + }
2034 +
2035 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2036 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2037 + return;
2038 +
2039 + val = rt_sysc_r32(SYSCFG1);
2040 + val &= ~(3 << shift);
2041 + val |= mask << shift;
2042 + rt_sysc_w32(val, SYSCFG1);
2043 +
2044 + if (priv->phy->phy_fixed[id]) {
2045 + const __be32 *link = priv->phy->phy_fixed[id];
2046 + int tx_fc, rx_fc;
2047 + u32 val = 0;
2048 +
2049 + priv->phy->speed[id] = be32_to_cpup(link++);
2050 + tx_fc = be32_to_cpup(link++);
2051 + rx_fc = be32_to_cpup(link++);
2052 + priv->phy->duplex[id] = be32_to_cpup(link++);
2053 + priv->link[id] = 1;
2054 +
2055 + switch (priv->phy->speed[id]) {
2056 + case SPEED_10:
2057 + val = 0;
2058 + break;
2059 + case SPEED_100:
2060 + val = 1;
2061 + break;
2062 + case SPEED_1000:
2063 + val = 2;
2064 + break;
2065 + default:
2066 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2067 + priv->phy->phy_fixed[id] = 0;
2068 + return;
2069 + }
2070 + val = PMCR_SPEED(val);
2071 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2072 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2073 + if (tx_fc)
2074 + val |= PMCR_TX_FC;
2075 + if (rx_fc)
2076 + val |= PMCR_RX_FC;
2077 + if (priv->phy->duplex[id])
2078 + val |= PMCR_DUPLEX;
2079 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2080 + dev_info(priv->device, "using fixed link parameters\n");
2081 + return;
2082 + }
2083 +
2084 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2085 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2086 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
2087 +
2088 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2089 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2090 + gsw->autopoll |= BIT(id);
2091 + gsw_auto_poll(gsw);
2092 + return;
2093 + }
2094 +}
2095 +
2096 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2097 +{
2098 + u32 is_BGA = mt7620_is_bga();
2099 +
2100 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2101 + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2102 +
2103 + /*correct PHY setting L3.0 BGA*/
2104 + _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2105 +
2106 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
2107 + if (is_BGA)
2108 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
2109 + else
2110 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
2111 +
2112 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2113 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
2114 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
2115 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
2116 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
2117 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
2118 +
2119 + _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2120 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
2121 +
2122 + _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2123 + if (is_BGA) {
2124 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
2125 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
2126 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2127 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2128 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2129 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2130 + } else {
2131 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
2132 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2133 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2134 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2135 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2136 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2137 + }
2138 + _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2139 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2140 +
2141 + _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2142 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
2143 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
2144 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
2145 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
2146 +
2147 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2148 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2149 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2150 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2151 + _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2152 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
2153 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
2154 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
2155 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2156 +
2157 + /* CPU Port6 Force Link 1G, FC ON */
2158 + gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2159 + /* Set Port6 CPU Port */
2160 + gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2161 +
2162 + /* setup port 4 */
2163 + if (gsw->port4 == PORT4_EPHY) {
2164 + u32 val = rt_sysc_r32(SYSCFG1);
2165 + val |= 3 << 14;
2166 + rt_sysc_w32(val, SYSCFG1);
2167 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
2168 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2169 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
2170 + pr_info("gsw: setting port4 to ephy mode\n");
2171 + }
2172 +}
2173 +
2174 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2175 +{
2176 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2177 + unsigned long flags;
2178 +
2179 + spin_lock_irqsave(&priv->page_lock, flags);
2180 + gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2181 + gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2182 + GSW_REG_SMACCR0);
2183 + spin_unlock_irqrestore(&priv->page_lock, flags);
2184 +}
2185 +
2186 +static struct of_device_id gsw_match[] = {
2187 + { .compatible = "ralink,mt7620a-gsw" },
2188 + {}
2189 +};
2190 +
2191 +int mt7620_gsw_config(struct fe_priv *priv)
2192 +{
2193 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2194 +
2195 + /* is the mt7530 internal or external */
2196 + if ((_mt7620_mii_read(gsw, 0x1f, 2) == 1) && (_mt7620_mii_read(gsw, 0x1f, 3) == 0xbeef))
2197 + mt7530_probe(priv->device, NULL, priv->mii_bus);
2198 + else
2199 + mt7530_probe(priv->device, gsw->base, NULL);
2200 +
2201 + return 0;
2202 +}
2203 +
2204 +int mt7620_gsw_probe(struct fe_priv *priv)
2205 +{
2206 + struct mt7620_gsw *gsw;
2207 + struct device_node *np;
2208 + const char *port4 = NULL;
2209 +
2210 + np = of_find_matching_node(NULL, gsw_match);
2211 + if (!np) {
2212 + dev_err(priv->device, "no gsw node found\n");
2213 + return -EINVAL;
2214 + }
2215 + np = of_node_get(np);
2216 +
2217 + gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2218 + if (!gsw) {
2219 + dev_err(priv->device, "no gsw memory for private data\n");
2220 + return -ENOMEM;
2221 + }
2222 +
2223 + gsw->irq = irq_of_parse_and_map(np, 0);
2224 + if (!gsw->irq) {
2225 + dev_err(priv->device, "no gsw irq resource found\n");
2226 + return -ENOMEM;
2227 + }
2228 +
2229 + gsw->base = of_iomap(np, 0);
2230 + if (!gsw->base) {
2231 + dev_err(priv->device, "gsw ioremap failed\n");
2232 + return -ENOMEM;
2233 + }
2234 +
2235 + gsw->dev = priv->device;
2236 + priv->soc->swpriv = gsw;
2237 +
2238 + of_property_read_string(np, "ralink,port4", &port4);
2239 + if (port4 && !strcmp(port4, "ephy"))
2240 + gsw->port4 = PORT4_EPHY;
2241 + else if (port4 && !strcmp(port4, "gmac"))
2242 + gsw->port4 = PORT4_EXT;
2243 + else
2244 + WARN_ON(port4);
2245 +
2246 + gsw_hw_init(gsw);
2247 +
2248 + gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2249 + request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2250 +
2251 + return 0;
2252 +}
2253 Index: linux-3.10.18/drivers/net/ethernet/ralink/gsw_mt7620a.h
2254 ===================================================================
2255 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2256 +++ linux-3.10.18/drivers/net/ethernet/ralink/gsw_mt7620a.h 2013-11-21 15:20:28.676444348 +0100
2257 @@ -0,0 +1,30 @@
2258 +/*
2259 + * This program is free software; you can redistribute it and/or modify
2260 + * it under the terms of the GNU General Public License as published by
2261 + * the Free Software Foundation; version 2 of the License
2262 + *
2263 + * This program is distributed in the hope that it will be useful,
2264 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2265 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2266 + * GNU General Public License for more details.
2267 + *
2268 + * You should have received a copy of the GNU General Public License
2269 + * along with this program; if not, write to the Free Software
2270 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2271 + *
2272 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2273 + */
2274 +
2275 +#ifndef _RALINK_GSW_MT7620_H__
2276 +#define _RALINK_GSW_MT7620_H__
2277 +
2278 +extern int mt7620_gsw_config(struct fe_priv *priv);
2279 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2280 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2281 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2282 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2283 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2284 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2285 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2286 +
2287 +#endif
2288 Index: linux-3.10.18/drivers/net/ethernet/ralink/mdio.c
2289 ===================================================================
2290 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2291 +++ linux-3.10.18/drivers/net/ethernet/ralink/mdio.c 2013-11-21 15:20:28.680444349 +0100
2292 @@ -0,0 +1,244 @@
2293 +/*
2294 + * This program is free software; you can redistribute it and/or modify
2295 + * it under the terms of the GNU General Public License as published by
2296 + * the Free Software Foundation; version 2 of the License
2297 + *
2298 + * This program is distributed in the hope that it will be useful,
2299 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2300 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2301 + * GNU General Public License for more details.
2302 + *
2303 + * You should have received a copy of the GNU General Public License
2304 + * along with this program; if not, write to the Free Software
2305 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2306 + *
2307 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2308 + */
2309 +
2310 +#include <linux/module.h>
2311 +#include <linux/kernel.h>
2312 +#include <linux/types.h>
2313 +#include <linux/dma-mapping.h>
2314 +#include <linux/init.h>
2315 +#include <linux/skbuff.h>
2316 +#include <linux/etherdevice.h>
2317 +#include <linux/ethtool.h>
2318 +#include <linux/platform_device.h>
2319 +#include <linux/phy.h>
2320 +#include <linux/of_device.h>
2321 +#include <linux/clk.h>
2322 +#include <linux/of_net.h>
2323 +#include <linux/of_mdio.h>
2324 +
2325 +#include "ralink_soc_eth.h"
2326 +#include "mdio.h"
2327 +
2328 +static int fe_mdio_reset(struct mii_bus *bus)
2329 +{
2330 + /* TODO */
2331 + return 0;
2332 +}
2333 +
2334 +static void fe_phy_link_adjust(struct net_device *dev)
2335 +{
2336 + struct fe_priv *priv = netdev_priv(dev);
2337 + unsigned long flags;
2338 + int i;
2339 +
2340 + spin_lock_irqsave(&priv->phy->lock, flags);
2341 + for (i = 0; i < 8; i++) {
2342 + if (priv->phy->phy_node[i]) {
2343 + struct phy_device *phydev = priv->phy->phy[i];
2344 + int status_change = 0;
2345 +
2346 + if (phydev->link)
2347 + if (priv->phy->duplex[i] != phydev->duplex ||
2348 + priv->phy->speed[i] != phydev->speed)
2349 + status_change = 1;
2350 +
2351 + if (phydev->link != priv->link[i])
2352 + status_change = 1;
2353 +
2354 + switch (phydev->speed) {
2355 + case SPEED_1000:
2356 + case SPEED_100:
2357 + case SPEED_10:
2358 + priv->link[i] = phydev->link;
2359 + priv->phy->duplex[i] = phydev->duplex;
2360 + priv->phy->speed[i] = phydev->speed;
2361 +
2362 + if (status_change && priv->soc->mdio_adjust_link)
2363 + priv->soc->mdio_adjust_link(priv, i);
2364 + break;
2365 + }
2366 + }
2367 + }
2368 +}
2369 +
2370 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2371 +{
2372 + const __be32 *_port = NULL;
2373 + struct phy_device *phydev;
2374 + int phy_mode, port;
2375 +
2376 + _port = of_get_property(phy_node, "reg", NULL);
2377 +
2378 + if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2379 + pr_err("%s: invalid port id\n", phy_node->name);
2380 + return -EINVAL;
2381 + }
2382 + port = be32_to_cpu(*_port);
2383 + phy_mode = of_get_phy_mode(phy_node);
2384 + if (phy_mode < 0) {
2385 + dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2386 + priv->phy->phy_node[port] = NULL;
2387 + return -EINVAL;
2388 + }
2389 +
2390 + phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2391 + 0, phy_mode);
2392 + if (IS_ERR(phydev)) {
2393 + dev_err(priv->device, "could not connect to PHY\n");
2394 + priv->phy->phy_node[port] = NULL;
2395 + return PTR_ERR(phydev);
2396 + }
2397 +
2398 + phydev->supported &= PHY_GBIT_FEATURES;
2399 + phydev->advertising = phydev->supported;
2400 + phydev->no_auto_carrier_off = 1;
2401 +
2402 + dev_info(priv->device,
2403 + "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2404 + port, dev_name(&phydev->dev), phydev->phy_id,
2405 + phydev->drv->name);
2406 +
2407 + priv->phy->phy[port] = phydev;
2408 + priv->link[port] = 0;
2409 +
2410 + return 0;
2411 +}
2412 +
2413 +static int fe_phy_connect(struct fe_priv *priv)
2414 +{
2415 + return 0;
2416 +}
2417 +
2418 +static void fe_phy_disconnect(struct fe_priv *priv)
2419 +{
2420 + unsigned long flags;
2421 + int i;
2422 +
2423 + for (i = 0; i < 8; i++)
2424 + if (priv->phy->phy_fixed[i]) {
2425 + spin_lock_irqsave(&priv->phy->lock, flags);
2426 + priv->link[i] = 0;
2427 + if (priv->soc->mdio_adjust_link)
2428 + priv->soc->mdio_adjust_link(priv, i);
2429 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2430 + } else if (priv->phy->phy[i]) {
2431 + phy_disconnect(priv->phy->phy[i]);
2432 + }
2433 +}
2434 +
2435 +static void fe_phy_start(struct fe_priv *priv)
2436 +{
2437 + unsigned long flags;
2438 + int i;
2439 +
2440 + for (i = 0; i < 8; i++) {
2441 + if (priv->phy->phy_fixed[i]) {
2442 + spin_lock_irqsave(&priv->phy->lock, flags);
2443 + priv->link[i] = 1;
2444 + if (priv->soc->mdio_adjust_link)
2445 + priv->soc->mdio_adjust_link(priv, i);
2446 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2447 + } else if (priv->phy->phy[i]) {
2448 + phy_start(priv->phy->phy[i]);
2449 + }
2450 + }
2451 +}
2452 +
2453 +static void fe_phy_stop(struct fe_priv *priv)
2454 +{
2455 + unsigned long flags;
2456 + int i;
2457 +
2458 + for (i = 0; i < 8; i++)
2459 + if (priv->phy->phy_fixed[i]) {
2460 + spin_lock_irqsave(&priv->phy->lock, flags);
2461 + priv->link[i] = 0;
2462 + if (priv->soc->mdio_adjust_link)
2463 + priv->soc->mdio_adjust_link(priv, i);
2464 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2465 + } else if (priv->phy->phy[i]) {
2466 + phy_stop(priv->phy->phy[i]);
2467 + }
2468 +}
2469 +
2470 +static struct fe_phy phy_ralink = {
2471 + .connect = fe_phy_connect,
2472 + .disconnect = fe_phy_disconnect,
2473 + .start = fe_phy_start,
2474 + .stop = fe_phy_stop,
2475 +};
2476 +
2477 +int fe_mdio_init(struct fe_priv *priv)
2478 +{
2479 + struct device_node *mii_np;
2480 + int err;
2481 +
2482 + if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2483 + return 0;
2484 +
2485 + spin_lock_init(&phy_ralink.lock);
2486 + priv->phy = &phy_ralink;
2487 +
2488 + mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2489 + if (!mii_np) {
2490 + dev_err(priv->device, "no %s child node found", "mdio-bus");
2491 + return -ENODEV;
2492 + }
2493 +
2494 + if (!of_device_is_available(mii_np)) {
2495 + err = 0;
2496 + goto err_put_node;
2497 + }
2498 +
2499 + priv->mii_bus = mdiobus_alloc();
2500 + if (priv->mii_bus == NULL) {
2501 + err = -ENOMEM;
2502 + goto err_put_node;
2503 + }
2504 +
2505 + priv->mii_bus->name = "mdio";
2506 + priv->mii_bus->read = priv->soc->mdio_read;
2507 + priv->mii_bus->write = priv->soc->mdio_write;
2508 + priv->mii_bus->reset = fe_mdio_reset;
2509 + priv->mii_bus->irq = priv->mii_irq;
2510 + priv->mii_bus->priv = priv;
2511 + priv->mii_bus->parent = priv->device;
2512 +
2513 + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2514 + err = of_mdiobus_register(priv->mii_bus, mii_np);
2515 + if (err)
2516 + goto err_free_bus;
2517 +
2518 + return 0;
2519 +
2520 +err_free_bus:
2521 + kfree(priv->mii_bus);
2522 +err_put_node:
2523 + of_node_put(mii_np);
2524 + priv->mii_bus = NULL;
2525 + return err;
2526 +}
2527 +
2528 +void fe_mdio_cleanup(struct fe_priv *priv)
2529 +{
2530 + if (!priv->mii_bus)
2531 + return;
2532 +
2533 + mdiobus_unregister(priv->mii_bus);
2534 + of_node_put(priv->mii_bus->dev.of_node);
2535 + kfree(priv->mii_bus);
2536 +}
2537 Index: linux-3.10.18/drivers/net/ethernet/ralink/mdio.h
2538 ===================================================================
2539 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2540 +++ linux-3.10.18/drivers/net/ethernet/ralink/mdio.h 2013-11-21 15:20:28.680444349 +0100
2541 @@ -0,0 +1,29 @@
2542 +/*
2543 + * This program is free software; you can redistribute it and/or modify
2544 + * it under the terms of the GNU General Public License as published by
2545 + * the Free Software Foundation; version 2 of the License
2546 + *
2547 + * This program is distributed in the hope that it will be useful,
2548 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2549 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2550 + * GNU General Public License for more details.
2551 + *
2552 + * You should have received a copy of the GNU General Public License
2553 + * along with this program; if not, write to the Free Software
2554 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2555 + *
2556 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2557 + */
2558 +
2559 +#ifndef _RALINK_MDIO_H__
2560 +#define _RALINK_MDIO_H__
2561 +
2562 +#ifdef CONFIG_NET_RALINK_MDIO
2563 +extern int fe_mdio_init(struct fe_priv *priv);
2564 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2565 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2566 +#else
2567 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2568 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2569 +#endif
2570 +#endif
2571 Index: linux-3.10.18/drivers/net/ethernet/ralink/mdio_rt2880.c
2572 ===================================================================
2573 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2574 +++ linux-3.10.18/drivers/net/ethernet/ralink/mdio_rt2880.c 2013-11-21 15:20:28.680444349 +0100
2575 @@ -0,0 +1,232 @@
2576 +/*
2577 + * This program is free software; you can redistribute it and/or modify
2578 + * it under the terms of the GNU General Public License as published by
2579 + * the Free Software Foundation; version 2 of the License
2580 + *
2581 + * This program is distributed in the hope that it will be useful,
2582 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2583 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2584 + * GNU General Public License for more details.
2585 + *
2586 + * You should have received a copy of the GNU General Public License
2587 + * along with this program; if not, write to the Free Software
2588 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2589 + *
2590 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2591 + */
2592 +
2593 +#include <linux/module.h>
2594 +#include <linux/kernel.h>
2595 +#include <linux/types.h>
2596 +#include <linux/dma-mapping.h>
2597 +#include <linux/init.h>
2598 +#include <linux/skbuff.h>
2599 +#include <linux/etherdevice.h>
2600 +#include <linux/ethtool.h>
2601 +#include <linux/platform_device.h>
2602 +#include <linux/phy.h>
2603 +#include <linux/of_device.h>
2604 +#include <linux/clk.h>
2605 +#include <linux/of_net.h>
2606 +#include <linux/of_mdio.h>
2607 +
2608 +#include "ralink_soc_eth.h"
2609 +#include "mdio_rt2880.h"
2610 +#include "mdio.h"
2611 +
2612 +#define FE_MDIO_RETRY 1000
2613 +
2614 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2615 +{
2616 + switch (priv->phy->speed[0]) {
2617 + case SPEED_1000:
2618 + return "1000";
2619 + case SPEED_100:
2620 + return "100";
2621 + case SPEED_10:
2622 + return "10";
2623 + }
2624 +
2625 + return "?";
2626 +}
2627 +
2628 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2629 +{
2630 + u32 mdio_cfg;
2631 +
2632 + if (!priv->link[0]) {
2633 + netif_carrier_off(priv->netdev);
2634 + netdev_info(priv->netdev, "link down\n");
2635 + return;
2636 + }
2637 +
2638 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2639 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
2640 + FE_MDIO_CFG_GP1_FRC_EN;
2641 +
2642 + if (priv->phy->duplex[0] == DUPLEX_FULL)
2643 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2644 +
2645 + if (priv->phy->tx_fc[0])
2646 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2647 +
2648 + if (priv->phy->rx_fc[0])
2649 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2650 +
2651 + switch (priv->phy->speed[0]) {
2652 + case SPEED_10:
2653 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2654 + break;
2655 + case SPEED_100:
2656 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2657 + break;
2658 + case SPEED_1000:
2659 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2660 + break;
2661 + default:
2662 + BUG();
2663 + }
2664 +
2665 + fe_w32(mdio_cfg, FE_MDIO_CFG);
2666 +
2667 + netif_carrier_on(priv->netdev);
2668 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2669 + rt2880_speed_str(priv),
2670 + (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2671 +}
2672 +
2673 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2674 +{
2675 + int retries;
2676 +
2677 + retries = FE_MDIO_RETRY;
2678 + while (1) {
2679 + u32 t;
2680 +
2681 + t = fe_r32(FE_MDIO_ACCESS);
2682 + if ((t & (0x1 << 31)) == 0)
2683 + return 0;
2684 +
2685 + if (retries-- == 0)
2686 + break;
2687 +
2688 + udelay(1);
2689 + }
2690 +
2691 + dev_err(priv->device, "MDIO operation timed out\n");
2692 + return -ETIMEDOUT;
2693 +}
2694 +
2695 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2696 +{
2697 + struct fe_priv *priv = bus->priv;
2698 + int err;
2699 + u32 t;
2700 +
2701 + err = rt2880_mdio_wait_ready(priv);
2702 + if (err)
2703 + return 0xffff;
2704 +
2705 + t = (phy_addr << 24) | (phy_reg << 16);
2706 + fe_w32(t, FE_MDIO_ACCESS);
2707 + t |= (1 << 31);
2708 + fe_w32(t, FE_MDIO_ACCESS);
2709 +
2710 + err = rt2880_mdio_wait_ready(priv);
2711 + if (err)
2712 + return 0xffff;
2713 +
2714 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2715 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2716 +
2717 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2718 +}
2719 +
2720 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2721 +{
2722 + struct fe_priv *priv = bus->priv;
2723 + int err;
2724 + u32 t;
2725 +
2726 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2727 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2728 +
2729 + err = rt2880_mdio_wait_ready(priv);
2730 + if (err)
2731 + return err;
2732 +
2733 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2734 + fe_w32(t, FE_MDIO_ACCESS);
2735 + t |= (1 << 31);
2736 + fe_w32(t, FE_MDIO_ACCESS);
2737 +
2738 + return rt2880_mdio_wait_ready(priv);
2739 +}
2740 +
2741 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2742 +{
2743 + const __be32 *id = of_get_property(np, "reg", NULL);
2744 + const __be32 *link;
2745 + int size;
2746 + int phy_mode;
2747 +
2748 + if (!id || (be32_to_cpu(*id) != 0)) {
2749 + pr_err("%s: invalid port id\n", np->name);
2750 + return;
2751 + }
2752 +
2753 + priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2754 + if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2755 + pr_err("%s: invalid fixed link property\n", np->name);
2756 + priv->phy->phy_fixed[0] = NULL;
2757 + return;
2758 + }
2759 +
2760 + phy_mode = of_get_phy_mode(np);
2761 + switch (phy_mode) {
2762 + case PHY_INTERFACE_MODE_RGMII:
2763 + break;
2764 + case PHY_INTERFACE_MODE_MII:
2765 + break;
2766 + case PHY_INTERFACE_MODE_RMII:
2767 + break;
2768 + default:
2769 + if (!priv->phy->phy_fixed[0])
2770 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2771 + break;
2772 + }
2773 +
2774 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2775 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2776 + return;
2777 +
2778 + if (priv->phy->phy_fixed[0]) {
2779 + link = priv->phy->phy_fixed[0];
2780 + priv->phy->speed[0] = be32_to_cpup(link++);
2781 + priv->phy->duplex[0] = be32_to_cpup(link++);
2782 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
2783 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
2784 +
2785 + priv->link[0] = 1;
2786 + switch (priv->phy->speed[0]) {
2787 + case SPEED_10:
2788 + break;
2789 + case SPEED_100:
2790 + break;
2791 + case SPEED_1000:
2792 + break;
2793 + default:
2794 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2795 + priv->phy->phy_fixed[0] = 0;
2796 + return;
2797 + }
2798 + dev_info(priv->device, "using fixed link parameters\n");
2799 + rt2880_mdio_link_adjust(priv, 0);
2800 + return;
2801 + }
2802 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2803 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2804 + }
2805 +
2806 + return;
2807 +}
2808 Index: linux-3.10.18/drivers/net/ethernet/ralink/mdio_rt2880.h
2809 ===================================================================
2810 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2811 +++ linux-3.10.18/drivers/net/ethernet/ralink/mdio_rt2880.h 2013-11-21 15:20:28.680444349 +0100
2812 @@ -0,0 +1,26 @@
2813 +/*
2814 + * This program is free software; you can redistribute it and/or modify
2815 + * it under the terms of the GNU General Public License as published by
2816 + * the Free Software Foundation; version 2 of the License
2817 + *
2818 + * This program is distributed in the hope that it will be useful,
2819 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2820 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2821 + * GNU General Public License for more details.
2822 + *
2823 + * You should have received a copy of the GNU General Public License
2824 + * along with this program; if not, write to the Free Software
2825 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2826 + *
2827 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2828 + */
2829 +
2830 +#ifndef _RALINK_MDIO_RT2880_H__
2831 +#define _RALINK_MDIO_RT2880_H__
2832 +
2833 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2834 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2835 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2836 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2837 +
2838 +#endif
2839 Index: linux-3.10.18/drivers/net/ethernet/ralink/ralink_soc_eth.c
2840 ===================================================================
2841 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2842 +++ linux-3.10.18/drivers/net/ethernet/ralink/ralink_soc_eth.c 2013-11-21 17:11:49.492603543 +0100
2843 @@ -0,0 +1,769 @@
2844 +/*
2845 + * This program is free software; you can redistribute it and/or modify
2846 + * it under the terms of the GNU General Public License as published by
2847 + * the Free Software Foundation; version 2 of the License
2848 + *
2849 + * This program is distributed in the hope that it will be useful,
2850 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2851 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2852 + * GNU General Public License for more details.
2853 + *
2854 + * You should have received a copy of the GNU General Public License
2855 + * along with this program; if not, write to the Free Software
2856 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2857 + *
2858 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2859 + */
2860 +
2861 +#include <linux/module.h>
2862 +#include <linux/kernel.h>
2863 +#include <linux/types.h>
2864 +#include <linux/dma-mapping.h>
2865 +#include <linux/init.h>
2866 +#include <linux/skbuff.h>
2867 +#include <linux/etherdevice.h>
2868 +#include <linux/ethtool.h>
2869 +#include <linux/platform_device.h>
2870 +#include <linux/of_device.h>
2871 +#include <linux/clk.h>
2872 +#include <linux/of_net.h>
2873 +#include <linux/of_mdio.h>
2874 +#include <linux/if_vlan.h>
2875 +#include <linux/reset.h>
2876 +
2877 +#include <asm/mach-ralink/ralink_regs.h>
2878 +
2879 +#include "ralink_soc_eth.h"
2880 +#include "esw_rt3052.h"
2881 +#include "mdio.h"
2882 +
2883 +#define TX_TIMEOUT (20 * HZ / 100)
2884 +#define MAX_RX_LENGTH 1536
2885 +
2886 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
2887 + [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
2888 + [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
2889 + [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
2890 + [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
2891 + [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
2892 + [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
2893 + [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
2894 + [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
2895 + [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
2896 + [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
2897 + [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
2898 +};
2899 +
2900 +static const u32 *fe_reg_table = fe_reg_table_default;
2901 +
2902 +static void __iomem *fe_base = 0;
2903 +
2904 +void fe_w32(u32 val, unsigned reg)
2905 +{
2906 + __raw_writel(val, fe_base + reg);
2907 +}
2908 +
2909 +u32 fe_r32(unsigned reg)
2910 +{
2911 + return __raw_readl(fe_base + reg);
2912 +}
2913 +
2914 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
2915 +{
2916 + fe_w32(val, fe_reg_table[reg]);
2917 +}
2918 +
2919 +static inline u32 fe_reg_r32(enum fe_reg reg)
2920 +{
2921 + return fe_r32(fe_reg_table[reg]);
2922 +}
2923 +
2924 +static inline void fe_int_disable(u32 mask)
2925 +{
2926 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
2927 + FE_REG_FE_INT_ENABLE);
2928 + /* flush write */
2929 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
2930 +}
2931 +
2932 +static inline void fe_int_enable(u32 mask)
2933 +{
2934 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
2935 + FE_REG_FE_INT_ENABLE);
2936 + /* flush write */
2937 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
2938 +}
2939 +
2940 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
2941 +{
2942 + unsigned long flags;
2943 +
2944 + spin_lock_irqsave(&priv->page_lock, flags);
2945 + fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
2946 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2947 + FE_GDMA1_MAC_ADRL);
2948 + spin_unlock_irqrestore(&priv->page_lock, flags);
2949 +}
2950 +
2951 +static int fe_set_mac_address(struct net_device *dev, void *p)
2952 +{
2953 + int ret = eth_mac_addr(dev, p);
2954 +
2955 + if (!ret) {
2956 + struct fe_priv *priv = netdev_priv(dev);
2957 +
2958 + if (priv->soc->set_mac)
2959 + priv->soc->set_mac(priv, dev->dev_addr);
2960 + else
2961 + fe_hw_set_macaddr(priv, p);
2962 + }
2963 +
2964 + return ret;
2965 +}
2966 +
2967 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
2968 +{
2969 + struct sk_buff *skb;
2970 +
2971 + skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
2972 + if (!skb)
2973 + return NULL;
2974 +
2975 + skb_reserve(skb, NET_IP_ALIGN);
2976 +
2977 + return skb;
2978 +}
2979 +
2980 +static int fe_alloc_rx(struct fe_priv *priv)
2981 +{
2982 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
2983 + int i;
2984 +
2985 + priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
2986 + &priv->rx_phys, GFP_ATOMIC);
2987 + if (!priv->rx_dma)
2988 + return -ENOMEM;
2989 +
2990 + memset(priv->rx_dma, 0, size);
2991 +
2992 + for (i = 0; i < NUM_DMA_DESC; i++) {
2993 + priv->rx_skb[i] = fe_alloc_skb(priv);
2994 + if (!priv->rx_skb[i])
2995 + return -ENOMEM;
2996 + }
2997 +
2998 + for (i = 0; i < NUM_DMA_DESC; i++) {
2999 + dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
3000 + priv->rx_skb[i]->data,
3001 + MAX_RX_LENGTH,
3002 + DMA_FROM_DEVICE);
3003 + priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3004 +
3005 + if (priv->soc->rx_dma)
3006 + priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
3007 + else
3008 + priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3009 + }
3010 + wmb();
3011 +
3012 + fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3013 + fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3014 + fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3015 + fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3016 +
3017 + return 0;
3018 +}
3019 +
3020 +static int fe_alloc_tx(struct fe_priv *priv)
3021 +{
3022 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3023 + int i;
3024 +
3025 + priv->tx_free_idx = 0;
3026 +
3027 + priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
3028 + &priv->tx_phys, GFP_ATOMIC);
3029 + if (!priv->tx_dma)
3030 + return -ENOMEM;
3031 +
3032 + memset(priv->tx_dma, 0, size);
3033 +
3034 + for (i = 0; i < NUM_DMA_DESC; i++) {
3035 + if (priv->soc->tx_dma) {
3036 + priv->soc->tx_dma(priv, i, NULL);
3037 + continue;
3038 + }
3039 +
3040 + priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3041 + priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3042 + }
3043 +
3044 + fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3045 + fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3046 + fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3047 + fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3048 +
3049 + return 0;
3050 +}
3051 +
3052 +static void fe_free_dma(struct fe_priv *priv)
3053 +{
3054 + int i;
3055 +
3056 + for (i = 0; i < NUM_DMA_DESC; i++) {
3057 + if (priv->rx_skb[i]) {
3058 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3059 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3060 + dev_kfree_skb_any(priv->rx_skb[i]);
3061 + priv->rx_skb[i] = NULL;
3062 + }
3063 +
3064 + if (priv->tx_skb[i]) {
3065 + dev_kfree_skb_any(priv->tx_skb[i]);
3066 + priv->tx_skb[i] = NULL;
3067 + }
3068 + }
3069 +
3070 + if (priv->rx_dma) {
3071 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3072 + dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3073 + priv->rx_phys);
3074 + }
3075 +
3076 + if (priv->tx_dma) {
3077 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3078 + dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3079 + priv->tx_phys);
3080 + }
3081 +
3082 + netdev_reset_queue(priv->netdev);
3083 +}
3084 +
3085 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3086 +{
3087 + struct fe_priv *priv = netdev_priv(dev);
3088 + dma_addr_t mapped_addr;
3089 + u32 tx_next;
3090 + u32 tx;
3091 +
3092 + if (priv->soc->min_pkt_len) {
3093 + if (skb->len < priv->soc->min_pkt_len) {
3094 + if (skb_padto(skb, priv->soc->min_pkt_len)) {
3095 + printk(KERN_ERR
3096 + "fe_eth: skb_padto failed\n");
3097 + kfree_skb(skb);
3098 + return 0;
3099 + }
3100 + skb_put(skb, priv->soc->min_pkt_len - skb->len);
3101 + }
3102 + }
3103 +
3104 + dev->trans_start = jiffies;
3105 + mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3106 + skb->len, DMA_TO_DEVICE);
3107 +
3108 + spin_lock(&priv->page_lock);
3109 +
3110 + tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3111 + tx_next = (tx + 1) % NUM_DMA_DESC;
3112 +
3113 + if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3114 + !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3115 + !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3116 + {
3117 + spin_unlock(&priv->page_lock);
3118 + dev->stats.tx_dropped++;
3119 + kfree_skb(skb);
3120 +
3121 + return NETDEV_TX_OK;
3122 + }
3123 +
3124 + priv->tx_skb[tx] = skb;
3125 + priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3126 + wmb();
3127 +
3128 + priv->tx_dma[tx].txd4 &= ~0x80;
3129 + if (priv->soc->tx_dma)
3130 + priv->soc->tx_dma(priv, tx, skb);
3131 + else
3132 + priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3133 +
3134 + if (skb->ip_summed == CHECKSUM_PARTIAL)
3135 + priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3136 + else
3137 + priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3138 +
3139 + dev->stats.tx_packets++;
3140 + dev->stats.tx_bytes += skb->len;
3141 +
3142 + fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3143 + netdev_sent_queue(dev, skb->len);
3144 +
3145 + spin_unlock(&priv->page_lock);
3146 +
3147 + return NETDEV_TX_OK;
3148 +}
3149 +
3150 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3151 +{
3152 + struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3153 + int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3154 + int complete = 0;
3155 + int rx = 0;
3156 +
3157 + while ((rx < budget) && !complete) {
3158 + idx = (idx + 1) % NUM_DMA_DESC;
3159 +
3160 + if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3161 + struct sk_buff *new_skb = fe_alloc_skb(priv);
3162 +
3163 + if (new_skb) {
3164 + int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3165 + dma_addr_t dma_addr;
3166 +
3167 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3168 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3169 +
3170 + skb_put(priv->rx_skb[idx], pktlen);
3171 + priv->rx_skb[idx]->dev = priv->netdev;
3172 + priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3173 + if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3174 + priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3175 + else
3176 + priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3177 + priv->netdev->stats.rx_packets++;
3178 + priv->netdev->stats.rx_bytes += pktlen;
3179 +
3180 +#ifdef CONFIG_INET_LRO
3181 + if (priv->soc->get_skb_header && priv->rx_skb[idx]->ip_summed == CHECKSUM_UNNECESSARY)
3182 + lro_receive_skb(&priv->lro_mgr, priv->rx_skb[idx], NULL);
3183 + else
3184 +#endif
3185 + netif_receive_skb(priv->rx_skb[idx]);
3186 +
3187 + priv->rx_skb[idx] = new_skb;
3188 +
3189 + dma_addr = dma_map_single(&priv->netdev->dev,
3190 + new_skb->data,
3191 + MAX_RX_LENGTH,
3192 + DMA_FROM_DEVICE);
3193 + priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3194 + wmb();
3195 + } else {
3196 + priv->netdev->stats.rx_dropped++;
3197 + }
3198 +
3199 + if (priv->soc->rx_dma)
3200 + priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3201 + else
3202 + priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3203 + fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3204 +
3205 + rx++;
3206 + } else {
3207 + complete = 1;
3208 + }
3209 + }
3210 +
3211 +#ifdef CONFIG_INET_LRO
3212 + if (priv->soc->get_skb_header)
3213 + lro_flush_all(&priv->lro_mgr);
3214 +#endif
3215 + if (complete) {
3216 + napi_complete(&priv->rx_napi);
3217 + fe_int_enable(priv->soc->rx_dly_int);
3218 + }
3219 +
3220 + return rx;
3221 +}
3222 +
3223 +static void fe_tx_housekeeping(unsigned long ptr)
3224 +{
3225 + struct net_device *dev = (struct net_device*)ptr;
3226 + struct fe_priv *priv = netdev_priv(dev);
3227 + unsigned int bytes_compl = 0;
3228 + unsigned int pkts_compl = 0;
3229 +
3230 + spin_lock(&priv->page_lock);
3231 + while (1) {
3232 + struct fe_tx_dma *txd;
3233 +
3234 + txd = &priv->tx_dma[priv->tx_free_idx];
3235 +
3236 + if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3237 + break;
3238 +
3239 + bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3240 + pkts_compl++;
3241 +
3242 + dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3243 + priv->tx_skb[priv->tx_free_idx] = NULL;
3244 + priv->tx_free_idx++;
3245 + if (priv->tx_free_idx >= NUM_DMA_DESC)
3246 + priv->tx_free_idx = 0;
3247 + }
3248 +
3249 + netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3250 + spin_unlock(&priv->page_lock);
3251 +
3252 + fe_int_enable(priv->soc->tx_dly_int);
3253 +}
3254 +
3255 +static void fe_tx_timeout(struct net_device *dev)
3256 +{
3257 + struct fe_priv *priv = netdev_priv(dev);
3258 +
3259 + tasklet_schedule(&priv->tx_tasklet);
3260 + priv->netdev->stats.tx_errors++;
3261 + netdev_err(dev, "transmit timed out, waking up the queue\n");
3262 + netif_wake_queue(dev);
3263 +}
3264 +
3265 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3266 +{
3267 + struct fe_priv *priv = netdev_priv(dev);
3268 + unsigned int status;
3269 + unsigned int mask;
3270 +
3271 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3272 + mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3273 +
3274 + if (!(status & mask))
3275 + return IRQ_NONE;
3276 +
3277 + if (status & priv->soc->rx_dly_int) {
3278 + fe_int_disable(priv->soc->rx_dly_int);
3279 + napi_schedule(&priv->rx_napi);
3280 + }
3281 +
3282 + if (status & priv->soc->tx_dly_int) {
3283 + fe_int_disable(priv->soc->tx_dly_int);
3284 + tasklet_schedule(&priv->tx_tasklet);
3285 + }
3286 +
3287 + fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3288 +
3289 + return IRQ_HANDLED;
3290 +}
3291 +
3292 +static int fe_hw_init(struct net_device *dev)
3293 +{
3294 + struct fe_priv *priv = netdev_priv(dev);
3295 + int err;
3296 +
3297 + err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3298 + dev_name(priv->device), dev);
3299 + if (err)
3300 + return err;
3301 +
3302 + err = fe_alloc_rx(priv);
3303 + if (!err)
3304 + err = fe_alloc_tx(priv);
3305 + if (err)
3306 + return err;
3307 +
3308 + if (priv->soc->set_mac)
3309 + priv->soc->set_mac(priv, dev->dev_addr);
3310 + else
3311 + fe_hw_set_macaddr(priv, dev->dev_addr);
3312 +
3313 + fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3314 +
3315 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3316 +
3317 + tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
3318 +
3319 + if (priv->soc->fwd_config) {
3320 + priv->soc->fwd_config(priv);
3321 + } else {
3322 + unsigned long sysclk = priv->sysclk;
3323 +
3324 + if (!sysclk) {
3325 + netdev_err(dev, "unable to get clock\n");
3326 + return -EINVAL;
3327 + }
3328 +
3329 + sysclk /= FE_US_CYC_CNT_DIVISOR;
3330 + sysclk <<= FE_US_CYC_CNT_SHIFT;
3331 +
3332 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
3333 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
3334 + FE_FE_GLO_CFG);
3335 +
3336 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3337 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3338 + FE_GDMA1_FWD_CFG);
3339 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3340 + FE_CDMA_CSG_CFG);
3341 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3342 + }
3343 +
3344 + fe_w32(1, FE_FE_RST_GL);
3345 + fe_w32(0, FE_FE_RST_GL);
3346 +
3347 + return 0;
3348 +}
3349 +
3350 +static int fe_open(struct net_device *dev)
3351 +{
3352 + struct fe_priv *priv = netdev_priv(dev);
3353 + unsigned long flags;
3354 + u32 val;
3355 +
3356 + spin_lock_irqsave(&priv->page_lock, flags);
3357 + napi_enable(&priv->rx_napi);
3358 +
3359 + val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
3360 + val |= priv->soc->pdma_glo_cfg;
3361 + fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
3362 +
3363 + spin_unlock_irqrestore(&priv->page_lock, flags);
3364 +
3365 + if (priv->phy)
3366 + priv->phy->start(priv);
3367 +
3368 + if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
3369 + netif_carrier_on(dev);
3370 +
3371 + netif_start_queue(dev);
3372 + fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3373 +
3374 + return 0;
3375 +}
3376 +
3377 +static int fe_stop(struct net_device *dev)
3378 +{
3379 + struct fe_priv *priv = netdev_priv(dev);
3380 + unsigned long flags;
3381 +
3382 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3383 +
3384 + netif_stop_queue(dev);
3385 +
3386 + if (priv->phy)
3387 + priv->phy->stop(priv);
3388 +
3389 + spin_lock_irqsave(&priv->page_lock, flags);
3390 + napi_disable(&priv->rx_napi);
3391 +
3392 + fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
3393 + ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
3394 + FE_REG_PDMA_GLO_CFG);
3395 + spin_unlock_irqrestore(&priv->page_lock, flags);
3396 +
3397 + return 0;
3398 +}
3399 +
3400 +static int __init fe_init(struct net_device *dev)
3401 +{
3402 + struct fe_priv *priv = netdev_priv(dev);
3403 + struct device_node *port;
3404 + int err;
3405 +
3406 + BUG_ON(!priv->soc->reset_fe);
3407 + priv->soc->reset_fe();
3408 +
3409 + if (priv->soc->switch_init)
3410 + priv->soc->switch_init(priv);
3411 +
3412 + net_srandom(jiffies);
3413 + memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
3414 + of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
3415 +
3416 + err = fe_mdio_init(priv);
3417 + if (err)
3418 + return err;
3419 +
3420 + if (priv->phy) {
3421 + err = priv->phy->connect(priv);
3422 + if (err)
3423 + goto err_mdio_cleanup;
3424 + }
3425 +
3426 + if (priv->soc->port_init)
3427 + for_each_child_of_node(priv->device->of_node, port)
3428 + if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
3429 + priv->soc->port_init(priv, port);
3430 +
3431 + err = fe_hw_init(dev);
3432 + if (err)
3433 + goto err_phy_disconnect;
3434 +
3435 + if (priv->soc->switch_config)
3436 + priv->soc->switch_config(priv);
3437 +
3438 + return 0;
3439 +
3440 +err_phy_disconnect:
3441 + if (priv->phy)
3442 + priv->phy->disconnect(priv);
3443 +err_mdio_cleanup:
3444 + fe_mdio_cleanup(priv);
3445 +
3446 + return err;
3447 +}
3448 +
3449 +static void fe_uninit(struct net_device *dev)
3450 +{
3451 + struct fe_priv *priv = netdev_priv(dev);
3452 +
3453 + tasklet_kill(&priv->tx_tasklet);
3454 +
3455 + if (priv->phy)
3456 + priv->phy->disconnect(priv);
3457 + fe_mdio_cleanup(priv);
3458 +
3459 + fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
3460 + free_irq(dev->irq, dev);
3461 +
3462 + fe_free_dma(priv);
3463 +}
3464 +
3465 +static const struct net_device_ops fe_netdev_ops = {
3466 + .ndo_init = fe_init,
3467 + .ndo_uninit = fe_uninit,
3468 + .ndo_open = fe_open,
3469 + .ndo_stop = fe_stop,
3470 + .ndo_start_xmit = fe_start_xmit,
3471 + .ndo_tx_timeout = fe_tx_timeout,
3472 + .ndo_set_mac_address = fe_set_mac_address,
3473 + .ndo_change_mtu = eth_change_mtu,
3474 + .ndo_validate_addr = eth_validate_addr,
3475 +};
3476 +
3477 +static int fe_probe(struct platform_device *pdev)
3478 +{
3479 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3480 + const struct of_device_id *match;
3481 + struct fe_soc_data *soc = NULL;
3482 + struct net_device *netdev;
3483 + struct fe_priv *priv;
3484 + struct clk *sysclk;
3485 + int err;
3486 +
3487 + device_reset(&pdev->dev);
3488 +
3489 + match = of_match_device(of_fe_match, &pdev->dev);
3490 + soc = (struct fe_soc_data *) match->data;
3491 + if (soc->reg_table)
3492 + fe_reg_table = soc->reg_table;
3493 +
3494 + fe_base = devm_request_and_ioremap(&pdev->dev, res);
3495 + if (!fe_base)
3496 + return -ENOMEM;
3497 +
3498 + netdev = alloc_etherdev(sizeof(struct fe_priv));
3499 + if (!netdev) {
3500 + dev_err(&pdev->dev, "alloc_etherdev failed\n");
3501 + return -ENOMEM;
3502 + }
3503 +
3504 + strcpy(netdev->name, "eth%d");
3505 + netdev->netdev_ops = &fe_netdev_ops;
3506 + netdev->base_addr = (unsigned long) fe_base;
3507 + netdev->watchdog_timeo = TX_TIMEOUT;
3508 + netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3509 +
3510 + if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
3511 + netdev->features |= NETIF_F_HW_VLAN_CTAG_TX;
3512 +
3513 + netdev->irq = platform_get_irq(pdev, 0);
3514 + if (netdev->irq < 0) {
3515 + dev_err(&pdev->dev, "no IRQ resource found\n");
3516 + kfree(netdev);
3517 + return -ENXIO;
3518 + }
3519 +
3520 + priv = netdev_priv(netdev);
3521 + memset(priv, 0, sizeof(struct fe_priv));
3522 + spin_lock_init(&priv->page_lock);
3523 +
3524 + sysclk = devm_clk_get(&pdev->dev, NULL);
3525 + if (!IS_ERR(sysclk))
3526 + priv->sysclk = clk_get_rate(sysclk);
3527 +
3528 + priv->netdev = netdev;
3529 + priv->device = &pdev->dev;
3530 + priv->soc = soc;
3531 +
3532 + err = register_netdev(netdev);
3533 + if (err) {
3534 + dev_err(&pdev->dev, "error bringing up device\n");
3535 + kfree(netdev);
3536 + return err;
3537 + }
3538 + netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
3539 +
3540 +#ifdef CONFIG_INET_LRO
3541 + if (priv->soc->get_skb_header) {
3542 + priv->lro_mgr.dev = netdev;
3543 + memset(&priv->lro_mgr.stats, 0, sizeof(priv->lro_mgr.stats));
3544 + priv->lro_mgr.features = LRO_F_NAPI;
3545 + priv->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
3546 + priv->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
3547 + priv->lro_mgr.max_desc = ARRAY_SIZE(priv->lro_arr);
3548 + priv->lro_mgr.max_aggr = 64;
3549 + priv->lro_mgr.frag_align_pad = 0;
3550 + priv->lro_mgr.lro_arr = priv->lro_arr;
3551 + priv->lro_mgr.get_skb_header = priv->soc->get_skb_header;
3552 + }
3553 +#endif
3554 +
3555 + platform_set_drvdata(pdev, netdev);
3556 +
3557 + netdev_info(netdev, "done loading\n");
3558 +
3559 + return 0;
3560 +}
3561 +
3562 +static int fe_remove(struct platform_device *pdev)
3563 +{
3564 + struct net_device *dev = platform_get_drvdata(pdev);
3565 + struct fe_priv *priv = netdev_priv(dev);
3566 +
3567 + netif_stop_queue(dev);
3568 + netif_napi_del(&priv->rx_napi);
3569 +
3570 + unregister_netdev(dev);
3571 + free_netdev(dev);
3572 +
3573 + return 0;
3574 +}
3575 +
3576 +static struct platform_driver fe_driver = {
3577 + .probe = fe_probe,
3578 + .remove = fe_remove,
3579 + .driver = {
3580 + .name = "ralink_soc_eth",
3581 + .owner = THIS_MODULE,
3582 + .of_match_table = of_fe_match,
3583 + },
3584 +};
3585 +
3586 +static int __init init_rtfe(void)
3587 +{
3588 + int ret;
3589 +
3590 + ret = rtesw_init();
3591 + if (ret)
3592 + return ret;
3593 +
3594 + ret = platform_driver_register(&fe_driver);
3595 + if (ret)
3596 + rtesw_exit();
3597 +
3598 + return ret;
3599 +}
3600 +
3601 +static void __exit exit_rtfe(void)
3602 +{
3603 + platform_driver_unregister(&fe_driver);
3604 + rtesw_exit();
3605 +}
3606 +
3607 +module_init(init_rtfe);
3608 +module_exit(exit_rtfe);
3609 +
3610 +MODULE_LICENSE("GPL");
3611 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3612 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
3613 Index: linux-3.10.18/drivers/net/ethernet/ralink/ralink_soc_eth.h
3614 ===================================================================
3615 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3616 +++ linux-3.10.18/drivers/net/ethernet/ralink/ralink_soc_eth.h 2013-11-21 17:05:21.368594293 +0100
3617 @@ -0,0 +1,380 @@
3618 +/*
3619 + * This program is free software; you can redistribute it and/or modify
3620 + * it under the terms of the GNU General Public License as published by
3621 + * the Free Software Foundation; version 2 of the License
3622 + *
3623 + * This program is distributed in the hope that it will be useful,
3624 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3625 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3626 + * GNU General Public License for more details.
3627 + *
3628 + * You should have received a copy of the GNU General Public License
3629 + * along with this program; if not, write to the Free Software
3630 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3631 + *
3632 + * based on Ralink SDK3.3
3633 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3634 + */
3635 +
3636 +#ifndef FE_ETH_H
3637 +#define FE_ETH_H
3638 +
3639 +#include <linux/mii.h>
3640 +#include <linux/interrupt.h>
3641 +#include <linux/netdevice.h>
3642 +#include <linux/dma-mapping.h>
3643 +#include <linux/phy.h>
3644 +#include <linux/inet_lro.h>
3645 +
3646 +
3647 +enum fe_reg {
3648 + FE_REG_PDMA_GLO_CFG = 0,
3649 + FE_REG_PDMA_RST_CFG,
3650 + FE_REG_DLY_INT_CFG,
3651 + FE_REG_TX_BASE_PTR0,
3652 + FE_REG_TX_MAX_CNT0,
3653 + FE_REG_TX_CTX_IDX0,
3654 + FE_REG_RX_BASE_PTR0,
3655 + FE_REG_RX_MAX_CNT0,
3656 + FE_REG_RX_CALC_IDX0,
3657 + FE_REG_FE_INT_ENABLE,
3658 + FE_REG_FE_INT_STATUS,
3659 + FE_REG_FE_DMA_VID_BASE,
3660 + FE_REG_COUNT
3661 +};
3662 +
3663 +#define NUM_DMA_DESC 0x100
3664 +
3665 +#define FE_DELAY_EN_INT 0x80
3666 +#define FE_DELAY_MAX_INT 0x04
3667 +#define FE_DELAY_MAX_TOUT 0x04
3668 +#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
3669 +#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
3670 +#define FE_PSE_FQFC_CFG_INIT 0x80504000
3671 +
3672 +/* interrupt bits */
3673 +#define FE_CNT_PPE_AF BIT(31)
3674 +#define FE_CNT_GDM_AF BIT(29)
3675 +#define FE_PSE_P2_FC BIT(26)
3676 +#define FE_PSE_BUF_DROP BIT(24)
3677 +#define FE_GDM_OTHER_DROP BIT(23)
3678 +#define FE_PSE_P1_FC BIT(22)
3679 +#define FE_PSE_P0_FC BIT(21)
3680 +#define FE_PSE_FQ_EMPTY BIT(20)
3681 +#define FE_GE1_STA_CHG BIT(18)
3682 +#define FE_TX_COHERENT BIT(17)
3683 +#define FE_RX_COHERENT BIT(16)
3684 +#define FE_TX_DONE_INT3 BIT(11)
3685 +#define FE_TX_DONE_INT2 BIT(10)
3686 +#define FE_TX_DONE_INT1 BIT(9)
3687 +#define FE_TX_DONE_INT0 BIT(8)
3688 +#define FE_RX_DONE_INT0 BIT(2)
3689 +#define FE_TX_DLY_INT BIT(1)
3690 +#define FE_RX_DLY_INT BIT(0)
3691 +
3692 +#define RT5350_RX_DLY_INT BIT(30)
3693 +#define RT5350_TX_DLY_INT BIT(28)
3694 +
3695 +/* registers */
3696 +#define FE_FE_OFFSET 0x0000
3697 +#define FE_GDMA_OFFSET 0x0020
3698 +#define FE_PSE_OFFSET 0x0040
3699 +#define FE_GDMA2_OFFSET 0x0060
3700 +#define FE_CDMA_OFFSET 0x0080
3701 +#define FE_DMA_VID0 0x00a8
3702 +#define FE_PDMA_OFFSET 0x0100
3703 +#define FE_PPE_OFFSET 0x0200
3704 +#define FE_CMTABLE_OFFSET 0x0400
3705 +#define FE_POLICYTABLE_OFFSET 0x1000
3706 +
3707 +#define RT5350_PDMA_OFFSET 0x0800
3708 +#define RT5350_SDM_OFFSET 0x0c00
3709 +
3710 +#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
3711 +#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
3712 +#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
3713 +#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
3714 +#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
3715 +#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
3716 +#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
3717 +#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
3718 +
3719 +#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
3720 +#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
3721 +#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
3722 +#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
3723 +#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
3724 +
3725 +#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
3726 +#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
3727 +#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
3728 +#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
3729 +#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
3730 +
3731 +#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
3732 +#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
3733 +#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
3734 +#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
3735 +
3736 +#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
3737 +#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
3738 +
3739 +#define MT7620A_GDMA_OFFSET 0x0600
3740 +#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
3741 +#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
3742 +#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
3743 +#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
3744 +#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
3745 +
3746 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
3747 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
3748 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
3749 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
3750 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
3751 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
3752 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
3753 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
3754 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
3755 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
3756 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
3757 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
3758 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
3759 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
3760 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
3761 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
3762 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
3763 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
3764 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
3765 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
3766 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
3767 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
3768 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
3769 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
3770 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
3771 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
3772 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
3773 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
3774 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
3775 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
3776 +
3777 +#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
3778 +#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
3779 +#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
3780 +#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
3781 +#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
3782 +#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
3783 +#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
3784 +#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
3785 +#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
3786 +#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
3787 +#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
3788 +#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
3789 +#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
3790 +#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
3791 +#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
3792 +#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
3793 +#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
3794 +#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
3795 +#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
3796 +#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
3797 +#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
3798 +#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
3799 +#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
3800 +#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
3801 +#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
3802 +#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
3803 +#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
3804 +#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
3805 +
3806 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
3807 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
3808 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
3809 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
3810 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
3811 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
3812 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
3813 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
3814 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
3815 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
3816 +
3817 +#define RT5350_SDM_ICS_EN BIT(16)
3818 +#define RT5350_SDM_TCS_EN BIT(17)
3819 +#define RT5350_SDM_UCS_EN BIT(18)
3820 +
3821 +
3822 +/* MDIO_CFG register bits */
3823 +#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
3824 +#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
3825 +#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
3826 +#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
3827 +#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
3828 +#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
3829 +#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
3830 +#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
3831 +#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
3832 +#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
3833 +#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
3834 +#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
3835 +#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
3836 +#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
3837 +#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
3838 +#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
3839 +#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
3840 +#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
3841 +#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
3842 +#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
3843 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
3844 +#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
3845 +#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
3846 +#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
3847 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
3848 +
3849 +/* uni-cast port */
3850 +#define FE_GDM1_ICS_EN BIT(22)
3851 +#define FE_GDM1_TCS_EN BIT(21)
3852 +#define FE_GDM1_UCS_EN BIT(20)
3853 +#define FE_GDM1_JMB_EN BIT(19)
3854 +#define FE_GDM1_STRPCRC BIT(16)
3855 +#define FE_GDM1_UFRC_P_CPU (0 << 12)
3856 +#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
3857 +#define FE_GDM1_UFRC_P_PPE (6 << 12)
3858 +
3859 +/* checksums */
3860 +#define FE_ICS_GEN_EN BIT(2)
3861 +#define FE_UCS_GEN_EN BIT(1)
3862 +#define FE_TCS_GEN_EN BIT(0)
3863 +
3864 +/* dma ring */
3865 +#define FE_PST_DRX_IDX0 BIT(16)
3866 +#define FE_PST_DTX_IDX3 BIT(3)
3867 +#define FE_PST_DTX_IDX2 BIT(2)
3868 +#define FE_PST_DTX_IDX1 BIT(1)
3869 +#define FE_PST_DTX_IDX0 BIT(0)
3870 +
3871 +#define FE_TX_WB_DDONE BIT(6)
3872 +#define FE_RX_DMA_BUSY BIT(3)
3873 +#define FE_TX_DMA_BUSY BIT(1)
3874 +#define FE_RX_DMA_EN BIT(2)
3875 +#define FE_TX_DMA_EN BIT(0)
3876 +
3877 +#define FE_PDMA_SIZE_4DWORDS (0 << 4)
3878 +#define FE_PDMA_SIZE_8DWORDS (1 << 4)