target/linux/ramips/patches-3.10/0114-PCI-MIPS-adds-rt2880-pci-support.patch

   1 From b7040c3ad7b8daf8309d083e9248cfa577075cfb Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 18:27:29 +0100
   4 Subject: [PATCH 114/133] PCI: MIPS: adds rt2880 pci support
   5
   6 Add support for the pci found on the rt2880 SoC.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  arch/mips/pci/Makefile     |    1 +
  11  arch/mips/pci/pci-rt2880.c |  281 ++++++++++++++++++++++++++++++++++++++++++++
  12  arch/mips/ralink/Kconfig   |    1 +
  13  3 files changed, 283 insertions(+)
  14  create mode 100644 arch/mips/pci/pci-rt2880.c
  15
  16 --- a/arch/mips/pci/Makefile
  17 +++ b/arch/mips/pci/Makefile
  18 @@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)  += pci-bcm1
  19  obj-$(CONFIG_SNI_RM)           += fixup-sni.o ops-sni.o
  20  obj-$(CONFIG_LANTIQ)           += fixup-lantiq.o
  21  obj-$(CONFIG_PCI_LANTIQ)       += pci-lantiq.o ops-lantiq.o
  22 +obj-$(CONFIG_SOC_RT2880)       += pci-rt2880.o
  23  obj-$(CONFIG_SOC_RT3883)       += pci-rt3883.o
  24  obj-$(CONFIG_TANBAC_TB0219)    += fixup-tb0219.o
  25  obj-$(CONFIG_TANBAC_TB0226)    += fixup-tb0226.o
  26 --- /dev/null
  27 +++ b/arch/mips/pci/pci-rt2880.c
  28 @@ -0,0 +1,281 @@
  29 +/*
  30 + *  Ralink RT288x SoC PCI register definitions
  31 + *
  32 + *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
  33 + *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
  34 + *
  35 + *  Parts of this file are based on Ralink's 2.6.21 BSP
  36 + *
  37 + *  This program is free software; you can redistribute it and/or modify it
  38 + *  under the terms of the GNU General Public License version 2 as published
  39 + *  by the Free Software Foundation.
  40 + */
  41 +
  42 +#include <linux/types.h>
  43 +#include <linux/pci.h>
  44 +#include <linux/io.h>
  45 +#include <linux/init.h>
  46 +#include <linux/module.h>
  47 +#include <linux/of_platform.h>
  48 +#include <linux/of_irq.h>
  49 +#include <linux/of_pci.h>
  50 +
  51 +#include <asm/mach-ralink/rt288x.h>
  52 +
  53 +#define RT2880_PCI_BASE                0x00440000
  54 +#define RT288X_CPU_IRQ_PCI     4
  55 +
  56 +#define RT2880_PCI_MEM_BASE    0x20000000
  57 +#define RT2880_PCI_MEM_SIZE    0x10000000
  58 +#define RT2880_PCI_IO_BASE     0x00460000
  59 +#define RT2880_PCI_IO_SIZE     0x00010000
  60 +
  61 +#define RT2880_PCI_REG_PCICFG_ADDR     0x00
  62 +#define RT2880_PCI_REG_PCIMSK_ADDR     0x0c
  63 +#define RT2880_PCI_REG_BAR0SETUP_ADDR  0x10
  64 +#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
  65 +#define RT2880_PCI_REG_CONFIG_ADDR     0x20
  66 +#define RT2880_PCI_REG_CONFIG_DATA     0x24
  67 +#define RT2880_PCI_REG_MEMBASE         0x28
  68 +#define RT2880_PCI_REG_IOBASE          0x2c
  69 +#define RT2880_PCI_REG_ID              0x30
  70 +#define RT2880_PCI_REG_CLASS           0x34
  71 +#define RT2880_PCI_REG_SUBID           0x38
  72 +#define RT2880_PCI_REG_ARBCTL          0x80
  73 +
  74 +static void __iomem *rt2880_pci_base;
  75 +static DEFINE_SPINLOCK(rt2880_pci_lock);
  76 +
  77 +static u32 rt2880_pci_reg_read(u32 reg)
  78 +{
  79 +       return readl(rt2880_pci_base + reg);
  80 +}
  81 +
  82 +static void rt2880_pci_reg_write(u32 val, u32 reg)
  83 +{
  84 +       writel(val, rt2880_pci_base + reg);
  85 +}
  86 +
  87 +static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
  88 +                                        unsigned int func, unsigned int where)
  89 +{
  90 +       return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
  91 +               0x80000000);
  92 +}
  93 +
  94 +static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  95 +                                 int where, int size, u32 *val)
  96 +{
  97 +       unsigned long flags;
  98 +       u32 address;
  99 +       u32 data;
 100 +
 101 +       address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 102 +                                        PCI_FUNC(devfn), where);
 103 +
 104 +       spin_lock_irqsave(&rt2880_pci_lock, flags);
 105 +       rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 106 +       data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 107 +       spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 108 +
 109 +       switch (size) {
 110 +       case 1:
 111 +               *val = (data >> ((where & 3) << 3)) & 0xff;
 112 +               break;
 113 +       case 2:
 114 +               *val = (data >> ((where & 3) << 3)) & 0xffff;
 115 +               break;
 116 +       case 4:
 117 +               *val = data;
 118 +               break;
 119 +       }
 120 +
 121 +       return PCIBIOS_SUCCESSFUL;
 122 +}
 123 +
 124 +static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
 125 +                                  int where, int size, u32 val)
 126 +{
 127 +       unsigned long flags;
 128 +       u32 address;
 129 +       u32 data;
 130 +
 131 +       address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
 132 +                                        PCI_FUNC(devfn), where);
 133 +
 134 +       spin_lock_irqsave(&rt2880_pci_lock, flags);
 135 +       rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 136 +       data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 137 +
 138 +       switch (size) {
 139 +       case 1:
 140 +               data = (data & ~(0xff << ((where & 3) << 3))) |
 141 +                      (val << ((where & 3) << 3));
 142 +               break;
 143 +       case 2:
 144 +               data = (data & ~(0xffff << ((where & 3) << 3))) |
 145 +                      (val << ((where & 3) << 3));
 146 +               break;
 147 +       case 4:
 148 +               data = val;
 149 +               break;
 150 +       }
 151 +
 152 +       rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
 153 +       spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 154 +
 155 +       return PCIBIOS_SUCCESSFUL;
 156 +}
 157 +
 158 +static struct pci_ops rt2880_pci_ops = {
 159 +       .read   = rt2880_pci_config_read,
 160 +       .write  = rt2880_pci_config_write,
 161 +};
 162 +
 163 +static struct resource rt2880_pci_mem_resource = {
 164 +       .name   = "PCI MEM space",
 165 +       .start  = RT2880_PCI_MEM_BASE,
 166 +       .end    = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
 167 +       .flags  = IORESOURCE_MEM,
 168 +};
 169 +
 170 +static struct resource rt2880_pci_io_resource = {
 171 +       .name   = "PCI IO space",
 172 +       .start  = RT2880_PCI_IO_BASE,
 173 +       .end    = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
 174 +       .flags  = IORESOURCE_IO,
 175 +};
 176 +
 177 +static struct pci_controller rt2880_pci_controller = {
 178 +       .pci_ops        = &rt2880_pci_ops,
 179 +       .mem_resource   = &rt2880_pci_mem_resource,
 180 +       .io_resource    = &rt2880_pci_io_resource,
 181 +};
 182 +
 183 +static inline u32 rt2880_pci_read_u32(unsigned long reg)
 184 +{
 185 +       unsigned long flags;
 186 +       u32 address;
 187 +       u32 ret;
 188 +
 189 +       address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
 190 +
 191 +       spin_lock_irqsave(&rt2880_pci_lock, flags);
 192 +       rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 193 +       ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 194 +       spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 195 +
 196 +       return ret;
 197 +}
 198 +
 199 +static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
 200 +{
 201 +       unsigned long flags;
 202 +       u32 address;
 203 +
 204 +       address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
 205 +
 206 +       spin_lock_irqsave(&rt2880_pci_lock, flags);
 207 +       rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 208 +       rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
 209 +       spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 210 +}
 211 +
 212 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 213 +{
 214 +       u16 cmd;
 215 +       int irq = -1;
 216 +
 217 +       if (dev->bus->number != 0)
 218 +               return irq;
 219 +
 220 +       switch (PCI_SLOT(dev->devfn)) {
 221 +       case 0x00:
 222 +               rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
 223 +               (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
 224 +               break;
 225 +       case 0x11:
 226 +               irq = RT288X_CPU_IRQ_PCI;
 227 +               break;
 228 +       default:
 229 +               printk("%s:%s[%d] trying to alloc unknown pci irq\n",
 230 +                      __FILE__, __func__, __LINE__);
 231 +               BUG();
 232 +               break;
 233 +       }
 234 +
 235 +       pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
 236 +       pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
 237 +       pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
 238 +       cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 239 +              PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
 240 +              PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
 241 +       pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
 242 +       pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
 243 +                             dev->irq);
 244 +       return irq;
 245 +}
 246 +
 247 +static int rt288x_pci_probe(struct platform_device *pdev)
 248 +{
 249 +       void __iomem *io_map_base;
 250 +       int i;
 251 +
 252 +       rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
 253 +
 254 +       io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
 255 +       rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
 256 +       set_io_port_base((unsigned long) io_map_base);
 257 +
 258 +       ioport_resource.start = RT2880_PCI_IO_BASE;
 259 +       ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
 260 +
 261 +       rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
 262 +       for(i = 0; i < 0xfffff; i++) {}
 263 +
 264 +       rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
 265 +       rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
 266 +       rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
 267 +       rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
 268 +       rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
 269 +       rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
 270 +       rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
 271 +       rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
 272 +       rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
 273 +
 274 +       rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
 275 +       (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
 276 +
 277 +       register_pci_controller(&rt2880_pci_controller);
 278 +       return 0;
 279 +}
 280 +
 281 +int pcibios_plat_dev_init(struct pci_dev *dev)
 282 +{
 283 +       return 0;
 284 +}
 285 +
 286 +static const struct of_device_id rt288x_pci_match[] = {
 287 +       { .compatible = "ralink,rt288x-pci" },
 288 +       {},
 289 +};
 290 +MODULE_DEVICE_TABLE(of, rt288x_pci_match);
 291 +
 292 +static struct platform_driver rt288x_pci_driver = {
 293 +       .probe = rt288x_pci_probe,
 294 +       .driver = {
 295 +               .name = "rt288x-pci",
 296 +               .owner = THIS_MODULE,
 297 +               .of_match_table = rt288x_pci_match,
 298 +       },
 299 +};
 300 +
 301 +int __init pcibios_init(void)
 302 +{
 303 +       int ret = platform_driver_register(&rt288x_pci_driver);
 304 +       if (ret)
 305 +               pr_info("rt288x-pci: Error registering platform driver!");
 306 +       return ret;
 307 +}
 308 +
 309 +arch_initcall(pcibios_init);
 310 --- a/arch/mips/ralink/Kconfig
 311 +++ b/arch/mips/ralink/Kconfig
 312 @@ -15,6 +15,7 @@ choice
 313
 314         config SOC_RT288X
 315                 bool "RT288x"
 316 +               select HW_HAS_PCI
 317
 318         config SOC_RT305X
 319                 bool "RT305x"