projects / openwrt / openwrt.git / blob
? search:


af65043fc85f3fe4729b3855a1e9b271c0eb8f3e
[openwrt/openwrt.git] / target / linux / ramips / patches-3.10 / 0122-pinmux.patch
1 From d59fe652e3674e98caa688b4ddc9308007267adc Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 19 Aug 2013 13:49:52 +0200
4 Subject: [PATCH] pinctrl: ralink; add pinctrl driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/Kconfig | 2 +
9 arch/mips/ralink/common.h | 21 +--
10 arch/mips/ralink/dts/mt7620a.dtsi | 7 +
11 drivers/pinctrl/Kconfig | 5 +
12 drivers/pinctrl/Makefile | 1 +
13 drivers/pinctrl/pinctrl-rt2880.c | 368 +++++++++++++++++++++++++++++++++++++
14 6 files changed, 385 insertions(+), 19 deletions(-)
15 create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
16
17 Index: linux-3.10.17/arch/mips/Kconfig
18 ===================================================================
19 --- linux-3.10.17.orig/arch/mips/Kconfig 2013-10-26 17:19:49.094708911 +0200
20 +++ linux-3.10.17/arch/mips/Kconfig 2013-10-26 17:19:49.926708932 +0200
21 @@ -446,6 +446,8 @@
22 select HAVE_MACH_CLKDEV
23 select CLKDEV_LOOKUP
24 select ARCH_REQUIRE_GPIOLIB
25 + select PINCTRL
26 + select PINCTRL_RT2880
27
28 config SGI_IP22
29 bool "SGI IP22 (Indy/Indigo2)"
30 Index: linux-3.10.17/drivers/pinctrl/Kconfig
31 ===================================================================
32 --- linux-3.10.17.orig/drivers/pinctrl/Kconfig 2013-10-18 19:44:19.000000000 +0200
33 +++ linux-3.10.17/drivers/pinctrl/Kconfig 2013-10-26 17:19:49.930708931 +0200
34 @@ -114,6 +114,11 @@
35 select PINMUX
36 select PINCONF
37
38 +config PINCTRL_RT2880
39 + bool
40 + depends on RALINK
41 + select PINMUX
42 +
43 config PINCTRL_FALCON
44 bool
45 depends on SOC_FALCON
46 Index: linux-3.10.17/drivers/pinctrl/Makefile
47 ===================================================================
48 --- linux-3.10.17.orig/drivers/pinctrl/Makefile 2013-10-18 19:44:19.000000000 +0200
49 +++ linux-3.10.17/drivers/pinctrl/Makefile 2013-10-26 17:19:49.930708931 +0200
50 @@ -45,6 +45,7 @@
51 obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
52 obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
53 obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
54 +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
55
56 obj-$(CONFIG_PLAT_ORION) += mvebu/
57 obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
58 Index: linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c
59 ===================================================================
60 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
61 +++ linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c 2013-10-27 16:22:50.132754888 +0100
62 @@ -0,0 +1,466 @@
63 +/*
64 + * linux/drivers/pinctrl/pinctrl-rt2880.c
65 + *
66 + * This program is free software; you can redistribute it and/or modify
67 + * it under the terms of the GNU General Public License version 2 as
68 + * publishhed by the Free Software Foundation.
69 + *
70 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
71 + */
72 +
73 +#include <linux/module.h>
74 +#include <linux/device.h>
75 +#include <linux/io.h>
76 +#include <linux/platform_device.h>
77 +#include <linux/slab.h>
78 +#include <linux/of.h>
79 +#include <linux/pinctrl/pinctrl.h>
80 +#include <linux/pinctrl/pinconf.h>
81 +#include <linux/pinctrl/pinmux.h>
82 +#include <linux/pinctrl/consumer.h>
83 +#include <linux/pinctrl/machine.h>
84 +
85 +#include <asm/mach-ralink/ralink_regs.h>
86 +#include <asm/mach-ralink/pinmux.h>
87 +#include <asm/mach-ralink/mt7620.h>
88 +
89 +#include "core.h"
90 +
91 +#define SYSC_REG_GPIO_MODE 0x60
92 +
93 +struct rt2880_priv {
94 + struct device *dev;
95 +
96 + struct pinctrl_pin_desc *pads;
97 + struct pinctrl_desc *desc;
98 +
99 + struct rt2880_pmx_func **func;
100 + int func_count;
101 +
102 + struct rt2880_pmx_group *groups;
103 + const char **group_names;
104 + int group_count;
105 +
106 + uint8_t *gpio;
107 + int max_pins;
108 +};
109 +
110 +struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
111 +
112 +static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
113 +{
114 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
115 +
116 + return p->group_count;
117 +}
118 +
119 +static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
120 + unsigned group)
121 +{
122 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
123 +
124 + if (group >= p->group_count)
125 + return NULL;
126 +
127 + return p->group_names[group];
128 +}
129 +
130 +static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
131 + unsigned group,
132 + const unsigned **pins,
133 + unsigned *num_pins)
134 +{
135 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
136 +
137 + if (group >= p->group_count)
138 + return -EINVAL;
139 +
140 + *pins = p->groups[group].func[0].pins;
141 + *num_pins = p->groups[group].func[0].pin_count;
142 +
143 + return 0;
144 +}
145 +
146 +static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
147 + struct pinctrl_map *map, unsigned num_maps)
148 +{
149 + int i;
150 +
151 + for (i = 0; i < num_maps; i++)
152 + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
153 + map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
154 + kfree(map[i].data.configs.configs);
155 + kfree(map);
156 +}
157 +
158 +static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
159 + struct seq_file *s,
160 + unsigned offset)
161 +{
162 + seq_printf(s, "ralink pio");
163 +}
164 +
165 +static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
166 + struct device_node *np,
167 + struct pinctrl_map **map)
168 +{
169 + const char *function;
170 + int func = of_property_read_string(np, "ralink,function", &function);
171 + int grps = of_property_count_strings(np, "ralink,group");
172 + int i;
173 +
174 + if (func || !grps)
175 + return;
176 +
177 + for (i = 0; i < grps; i++) {
178 + const char *group;
179 +
180 + of_property_read_string_index(np, "ralink,group", i, &group);
181 +
182 + (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
183 + (*map)->name = function;
184 + (*map)->data.mux.group = group;
185 + (*map)->data.mux.function = function;
186 + (*map)++;
187 + }
188 +}
189 +
190 +static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
191 + struct device_node *np_config,
192 + struct pinctrl_map **map,
193 + unsigned *num_maps)
194 +{
195 + int max_maps = 0;
196 + struct pinctrl_map *tmp;
197 + struct device_node *np;
198 +
199 + for_each_child_of_node(np_config, np) {
200 + int ret = of_property_count_strings(np, "ralink,group");
201 +
202 + if (ret >= 0)
203 + max_maps += ret;
204 + }
205 +
206 + if (!max_maps)
207 + return max_maps;
208 +
209 + *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
210 + if (!*map)
211 + return -ENOMEM;
212 +
213 + tmp = *map;
214 +
215 + for_each_child_of_node(np_config, np)
216 + rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
217 + *num_maps = max_maps;
218 +
219 + return 0;
220 +}
221 +
222 +static const struct pinctrl_ops rt2880_pctrl_ops = {
223 + .get_groups_count = rt2880_get_group_count,
224 + .get_group_name = rt2880_get_group_name,
225 + .get_group_pins = rt2880_get_group_pins,
226 + .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
227 + .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
228 + .dt_free_map = rt2880_pinctrl_dt_free_map,
229 +};
230 +
231 +static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
232 +{
233 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
234 +
235 + return p->func_count;
236 +}
237 +
238 +static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
239 + unsigned func)
240 +{
241 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
242 +
243 + return p->func[func]->name;
244 +}
245 +
246 +static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
247 + unsigned func,
248 + const char * const **groups,
249 + unsigned * const num_groups)
250 +{
251 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
252 +
253 + if (p->func[func]->group_count == 1)
254 + *groups = &p->group_names[p->func[func]->groups[0]];
255 + else
256 + *groups = p->group_names;
257 +
258 + *num_groups = p->func[func]->group_count;
259 +
260 + return 0;
261 +}
262 +
263 +static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
264 + unsigned func,
265 + unsigned group)
266 +{
267 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
268 + u32 mode = 0;
269 +
270 + /* dont allow double use */
271 + if (p->groups[group].enabled) {
272 + dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
273 + return -EBUSY;
274 + }
275 +
276 + p->groups[group].enabled = 1;
277 + p->func[func]->enabled = 1;
278 +
279 + mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
280 + mode &= ~(p->groups[group].mask << p->groups[group].shift);
281 +
282 + /* function 0 is gpio and needs special handling */
283 + if (func == 0) {
284 + int i;
285 +
286 +
287 + mode |= p->groups[group].gpio << p->groups[group].shift;
288 + /* mark the pins as gpio */
289 + for (i = 0; i < p->groups[group].func[0].pin_count; i++)
290 + p->gpio[p->groups[group].func[0].pins[i]] = 1;
291 + } else {
292 + mode |= p->func[func]->value << p->groups[group].shift;
293 + }
294 + rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
295 +
296 +
297 + return 0;
298 +}
299 +
300 +static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
301 + struct pinctrl_gpio_range *range,
302 + unsigned pin)
303 +{
304 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
305 +
306 + if (!p->gpio[pin]) {
307 + dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
308 + return -EINVAL;
309 + }
310 +
311 + return 0;
312 +}
313 +
314 +static const struct pinmux_ops rt2880_pmx_group_ops = {
315 + .get_functions_count = rt2880_pmx_func_count,
316 + .get_function_name = rt2880_pmx_func_name,
317 + .get_function_groups = rt2880_pmx_group_get_groups,
318 + .enable = rt2880_pmx_group_enable,
319 + .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
320 +};
321 +
322 +static struct pinctrl_desc rt2880_pctrl_desc = {
323 + .owner = THIS_MODULE,
324 + .name = "rt2880-pinmux",
325 + .pctlops = &rt2880_pctrl_ops,
326 + .pmxops = &rt2880_pmx_group_ops,
327 +};
328 +
329 +static struct rt2880_pmx_func gpio_func = {
330 + .name = "gpio",
331 +};
332 +
333 +static int rt2880_pinmux_index(struct rt2880_priv *p)
334 +{
335 + struct rt2880_pmx_func **f;
336 + struct rt2880_pmx_group *mux = p->groups;
337 + int i, j, c = 0;
338 +
339 + /* count the mux functions */
340 + while (mux->name) {
341 + p->group_count++;
342 + mux++;
343 + }
344 +
345 + /* allocate the group names array needed by the gpio function */
346 + p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
347 + if (!p->group_names)
348 + return -1;
349 +
350 + for (i = 0; i < p->group_count; i++) {
351 + p->group_names[i] = p->groups[i].name;
352 + p->func_count += p->groups[i].func_count;
353 + }
354 +
355 + /* we have a dummy function[0] for gpio */
356 + p->func_count++;
357 +
358 + /* allocate our function and group mapping index buffers */
359 + f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
360 + gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
361 + if (!f || !gpio_func.groups)
362 + return -1;
363 +
364 + /* add a backpointer to the function so it knows its group */
365 + gpio_func.group_count = p->group_count;
366 + for (i = 0; i < gpio_func.group_count; i++)
367 + gpio_func.groups[i] = i;
368 +
369 + f[c] = &gpio_func;
370 + c++;
371 +
372 + /* add remaining functions */
373 + for (i = 0; i < p->group_count; i++) {
374 + for (j = 0; j < p->groups[i].func_count; j++) {
375 + f[c] = &p->groups[i].func[j];
376 + f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
377 + f[c]->groups[0] = i;
378 + f[c]->group_count = 1;
379 + c++;
380 + }
381 + }
382 + return 0;
383 +}
384 +
385 +static int rt2880_pinmux_pins(struct rt2880_priv *p)
386 +{
387 + int i, j;
388 +
389 + /* loop over the functions and initialize the pins array. also work out the highest pin used */
390 + for (i = 0; i < p->func_count; i++) {
391 + int pin;
392 +
393 + if (!p->func[i]->pin_count)
394 + continue;
395 +
396 + p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
397 + for (j = 0; j < p->func[i]->pin_count; j++)
398 + p->func[i]->pins[j] = p->func[i]->pin_first + j;
399 +
400 + pin = p->func[i]->pin_first + p->func[i]->pin_count;
401 + if (pin > p->max_pins)
402 + p->max_pins = pin;
403 + }
404 +
405 + /* the buffer that tells us which pins are gpio */
406 + p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
407 + GFP_KERNEL);
408 + /* the pads needed to tell pinctrl about our pins */
409 + p->pads = devm_kzalloc(p->dev,
410 + sizeof(struct pinctrl_pin_desc) * p->max_pins,
411 + GFP_KERNEL);
412 + if (!p->pads || !p->gpio ) {
413 + dev_err(p->dev, "Failed to allocate gpio data\n");
414 + return -ENOMEM;
415 + }
416 +
417 + memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
418 + for (i = 0; i < p->func_count; i++) {
419 + if (!p->func[i]->pin_count)
420 + continue;
421 +
422 + for (j = 0; j < p->func[i]->pin_count; j++)
423 + p->gpio[p->func[i]->pins[j]] = 0;
424 + }
425 +
426 + /* pin 0 is always a gpio */
427 + p->gpio[0] = 1;
428 +
429 + /* set the pads */
430 + for (i = 0; i < p->max_pins; i++) {
431 + /* strlen("ioXY") + 1 = 5 */
432 + char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
433 +
434 + if (!name) {
435 + dev_err(p->dev, "Failed to allocate pad name\n");
436 + return -ENOMEM;
437 + }
438 + snprintf(name, 5, "io%d", i);
439 + p->pads[i].number = i;
440 + p->pads[i].name = name;
441 + }
442 + p->desc->pins = p->pads;
443 + p->desc->npins = p->max_pins;
444 +
445 + return 0;
446 +}
447 +
448 +static int rt2880_pinmux_probe(struct platform_device *pdev)
449 +{
450 + struct rt2880_priv *p;
451 + struct pinctrl_dev *dev;
452 + struct device_node *np;
453 +
454 + if (!rt2880_pinmux_data)
455 + return -ENOSYS;
456 +
457 + /* setup the private data */
458 + p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
459 + if (!p)
460 + return -ENOMEM;
461 +
462 + p->dev = &pdev->dev;
463 + p->desc = &rt2880_pctrl_desc;
464 + p->groups = rt2880_pinmux_data;
465 + platform_set_drvdata(pdev, p);
466 +
467 + /* init the device */
468 + if (rt2880_pinmux_index(p)) {
469 + dev_err(&pdev->dev, "failed to load index\n");
470 + return -EINVAL;
471 + }
472 + if (rt2880_pinmux_pins(p)) {
473 + dev_err(&pdev->dev, "failed to load pins\n");
474 + return -EINVAL;
475 + }
476 + dev = pinctrl_register(p->desc, &pdev->dev, p);
477 + if (IS_ERR(dev))
478 + return PTR_ERR(dev);
479 +
480 + /* finalize by adding gpio ranges for enables gpio controllers */
481 + for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
482 + const __be32 *ngpio, *gpiobase;
483 + struct pinctrl_gpio_range *range;
484 + char *name;
485 +
486 + if (!of_device_is_available(np))
487 + continue;
488 +
489 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
490 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
491 + if (!ngpio || !gpiobase) {
492 + dev_err(&pdev->dev, "failed to load chip info\n");
493 + return -EINVAL;
494 + }
495 +
496 + range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
497 + range->name = name = (char *) &range[1];
498 + sprintf(name, "pio");
499 + range->npins = __be32_to_cpu(*ngpio);
500 + range->base = __be32_to_cpu(*gpiobase);
501 + range->pin_base = range->base;
502 + pinctrl_add_gpio_range(dev, range);
503 + }
504 +
505 + return 0;
506 +}
507 +
508 +static const struct of_device_id rt2880_pinmux_match[] = {
509 + { .compatible = "ralink,rt2880-pinmux" },
510 + {},
511 +};
512 +MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
513 +
514 +static struct platform_driver rt2880_pinmux_driver = {
515 + .probe = rt2880_pinmux_probe,
516 + .driver = {
517 + .name = "rt2880-pinmux",
518 + .owner = THIS_MODULE,
519 + .of_match_table = rt2880_pinmux_match,
520 + },
521 +};
522 +
523 +int __init rt2880_pinmux_init(void)
524 +{
525 + return platform_driver_register(&rt2880_pinmux_driver);
526 +}
527 +
528 +core_initcall_sync(rt2880_pinmux_init);
529 Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h
530 ===================================================================
531 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
532 +++ linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h 2013-10-27 07:28:38.999991133 +0100
533 @@ -0,0 +1,53 @@
534 +/*
535 + * This program is free software; you can redistribute it and/or modify
536 + * it under the terms of the GNU General Public License version 2 as
537 + * publishhed by the Free Software Foundation.
538 + *
539 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
540 + */
541 +
542 +#ifndef _RT288X_PINMUX_H__
543 +#define _RT288X_PINMUX_H__
544 +
545 +#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
546 +#define GRP(_name, _func, _mask, _shift) \
547 + { .name = _name, .mask = _mask, .shift = _shift, \
548 + .func = _func, .gpio = _mask, \
549 + .func_count = ARRAY_SIZE(_func) }
550 +
551 +#define GRP_G(_name, _func, _mask, _gpio, _shift) \
552 + { .name = _name, .mask = _mask, .shift = _shift, \
553 + .func = _func, .gpio = _gpio, \
554 + .func_count = ARRAY_SIZE(_func) }
555 +
556 +struct rt2880_pmx_group;
557 +
558 +struct rt2880_pmx_func {
559 + const char *name;
560 + const char value;
561 +
562 + int pin_first;
563 + int pin_count;
564 + int *pins;
565 +
566 + int *groups;
567 + int group_count;
568 +
569 + int enabled;
570 +};
571 +
572 +struct rt2880_pmx_group {
573 + const char *name;
574 + int enabled;
575 +
576 + const u32 shift;
577 + const char mask;
578 + const char gpio;
579 +
580 + struct rt2880_pmx_func *func;
581 + int func_count;
582 +};
583 +
584 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
585 +
586 +#endif
587 Index: linux-3.10.17/arch/mips/ralink/mt7620.c
588 ===================================================================
589 --- linux-3.10.17.orig/arch/mips/ralink/mt7620.c 2013-10-26 17:19:49.462708921 +0200
590 +++ linux-3.10.17/arch/mips/ralink/mt7620.c 2013-10-27 13:33:02.148512122 +0100
591 @@ -17,6 +17,7 @@
592 #include <asm/mipsregs.h>
593 #include <asm/mach-ralink/ralink_regs.h>
594 #include <asm/mach-ralink/mt7620.h>
595 +#include <asm/mach-ralink/pinmux.h>
596
597 #include "common.h"
598
599 @@ -48,118 +49,58 @@
600 /* the pll dividers */
601 static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
602
603 -static struct ralink_pinmux_grp mode_mux[] = {
604 - {
605 - .name = "i2c",
606 - .mask = MT7620_GPIO_MODE_I2C,
607 - .gpio_first = 1,
608 - .gpio_last = 2,
609 - }, {
610 - .name = "spi",
611 - .mask = MT7620_GPIO_MODE_SPI,
612 - .gpio_first = 3,
613 - .gpio_last = 6,
614 - }, {
615 - .name = "uartlite",
616 - .mask = MT7620_GPIO_MODE_UART1,
617 - .gpio_first = 15,
618 - .gpio_last = 16,
619 - }, {
620 - .name = "wdt",
621 - .mask = MT7620_GPIO_MODE_WDT,
622 - .gpio_first = 17,
623 - .gpio_last = 17,
624 - }, {
625 - .name = "mdio",
626 - .mask = MT7620_GPIO_MODE_MDIO,
627 - .gpio_first = 22,
628 - .gpio_last = 23,
629 - }, {
630 - .name = "rgmii1",
631 - .mask = MT7620_GPIO_MODE_RGMII1,
632 - .gpio_first = 24,
633 - .gpio_last = 35,
634 - }, {
635 - .name = "spi refclk",
636 - .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
637 - .gpio_first = 37,
638 - .gpio_last = 39,
639 - }, {
640 - .name = "jtag",
641 - .mask = MT7620_GPIO_MODE_JTAG,
642 - .gpio_first = 40,
643 - .gpio_last = 44,
644 - }, {
645 - /* shared lines with jtag */
646 - .name = "ephy",
647 - .mask = MT7620_GPIO_MODE_EPHY,
648 - .gpio_first = 40,
649 - .gpio_last = 44,
650 - }, {
651 - .name = "nand",
652 - .mask = MT7620_GPIO_MODE_JTAG,
653 - .gpio_first = 45,
654 - .gpio_last = 59,
655 - }, {
656 - .name = "rgmii2",
657 - .mask = MT7620_GPIO_MODE_RGMII2,
658 - .gpio_first = 60,
659 - .gpio_last = 71,
660 - }, {
661 - .name = "wled",
662 - .mask = MT7620_GPIO_MODE_WLED,
663 - .gpio_first = 72,
664 - .gpio_last = 72,
665 - }, {0}
666 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
667 +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
668 +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
669 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
670 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
671 +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
672 +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
673 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
674 +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
675 +static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
676 +static struct rt2880_pmx_func uartf_grp[] = {
677 + FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
678 + FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
679 + FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
680 + FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
681 + FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
682 + FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
683 + FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
684 };
685 -
686 -static struct ralink_pinmux_grp uart_mux[] = {
687 - {
688 - .name = "uartf",
689 - .mask = MT7620_GPIO_MODE_UARTF,
690 - .gpio_first = 7,
691 - .gpio_last = 14,
692 - }, {
693 - .name = "pcm uartf",
694 - .mask = MT7620_GPIO_MODE_PCM_UARTF,
695 - .gpio_first = 7,
696 - .gpio_last = 14,
697 - }, {
698 - .name = "pcm i2s",
699 - .mask = MT7620_GPIO_MODE_PCM_I2S,
700 - .gpio_first = 7,
701 - .gpio_last = 14,
702 - }, {
703 - .name = "i2s uartf",
704 - .mask = MT7620_GPIO_MODE_I2S_UARTF,
705 - .gpio_first = 7,
706 - .gpio_last = 14,
707 - }, {
708 - .name = "pcm gpio",
709 - .mask = MT7620_GPIO_MODE_PCM_GPIO,
710 - .gpio_first = 11,
711 - .gpio_last = 14,
712 - }, {
713 - .name = "gpio uartf",
714 - .mask = MT7620_GPIO_MODE_GPIO_UARTF,
715 - .gpio_first = 7,
716 - .gpio_last = 10,
717 - }, {
718 - .name = "gpio i2s",
719 - .mask = MT7620_GPIO_MODE_GPIO_I2S,
720 - .gpio_first = 7,
721 - .gpio_last = 10,
722 - }, {
723 - .name = "gpio",
724 - .mask = MT7620_GPIO_MODE_GPIO,
725 - }, {0}
726 +static struct rt2880_pmx_func wdt_grp[] = {
727 + FUNC("wdt rst", 0, 17, 1),
728 + FUNC("wdt refclk", 0, 17, 1),
729 + };
730 +static struct rt2880_pmx_func pcie_rst_grp[] = {
731 + FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
732 + FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
733 +};
734 +static struct rt2880_pmx_func nd_sd_grp[] = {
735 + FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
736 + FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
737 };
738
739 -struct ralink_pinmux rt_gpio_pinmux = {
740 - .mode = mode_mux,
741 - .uart = uart_mux,
742 - .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
743 - .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
744 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
745 + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
746 + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
747 + MT7620_GPIO_MODE_UART0_SHIFT),
748 + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
749 + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
750 + GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
751 + MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
752 + GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
753 + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
754 + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
755 + GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
756 + MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
757 + GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
758 + MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
759 + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
760 + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
761 + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
762 + GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
763 + { 0 }
764 };
765
766 void __init ralink_clk_init(void)
767 @@ -281,4 +222,6 @@
768 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
769 pr_info("Digital PMU set to %s control\n",
770 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
771 +
772 + rt2880_pinmux_data = mt7620a_pinmux_data;
773 }
774 Index: linux-3.10.17/arch/mips/ralink/rt305x.c
775 ===================================================================
776 --- linux-3.10.17.orig/arch/mips/ralink/rt305x.c 2013-10-26 17:19:49.722708926 +0200
777 +++ linux-3.10.17/arch/mips/ralink/rt305x.c 2013-10-27 16:23:29.836755834 +0100
778 @@ -17,90 +17,71 @@
779 #include <asm/mipsregs.h>
780 #include <asm/mach-ralink/ralink_regs.h>
781 #include <asm/mach-ralink/rt305x.h>
782 +#include <asm/mach-ralink/pinmux.h>
783
784 #include "common.h"
785
786 enum rt305x_soc_type rt305x_soc;
787
788 -static struct ralink_pinmux_grp mode_mux[] = {
789 - {
790 - .name = "i2c",
791 - .mask = RT305X_GPIO_MODE_I2C,
792 - .gpio_first = RT305X_GPIO_I2C_SD,
793 - .gpio_last = RT305X_GPIO_I2C_SCLK,
794 - }, {
795 - .name = "spi",
796 - .mask = RT305X_GPIO_MODE_SPI,
797 - .gpio_first = RT305X_GPIO_SPI_EN,
798 - .gpio_last = RT305X_GPIO_SPI_CLK,
799 - }, {
800 - .name = "uartlite",
801 - .mask = RT305X_GPIO_MODE_UART1,
802 - .gpio_first = RT305X_GPIO_UART1_TXD,
803 - .gpio_last = RT305X_GPIO_UART1_RXD,
804 - }, {
805 - .name = "jtag",
806 - .mask = RT305X_GPIO_MODE_JTAG,
807 - .gpio_first = RT305X_GPIO_JTAG_TDO,
808 - .gpio_last = RT305X_GPIO_JTAG_TDI,
809 - }, {
810 - .name = "mdio",
811 - .mask = RT305X_GPIO_MODE_MDIO,
812 - .gpio_first = RT305X_GPIO_MDIO_MDC,
813 - .gpio_last = RT305X_GPIO_MDIO_MDIO,
814 - }, {
815 - .name = "sdram",
816 - .mask = RT305X_GPIO_MODE_SDRAM,
817 - .gpio_first = RT305X_GPIO_SDRAM_MD16,
818 - .gpio_last = RT305X_GPIO_SDRAM_MD31,
819 - }, {
820 - .name = "rgmii",
821 - .mask = RT305X_GPIO_MODE_RGMII,
822 - .gpio_first = RT305X_GPIO_GE0_TXD0,
823 - .gpio_last = RT305X_GPIO_GE0_RXCLK,
824 - }, {0}
825 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
826 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
827 +static struct rt2880_pmx_func uartf_func[] = {
828 + FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
829 + FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
830 + FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
831 + FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
832 + FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
833 + FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
834 + FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
835 +};
836 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
837 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
838 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
839 +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
840 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
841 +static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
842 +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
843 +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
844 +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
845 +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
846 +
847 +static struct rt2880_pmx_group rt3050_pinmux_data[] = {
848 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
849 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
850 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
851 + RT305X_GPIO_MODE_UART0_SHIFT),
852 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
853 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
854 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
855 + GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
856 + GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
857 + { 0 }
858 +};
859 +
860 +static struct rt2880_pmx_group rt3352_pinmux_data[] = {
861 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
862 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
863 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
864 + RT305X_GPIO_MODE_UART0_SHIFT),
865 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
866 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
867 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
868 + GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
869 + GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
870 + GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
871 + GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
872 + { 0 }
873 };
874
875 -static struct ralink_pinmux_grp uart_mux[] = {
876 - {
877 - .name = "uartf",
878 - .mask = RT305X_GPIO_MODE_UARTF,
879 - .gpio_first = RT305X_GPIO_7,
880 - .gpio_last = RT305X_GPIO_14,
881 - }, {
882 - .name = "pcm uartf",
883 - .mask = RT305X_GPIO_MODE_PCM_UARTF,
884 - .gpio_first = RT305X_GPIO_7,
885 - .gpio_last = RT305X_GPIO_14,
886 - }, {
887 - .name = "pcm i2s",
888 - .mask = RT305X_GPIO_MODE_PCM_I2S,
889 - .gpio_first = RT305X_GPIO_7,
890 - .gpio_last = RT305X_GPIO_14,
891 - }, {
892 - .name = "i2s uartf",
893 - .mask = RT305X_GPIO_MODE_I2S_UARTF,
894 - .gpio_first = RT305X_GPIO_7,
895 - .gpio_last = RT305X_GPIO_14,
896 - }, {
897 - .name = "pcm gpio",
898 - .mask = RT305X_GPIO_MODE_PCM_GPIO,
899 - .gpio_first = RT305X_GPIO_10,
900 - .gpio_last = RT305X_GPIO_14,
901 - }, {
902 - .name = "gpio uartf",
903 - .mask = RT305X_GPIO_MODE_GPIO_UARTF,
904 - .gpio_first = RT305X_GPIO_7,
905 - .gpio_last = RT305X_GPIO_10,
906 - }, {
907 - .name = "gpio i2s",
908 - .mask = RT305X_GPIO_MODE_GPIO_I2S,
909 - .gpio_first = RT305X_GPIO_7,
910 - .gpio_last = RT305X_GPIO_10,
911 - }, {
912 - .name = "gpio",
913 - .mask = RT305X_GPIO_MODE_GPIO,
914 - }, {0}
915 +static struct rt2880_pmx_group rt5350_pinmux_data[] = {
916 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
917 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
918 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
919 + RT305X_GPIO_MODE_UART0_SHIFT),
920 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
921 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
922 + GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
923 + { 0 }
924 };
925
926 static void rt305x_wdt_reset(void)
927 @@ -114,14 +95,6 @@
928 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
929 }
930
931 -struct ralink_pinmux rt_gpio_pinmux = {
932 - .mode = mode_mux,
933 - .uart = uart_mux,
934 - .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
935 - .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
936 - .wdt_reset = rt305x_wdt_reset,
937 -};
938 -
939 static unsigned long rt5350_get_mem_size(void)
940 {
941 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
942 @@ -291,11 +264,14 @@
943 soc_info->mem_base = RT305X_SDRAM_BASE;
944 if (soc_is_rt5350()) {
945 soc_info->mem_size = rt5350_get_mem_size();
946 + rt2880_pinmux_data = rt5350_pinmux_data;
947 } else if (soc_is_rt305x() || soc_is_rt3350()) {
948 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
949 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
950 + rt2880_pinmux_data = rt3050_pinmux_data;
951 } else if (soc_is_rt3352()) {
952 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
953 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
954 + rt2880_pinmux_data = rt3352_pinmux_data;
955 }
956 }
957 Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/rt305x.h
958 ===================================================================
959 --- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/rt305x.h 2013-10-18 19:44:19.000000000 +0200
960 +++ linux-3.10.17/arch/mips/include/asm/mach-ralink/rt305x.h 2013-10-26 17:19:49.934708931 +0200
961 @@ -125,24 +125,28 @@
962 #define RT305X_GPIO_GE0_TXD0 40
963 #define RT305X_GPIO_GE0_RXCLK 51
964
965 -#define RT305X_GPIO_MODE_I2C BIT(0)
966 -#define RT305X_GPIO_MODE_SPI BIT(1)
967 #define RT305X_GPIO_MODE_UART0_SHIFT 2
968 #define RT305X_GPIO_MODE_UART0_MASK 0x7
969 #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
970 -#define RT305X_GPIO_MODE_UARTF 0x0
971 -#define RT305X_GPIO_MODE_PCM_UARTF 0x1
972 -#define RT305X_GPIO_MODE_PCM_I2S 0x2
973 -#define RT305X_GPIO_MODE_I2S_UARTF 0x3
974 -#define RT305X_GPIO_MODE_PCM_GPIO 0x4
975 -#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
976 -#define RT305X_GPIO_MODE_GPIO_I2S 0x6
977 -#define RT305X_GPIO_MODE_GPIO 0x7
978 -#define RT305X_GPIO_MODE_UART1 BIT(5)
979 -#define RT305X_GPIO_MODE_JTAG BIT(6)
980 -#define RT305X_GPIO_MODE_MDIO BIT(7)
981 -#define RT305X_GPIO_MODE_SDRAM BIT(8)
982 -#define RT305X_GPIO_MODE_RGMII BIT(9)
983 +#define RT305X_GPIO_MODE_UARTF 0
984 +#define RT305X_GPIO_MODE_PCM_UARTF 1
985 +#define RT305X_GPIO_MODE_PCM_I2S 2
986 +#define RT305X_GPIO_MODE_I2S_UARTF 3
987 +#define RT305X_GPIO_MODE_PCM_GPIO 4
988 +#define RT305X_GPIO_MODE_GPIO_UARTF 5
989 +#define RT305X_GPIO_MODE_GPIO_I2S 6
990 +#define RT305X_GPIO_MODE_GPIO 7
991 +
992 +#define RT305X_GPIO_MODE_I2C 0
993 +#define RT305X_GPIO_MODE_SPI 1
994 +#define RT305X_GPIO_MODE_UART1 5
995 +#define RT305X_GPIO_MODE_JTAG 6
996 +#define RT305X_GPIO_MODE_MDIO 7
997 +#define RT305X_GPIO_MODE_SDRAM 8
998 +#define RT305X_GPIO_MODE_RGMII 9
999 +#define RT5350_GPIO_MODE_PHY_LED 14
1000 +#define RT3352_GPIO_MODE_LNA 18
1001 +#define RT3352_GPIO_MODE_PA 20
1002
1003 #define RT3352_SYSC_REG_SYSCFG0 0x010
1004 #define RT3352_SYSC_REG_SYSCFG1 0x014
1005 Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h
1006 ===================================================================
1007 --- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/mt7620.h 2013-10-26 17:19:49.250708916 +0200
1008 +++ linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h 2013-10-27 13:13:24.892484072 +0100
1009 @@ -59,7 +59,6 @@
1010 #define MT7620_DDR2_SIZE_MIN 32
1011 #define MT7620_DDR2_SIZE_MAX 256
1012
1013 -#define MT7620_GPIO_MODE_I2C BIT(0)
1014 #define MT7620_GPIO_MODE_UART0_SHIFT 2
1015 #define MT7620_GPIO_MODE_UART0_MASK 0x7
1016 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
1017 @@ -71,15 +70,35 @@
1018 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
1019 #define MT7620_GPIO_MODE_GPIO_I2S 0x6
1020 #define MT7620_GPIO_MODE_GPIO 0x7
1021 -#define MT7620_GPIO_MODE_UART1 BIT(5)
1022 -#define MT7620_GPIO_MODE_MDIO BIT(8)
1023 -#define MT7620_GPIO_MODE_RGMII1 BIT(9)
1024 -#define MT7620_GPIO_MODE_RGMII2 BIT(10)
1025 -#define MT7620_GPIO_MODE_SPI BIT(11)
1026 -#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
1027 -#define MT7620_GPIO_MODE_WLED BIT(13)
1028 -#define MT7620_GPIO_MODE_JTAG BIT(15)
1029 -#define MT7620_GPIO_MODE_EPHY BIT(15)
1030 -#define MT7620_GPIO_MODE_WDT BIT(22)
1031 +
1032 +#define MT7620_GPIO_MODE_NAND 0
1033 +#define MT7620_GPIO_MODE_SD 1
1034 +#define MT7620_GPIO_MODE_ND_SD_GPIO 2
1035 +#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
1036 +#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
1037 +
1038 +#define MT7620_GPIO_MODE_PCIE_RST 0
1039 +#define MT7620_GPIO_MODE_PCIE_REF 1
1040 +#define MT7620_GPIO_MODE_PCIE_GPIO 2
1041 +#define MT7620_GPIO_MODE_PCIE_MASK 0x3
1042 +#define MT7620_GPIO_MODE_PCIE_SHIFT 16
1043 +
1044 +#define MT7620_GPIO_MODE_WDT_RST 0
1045 +#define MT7620_GPIO_MODE_WDT_REF 1
1046 +#define MT7620_GPIO_MODE_WDT_GPIO 2
1047 +#define MT7620_GPIO_MODE_WDT_MASK 0x3
1048 +#define MT7620_GPIO_MODE_WDT_SHIFT 21
1049 +
1050 +#define MT7620_GPIO_MODE_I2C 0
1051 +#define MT7620_GPIO_MODE_UART1 5
1052 +#define MT7620_GPIO_MODE_MDIO 8
1053 +#define MT7620_GPIO_MODE_RGMII1 9
1054 +#define MT7620_GPIO_MODE_RGMII2 10
1055 +#define MT7620_GPIO_MODE_SPI 11
1056 +#define MT7620_GPIO_MODE_SPI_REF_CLK 12
1057 +#define MT7620_GPIO_MODE_WLED 13
1058 +#define MT7620_GPIO_MODE_JTAG 15
1059 +#define MT7620_GPIO_MODE_EPHY 15
1060 +#define MT7620_GPIO_MODE_PA 20
1061
1062 #endif
1063 Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/rt3883.h
1064 ===================================================================
1065 --- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/rt3883.h 2013-10-18 19:44:19.000000000 +0200
1066 +++ linux-3.10.17/arch/mips/include/asm/mach-ralink/rt3883.h 2013-10-26 17:19:49.934708931 +0200
1067 @@ -112,8 +112,6 @@
1068 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
1069 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
1070
1071 -#define RT3883_GPIO_MODE_I2C BIT(0)
1072 -#define RT3883_GPIO_MODE_SPI BIT(1)
1073 #define RT3883_GPIO_MODE_UART0_SHIFT 2
1074 #define RT3883_GPIO_MODE_UART0_MASK 0x7
1075 #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
1076 @@ -125,11 +123,15 @@
1077 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
1078 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
1079 #define RT3883_GPIO_MODE_GPIO 0x7
1080 -#define RT3883_GPIO_MODE_UART1 BIT(5)
1081 -#define RT3883_GPIO_MODE_JTAG BIT(6)
1082 -#define RT3883_GPIO_MODE_MDIO BIT(7)
1083 -#define RT3883_GPIO_MODE_GE1 BIT(9)
1084 -#define RT3883_GPIO_MODE_GE2 BIT(10)
1085 +
1086 +#define RT3883_GPIO_MODE_I2C 0
1087 +#define RT3883_GPIO_MODE_SPI 1
1088 +#define RT3883_GPIO_MODE_UART1 5
1089 +#define RT3883_GPIO_MODE_JTAG 6
1090 +#define RT3883_GPIO_MODE_MDIO 7
1091 +#define RT3883_GPIO_MODE_GE1 9
1092 +#define RT3883_GPIO_MODE_GE2 10
1093 +
1094 #define RT3883_GPIO_MODE_PCI_SHIFT 11
1095 #define RT3883_GPIO_MODE_PCI_MASK 0x7
1096 #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
1097 Index: linux-3.10.17/arch/mips/ralink/common.h
1098 ===================================================================
1099 --- linux-3.10.17.orig/arch/mips/ralink/common.h 2013-10-26 17:19:49.094708911 +0200
1100 +++ linux-3.10.17/arch/mips/ralink/common.h 2013-10-26 17:19:49.934708931 +0200
1101 @@ -11,25 +11,6 @@
1102
1103 #define RAMIPS_SYS_TYPE_LEN 32
1104
1105 -struct ralink_pinmux_grp {
1106 - const char *name;
1107 - u32 mask;
1108 - int gpio_first;
1109 - int gpio_last;
1110 -};
1111 -
1112 -struct ralink_pinmux {
1113 - struct ralink_pinmux_grp *mode;
1114 - struct ralink_pinmux_grp *uart;
1115 - int uart_shift;
1116 - u32 uart_mask;
1117 - void (*wdt_reset)(void);
1118 - struct ralink_pinmux_grp *pci;
1119 - int pci_shift;
1120 - u32 pci_mask;
1121 -};
1122 -extern struct ralink_pinmux rt_gpio_pinmux;
1123 -
1124 struct ralink_soc_info {
1125 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
1126 unsigned char *compatible;
1127 Index: linux-3.10.17/arch/mips/ralink/rt3883.c
1128 ===================================================================
1129 --- linux-3.10.17.orig/arch/mips/ralink/rt3883.c 2013-10-18 19:44:19.000000000 +0200
1130 +++ linux-3.10.17/arch/mips/ralink/rt3883.c 2013-10-27 16:23:36.824756002 +0100
1131 @@ -17,132 +17,50 @@
1132 #include <asm/mipsregs.h>
1133 #include <asm/mach-ralink/ralink_regs.h>
1134 #include <asm/mach-ralink/rt3883.h>
1135 +#include <asm/mach-ralink/pinmux.h>
1136
1137 #include "common.h"
1138
1139 -static struct ralink_pinmux_grp mode_mux[] = {
1140 - {
1141 - .name = "i2c",
1142 - .mask = RT3883_GPIO_MODE_I2C,
1143 - .gpio_first = RT3883_GPIO_I2C_SD,
1144 - .gpio_last = RT3883_GPIO_I2C_SCLK,
1145 - }, {
1146 - .name = "spi",
1147 - .mask = RT3883_GPIO_MODE_SPI,
1148 - .gpio_first = RT3883_GPIO_SPI_CS0,
1149 - .gpio_last = RT3883_GPIO_SPI_MISO,
1150 - }, {
1151 - .name = "uartlite",
1152 - .mask = RT3883_GPIO_MODE_UART1,
1153 - .gpio_first = RT3883_GPIO_UART1_TXD,
1154 - .gpio_last = RT3883_GPIO_UART1_RXD,
1155 - }, {
1156 - .name = "jtag",
1157 - .mask = RT3883_GPIO_MODE_JTAG,
1158 - .gpio_first = RT3883_GPIO_JTAG_TDO,
1159 - .gpio_last = RT3883_GPIO_JTAG_TCLK,
1160 - }, {
1161 - .name = "mdio",
1162 - .mask = RT3883_GPIO_MODE_MDIO,
1163 - .gpio_first = RT3883_GPIO_MDIO_MDC,
1164 - .gpio_last = RT3883_GPIO_MDIO_MDIO,
1165 - }, {
1166 - .name = "ge1",
1167 - .mask = RT3883_GPIO_MODE_GE1,
1168 - .gpio_first = RT3883_GPIO_GE1_TXD0,
1169 - .gpio_last = RT3883_GPIO_GE1_RXCLK,
1170 - }, {
1171 - .name = "ge2",
1172 - .mask = RT3883_GPIO_MODE_GE2,
1173 - .gpio_first = RT3883_GPIO_GE2_TXD0,
1174 - .gpio_last = RT3883_GPIO_GE2_RXCLK,
1175 - }, {
1176 - .name = "pci",
1177 - .mask = RT3883_GPIO_MODE_PCI,
1178 - .gpio_first = RT3883_GPIO_PCI_AD0,
1179 - .gpio_last = RT3883_GPIO_PCI_AD31,
1180 - }, {
1181 - .name = "lna a",
1182 - .mask = RT3883_GPIO_MODE_LNA_A,
1183 - .gpio_first = RT3883_GPIO_LNA_PE_A0,
1184 - .gpio_last = RT3883_GPIO_LNA_PE_A2,
1185 - }, {
1186 - .name = "lna g",
1187 - .mask = RT3883_GPIO_MODE_LNA_G,
1188 - .gpio_first = RT3883_GPIO_LNA_PE_G0,
1189 - .gpio_last = RT3883_GPIO_LNA_PE_G2,
1190 - }, {0}
1191 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
1192 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
1193 +static struct rt2880_pmx_func uartf_func[] = {
1194 + FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
1195 + FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
1196 + FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
1197 + FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
1198 + FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
1199 + FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
1200 + FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
1201 };
1202 -
1203 -static struct ralink_pinmux_grp uart_mux[] = {
1204 - {
1205 - .name = "uartf",
1206 - .mask = RT3883_GPIO_MODE_UARTF,
1207 - .gpio_first = RT3883_GPIO_7,
1208 - .gpio_last = RT3883_GPIO_14,
1209 - }, {
1210 - .name = "pcm uartf",
1211 - .mask = RT3883_GPIO_MODE_PCM_UARTF,
1212 - .gpio_first = RT3883_GPIO_7,
1213 - .gpio_last = RT3883_GPIO_14,
1214 - }, {
1215 - .name = "pcm i2s",
1216 - .mask = RT3883_GPIO_MODE_PCM_I2S,
1217 - .gpio_first = RT3883_GPIO_7,
1218 - .gpio_last = RT3883_GPIO_14,
1219 - }, {
1220 - .name = "i2s uartf",
1221 - .mask = RT3883_GPIO_MODE_I2S_UARTF,
1222 - .gpio_first = RT3883_GPIO_7,
1223 - .gpio_last = RT3883_GPIO_14,
1224 - }, {
1225 - .name = "pcm gpio",
1226 - .mask = RT3883_GPIO_MODE_PCM_GPIO,
1227 - .gpio_first = RT3883_GPIO_11,
1228 - .gpio_last = RT3883_GPIO_14,
1229 - }, {
1230 - .name = "gpio uartf",
1231 - .mask = RT3883_GPIO_MODE_GPIO_UARTF,
1232 - .gpio_first = RT3883_GPIO_7,
1233 - .gpio_last = RT3883_GPIO_10,
1234 - }, {
1235 - .name = "gpio i2s",
1236 - .mask = RT3883_GPIO_MODE_GPIO_I2S,
1237 - .gpio_first = RT3883_GPIO_7,
1238 - .gpio_last = RT3883_GPIO_10,
1239 - }, {
1240 - .name = "gpio",
1241 - .mask = RT3883_GPIO_MODE_GPIO,
1242 - }, {0}
1243 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
1244 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
1245 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
1246 +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
1247 +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
1248 +static struct rt2880_pmx_func pci_func[] = {
1249 + FUNC("pci-dev", 0, 40, 32),
1250 + FUNC("pci-host2", 1, 40, 32),
1251 + FUNC("pci-host1", 2, 40, 32),
1252 + FUNC("pci-fnc", 3, 40, 32)
1253 };
1254 +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
1255 +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
1256
1257 -static struct ralink_pinmux_grp pci_mux[] = {
1258 - {
1259 - .name = "pci-dev",
1260 - .mask = 0,
1261 - .gpio_first = RT3883_GPIO_PCI_AD0,
1262 - .gpio_last = RT3883_GPIO_PCI_AD31,
1263 - }, {
1264 - .name = "pci-host2",
1265 - .mask = 1,
1266 - .gpio_first = RT3883_GPIO_PCI_AD0,
1267 - .gpio_last = RT3883_GPIO_PCI_AD31,
1268 - }, {
1269 - .name = "pci-host1",
1270 - .mask = 2,
1271 - .gpio_first = RT3883_GPIO_PCI_AD0,
1272 - .gpio_last = RT3883_GPIO_PCI_AD31,
1273 - }, {
1274 - .name = "pci-fnc",
1275 - .mask = 3,
1276 - .gpio_first = RT3883_GPIO_PCI_AD0,
1277 - .gpio_last = RT3883_GPIO_PCI_AD31,
1278 - }, {
1279 - .name = "pci-gpio",
1280 - .mask = 7,
1281 - .gpio_first = RT3883_GPIO_PCI_AD0,
1282 - .gpio_last = RT3883_GPIO_PCI_AD31,
1283 - }, {0}
1284 +static struct rt2880_pmx_group rt3883_pinmux_data[] = {
1285 + GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
1286 + GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
1287 + GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
1288 + RT3883_GPIO_MODE_UART0_SHIFT),
1289 + GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
1290 + GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
1291 + GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
1292 + GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
1293 + GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
1294 + GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
1295 + RT3883_GPIO_MODE_PCI_SHIFT),
1296 + GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
1297 + GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
1298 + { 0 }
1299 };
1300
1301 static void rt3883_wdt_reset(void)
1302 @@ -155,17 +73,6 @@
1303 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
1304 }
1305
1306 -struct ralink_pinmux rt_gpio_pinmux = {
1307 - .mode = mode_mux,
1308 - .uart = uart_mux,
1309 - .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
1310 - .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
1311 - .wdt_reset = rt3883_wdt_reset,
1312 - .pci = pci_mux,
1313 - .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
1314 - .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
1315 -};
1316 -
1317 void __init ralink_clk_init(void)
1318 {
1319 unsigned long cpu_rate, sys_rate;
1320 @@ -243,4 +150,6 @@
1321 soc_info->mem_base = RT3883_SDRAM_BASE;
1322 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
1323 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
1324 +
1325 + rt2880_pinmux_data = rt3883_pinmux_data;
1326 }
OpenWrt Source Repository