target/linux/ramips/patches-3.10/0202-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch

   1 From 46b62174f655edf6a4befae7f9871c431146b1b6 Mon Sep 17 00:00:00 2001
   2 From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
   3 Date: Wed, 11 Sep 2013 14:17:47 -0500
   4 Subject: [PATCH 202/215] MIPS: Fix SMP core calculations when using MT
   5  support.
   6
   7 The TCBIND register is only available if the core has MT support. It
   8 should not be read otherwise. Secondly, the number of TCs (siblings)
   9 are calculated differently depending on if the kernel is configured
  10 as SMVP or SMTC.
  11
  12 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
  13 Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
  14 Cc: linux-mips@linux-mips.org
  15 Patchwork: https://patchwork.linux-mips.org/patch/5822/
  16 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  17 (cherry picked from commit 670bac3a8c201fc1f5f92ac6b4a8b42dc8172937)
  18 ---
  19  arch/mips/kernel/smp-cmp.c |   13 +++++++++++--
  20  1 file changed, 11 insertions(+), 2 deletions(-)
  21
  22 --- a/arch/mips/kernel/smp-cmp.c
  23 +++ b/arch/mips/kernel/smp-cmp.c
  24 @@ -99,7 +99,9 @@ static void cmp_init_secondary(void)
  25
  26         c->core = (read_c0_ebase() >> 1) & 0x1ff;
  27  #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
  28 -       c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE;
  29 +       if (cpu_has_mipsmt)
  30 +               c->vpe_id = (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
  31 +                       TCBIND_CURVPE;
  32  #endif
  33  #ifdef CONFIG_MIPS_MT_SMTC
  34         c->tc_id  = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT;
  35 @@ -177,9 +179,16 @@ void __init cmp_smp_setup(void)
  36         }
  37
  38         if (cpu_has_mipsmt) {
  39 -               unsigned int nvpe, mvpconf0 = read_c0_mvpconf0();
  40 +               unsigned int nvpe = 1;
  41 +#ifdef CONFIG_MIPS_MT_SMP
  42 +               unsigned int mvpconf0 = read_c0_mvpconf0();
  43 +
  44 +               nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
  45 +#elif defined(CONFIG_MIPS_MT_SMTC)
  46 +               unsigned int mvpconf0 = read_c0_mvpconf0();
  47
  48                 nvpe = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
  49 +#endif
  50                 smp_num_siblings = nvpe;
  51         }
  52         pr_info("Detected %i available secondary CPU(s)\n", ncpu);