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ramips: improve ralink ethernet driver
[openwrt/openwrt.git] / target / linux / ramips / patches-3.14 / 0035-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
1 From c55d6cf3e2c593bf7d228c6532ec9bd8da82e09d Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 35/57] NET: MIPS: add ralink SoC ethernet driver
5
6 Add support for Ralink FE and ESW.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ralink/Kconfig | 32 +
15 drivers/net/ethernet/ralink/Makefile | 18 +
16 drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
17 drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
18 drivers/net/ethernet/ralink/gsw_mt7620a.c | 566 ++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.h | 30 +
20 drivers/net/ethernet/ralink/mdio.c | 244 ++++
21 drivers/net/ethernet/ralink/mdio.h | 29 +
22 drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
23 drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
24 drivers/net/ethernet/ralink/mt7530.c | 579 ++++++++
25 drivers/net/ethernet/ralink/mt7530.h | 20 +
26 drivers/net/ethernet/ralink/ralink_soc_eth.c | 844 +++++++++++
27 drivers/net/ethernet/ralink/ralink_soc_eth.h | 384 +++++
28 drivers/net/ethernet/ralink/soc_mt7620.c | 172 +++
29 drivers/net/ethernet/ralink/soc_rt2880.c | 52 +
30 drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
31 drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
32 22 files changed, 4926 insertions(+)
33 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
34 create mode 100644 drivers/net/ethernet/ralink/Kconfig
35 create mode 100644 drivers/net/ethernet/ralink/Makefile
36 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
37 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
38 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
39 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
40 create mode 100644 drivers/net/ethernet/ralink/mdio.c
41 create mode 100644 drivers/net/ethernet/ralink/mdio.h
42 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
43 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
44 create mode 100644 drivers/net/ethernet/ralink/mt7530.c
45 create mode 100644 drivers/net/ethernet/ralink/mt7530.h
46 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
47 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
48 create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
49 create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
50 create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
51 create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
52
53 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
54 ===================================================================
55 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
56 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h 2014-10-29 20:25:55.429357372 +0100
57 @@ -0,0 +1,27 @@
58 +/*
59 + * Ralink RT305x SoC platform device registration
60 + *
61 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
62 + *
63 + * This program is free software; you can redistribute it and/or modify it
64 + * under the terms of the GNU General Public License version 2 as published
65 + * by the Free Software Foundation.
66 + */
67 +
68 +#ifndef _RT305X_ESW_PLATFORM_H
69 +#define _RT305X_ESW_PLATFORM_H
70 +
71 +enum {
72 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
73 + RT305X_ESW_VLAN_CONFIG_LLLLW,
74 + RT305X_ESW_VLAN_CONFIG_WLLLL,
75 +};
76 +
77 +struct rt305x_esw_platform_data
78 +{
79 + u8 vlan_config;
80 + u32 reg_initval_fct2;
81 + u32 reg_initval_fpa2;
82 +};
83 +
84 +#endif /* _RT305X_ESW_PLATFORM_H */
85 Index: linux-3.14.18/arch/mips/ralink/rt305x.c
86 ===================================================================
87 --- linux-3.14.18.orig/arch/mips/ralink/rt305x.c 2014-10-29 20:25:55.377355456 +0100
88 +++ linux-3.14.18/arch/mips/ralink/rt305x.c 2014-10-29 20:25:55.433357519 +0100
89 @@ -199,6 +199,7 @@
90 }
91
92 ralink_clk_add("cpu", cpu_rate);
93 + ralink_clk_add("sys", sys_rate);
94 ralink_clk_add("10000b00.spi", sys_rate);
95 ralink_clk_add("10000100.timer", wdt_rate);
96 ralink_clk_add("10000120.watchdog", wdt_rate);
97 Index: linux-3.14.18/drivers/net/ethernet/Kconfig
98 ===================================================================
99 --- linux-3.14.18.orig/drivers/net/ethernet/Kconfig 2014-09-06 01:34:59.000000000 +0200
100 +++ linux-3.14.18/drivers/net/ethernet/Kconfig 2014-10-29 20:39:55.156284038 +0100
101 @@ -134,6 +134,7 @@
102 source "drivers/net/ethernet/packetengines/Kconfig"
103 source "drivers/net/ethernet/pasemi/Kconfig"
104 source "drivers/net/ethernet/qlogic/Kconfig"
105 +source "drivers/net/ethernet/ralink/Kconfig"
106 source "drivers/net/ethernet/realtek/Kconfig"
107 source "drivers/net/ethernet/renesas/Kconfig"
108 source "drivers/net/ethernet/rdc/Kconfig"
109 Index: linux-3.14.18/drivers/net/ethernet/Makefile
110 ===================================================================
111 --- linux-3.14.18.orig/drivers/net/ethernet/Makefile 2014-09-06 01:34:59.000000000 +0200
112 +++ linux-3.14.18/drivers/net/ethernet/Makefile 2014-10-29 20:39:55.156284038 +0100
113 @@ -56,6 +56,7 @@
114 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
115 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
116 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
117 +obj-$(CONFIG_NET_RALINK) += ralink/
118 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
119 obj-$(CONFIG_SH_ETH) += renesas/
120 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
121 Index: linux-3.14.18/drivers/net/ethernet/ralink/Kconfig
122 ===================================================================
123 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
124 +++ linux-3.14.18/drivers/net/ethernet/ralink/Kconfig 2014-10-29 20:25:55.433357519 +0100
125 @@ -0,0 +1,31 @@
126 +config NET_RALINK
127 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
128 + depends on RALINK
129 + help
130 + This driver supports the ethernet mac inside the ralink wisocs
131 +
132 +if NET_RALINK
133 +
134 +config NET_RALINK_MDIO
135 + def_bool NET_RALINK
136 + depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
137 + select PHYLIB
138 +
139 +config NET_RALINK_MDIO_RT2880
140 + def_bool NET_RALINK
141 + depends on (SOC_RT288X || SOC_RT3883)
142 + select NET_RALINK_MDIO
143 +
144 +config NET_RALINK_ESW_RT3052
145 + def_bool NET_RALINK
146 + depends on SOC_RT305X
147 + select PHYLIB
148 + select SWCONFIG
149 +
150 +config NET_RALINK_GSW_MT7620
151 + def_bool NET_RALINK
152 + depends on SOC_MT7620
153 + select NET_RALINK_MDIO
154 + select PHYLIB
155 + select SWCONFIG
156 +endif
157 Index: linux-3.14.18/drivers/net/ethernet/ralink/Makefile
158 ===================================================================
159 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
160 +++ linux-3.14.18/drivers/net/ethernet/ralink/Makefile 2014-10-29 20:25:55.433357519 +0100
161 @@ -0,0 +1,18 @@
162 +#
163 +# Makefile for the Ralink SoCs built-in ethernet macs
164 +#
165 +
166 +ralink-eth-y += ralink_soc_eth.o ralink_ethtool.o
167 +
168 +ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
169 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
170 +
171 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
172 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o mt7530.o
173 +
174 +ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
175 +ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
176 +ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
177 +ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
178 +
179 +obj-$(CONFIG_NET_RALINK) += ralink-eth.o
180 Index: linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.c
181 ===================================================================
182 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
183 +++ linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.c 2014-10-29 20:25:55.433357519 +0100
184 @@ -0,0 +1,1463 @@
185 +/*
186 + * This program is free software; you can redistribute it and/or modify
187 + * it under the terms of the GNU General Public License as published by
188 + * the Free Software Foundation; version 2 of the License
189 + *
190 + * This program is distributed in the hope that it will be useful,
191 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
192 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
193 + * GNU General Public License for more details.
194 + *
195 + * You should have received a copy of the GNU General Public License
196 + * along with this program; if not, write to the Free Software
197 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
198 + *
199 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
200 + */
201 +
202 +#include <linux/module.h>
203 +#include <linux/kernel.h>
204 +#include <linux/types.h>
205 +#include <linux/dma-mapping.h>
206 +#include <linux/init.h>
207 +#include <linux/skbuff.h>
208 +#include <linux/etherdevice.h>
209 +#include <linux/ethtool.h>
210 +#include <linux/platform_device.h>
211 +#include <linux/of_device.h>
212 +#include <linux/clk.h>
213 +#include <linux/of_net.h>
214 +#include <linux/of_mdio.h>
215 +
216 +#include <asm/mach-ralink/ralink_regs.h>
217 +
218 +#include "ralink_soc_eth.h"
219 +
220 +#include <linux/ioport.h>
221 +#include <linux/switch.h>
222 +#include <linux/mii.h>
223 +
224 +#include <ralink_regs.h>
225 +#include <asm/mach-ralink/rt305x.h>
226 +#include <asm/mach-ralink/rt305x_esw_platform.h>
227 +
228 +/*
229 + * HW limitations for this switch:
230 + * - No large frame support (PKT_MAX_LEN at most 1536)
231 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
232 + * though this might be possible using the undocumented PPE.
233 + */
234 +
235 +#define RT305X_ESW_REG_ISR 0x00
236 +#define RT305X_ESW_REG_IMR 0x04
237 +#define RT305X_ESW_REG_FCT0 0x08
238 +#define RT305X_ESW_REG_PFC1 0x14
239 +#define RT305X_ESW_REG_ATS 0x24
240 +#define RT305X_ESW_REG_ATS0 0x28
241 +#define RT305X_ESW_REG_ATS1 0x2c
242 +#define RT305X_ESW_REG_ATS2 0x30
243 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
244 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
245 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
246 +#define RT305X_ESW_REG_POA 0x80
247 +#define RT305X_ESW_REG_FPA 0x84
248 +#define RT305X_ESW_REG_SOCPC 0x8c
249 +#define RT305X_ESW_REG_POC0 0x90
250 +#define RT305X_ESW_REG_POC1 0x94
251 +#define RT305X_ESW_REG_POC2 0x98
252 +#define RT305X_ESW_REG_SGC 0x9c
253 +#define RT305X_ESW_REG_STRT 0xa0
254 +#define RT305X_ESW_REG_PCR0 0xc0
255 +#define RT305X_ESW_REG_PCR1 0xc4
256 +#define RT305X_ESW_REG_FPA2 0xc8
257 +#define RT305X_ESW_REG_FCT2 0xcc
258 +#define RT305X_ESW_REG_SGC2 0xe4
259 +#define RT305X_ESW_REG_P0LED 0xa4
260 +#define RT305X_ESW_REG_P1LED 0xa8
261 +#define RT305X_ESW_REG_P2LED 0xac
262 +#define RT305X_ESW_REG_P3LED 0xb0
263 +#define RT305X_ESW_REG_P4LED 0xb4
264 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
265 +#define RT305X_ESW_REG_P1PC 0xec
266 +#define RT305X_ESW_REG_P2PC 0xf0
267 +#define RT305X_ESW_REG_P3PC 0xf4
268 +#define RT305X_ESW_REG_P4PC 0xf8
269 +#define RT305X_ESW_REG_P5PC 0xfc
270 +
271 +#define RT305X_ESW_LED_LINK 0
272 +#define RT305X_ESW_LED_100M 1
273 +#define RT305X_ESW_LED_DUPLEX 2
274 +#define RT305X_ESW_LED_ACTIVITY 3
275 +#define RT305X_ESW_LED_COLLISION 4
276 +#define RT305X_ESW_LED_LINKACT 5
277 +#define RT305X_ESW_LED_DUPLCOLL 6
278 +#define RT305X_ESW_LED_10MACT 7
279 +#define RT305X_ESW_LED_100MACT 8
280 +/* Additional led states not in datasheet: */
281 +#define RT305X_ESW_LED_BLINK 10
282 +#define RT305X_ESW_LED_ON 12
283 +
284 +#define RT305X_ESW_LINK_S 25
285 +#define RT305X_ESW_DUPLEX_S 9
286 +#define RT305X_ESW_SPD_S 0
287 +
288 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
289 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
290 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
291 +
292 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
293 +
294 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
295 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
296 +
297 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
298 +#define RT305X_ESW_PVIDC_PVID_S 12
299 +
300 +#define RT305X_ESW_VLANI_VID_M 0xfff
301 +#define RT305X_ESW_VLANI_VID_S 12
302 +
303 +#define RT305X_ESW_VMSC_MSC_M 0xff
304 +#define RT305X_ESW_VMSC_MSC_S 8
305 +
306 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
307 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
308 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
309 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
310 +
311 +#define RT305X_ESW_POC0_EN_BP_S 0
312 +#define RT305X_ESW_POC0_EN_FC_S 8
313 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
314 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
315 +#define RT305X_ESW_POC0_DIS_PORT_S 23
316 +
317 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
318 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
319 +#define RT305X_ESW_POC2_ENAGING_S 8
320 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
321 +
322 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
323 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
324 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
325 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
326 +
327 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
328 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
329 +#define RT305X_ESW_PFC1_EN_TOS_S 24
330 +
331 +#define RT305X_ESW_VLAN_NONE 0xfff
332 +
333 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
334 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
335 +
336 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
337 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
338 +
339 +#define RT305X_ESW_POA_LINK_MASK 0x1f
340 +#define RT305X_ESW_POA_LINK_SHIFT 25
341 +
342 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
343 +#define RT305X_ESW_PORT0 0
344 +#define RT305X_ESW_PORT1 1
345 +#define RT305X_ESW_PORT2 2
346 +#define RT305X_ESW_PORT3 3
347 +#define RT305X_ESW_PORT4 4
348 +#define RT305X_ESW_PORT5 5
349 +#define RT305X_ESW_PORT6 6
350 +
351 +#define RT305X_ESW_PORTS_NONE 0
352 +
353 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
354 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
355 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
356 +
357 +#define RT305X_ESW_PORTS_INTERNAL \
358 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
359 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
360 + BIT(RT305X_ESW_PORT4))
361 +
362 +#define RT305X_ESW_PORTS_NOCPU \
363 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
364 +
365 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
366 +
367 +#define RT305X_ESW_PORTS_ALL \
368 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
369 +
370 +#define RT305X_ESW_NUM_VLANS 16
371 +#define RT305X_ESW_NUM_VIDS 4096
372 +#define RT305X_ESW_NUM_PORTS 7
373 +#define RT305X_ESW_NUM_LANWAN 6
374 +#define RT305X_ESW_NUM_LEDS 5
375 +
376 +#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
377 +#define RT5350_EWS_REG_LED_POLARITY 0x168
378 +#define RT5350_RESET_EPHY BIT(24)
379 +#define SYSC_REG_RESET_CTRL 0x34
380 +
381 +enum {
382 + /* Global attributes. */
383 + RT305X_ESW_ATTR_ENABLE_VLAN,
384 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
385 + RT305X_ESW_ATTR_BC_STATUS,
386 + RT305X_ESW_ATTR_LED_FREQ,
387 + /* Port attributes. */
388 + RT305X_ESW_ATTR_PORT_DISABLE,
389 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
390 + RT305X_ESW_ATTR_PORT_UNTAG,
391 + RT305X_ESW_ATTR_PORT_LED,
392 + RT305X_ESW_ATTR_PORT_LAN,
393 + RT305X_ESW_ATTR_PORT_RECV_BAD,
394 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
395 + RT5350_ESW_ATTR_PORT_TR_BAD,
396 + RT5350_ESW_ATTR_PORT_TR_GOOD,
397 +};
398 +
399 +struct esw_port {
400 + bool disable;
401 + bool doubletag;
402 + bool untag;
403 + u8 led;
404 + u16 pvid;
405 +};
406 +
407 +struct esw_vlan {
408 + u8 ports;
409 + u16 vid;
410 +};
411 +
412 +struct rt305x_esw {
413 + struct device *dev;
414 + void __iomem *base;
415 + int irq;
416 + const struct rt305x_esw_platform_data *pdata;
417 + /* Protects against concurrent register rmw operations. */
418 + spinlock_t reg_rw_lock;
419 +
420 + unsigned char port_map;
421 + unsigned int reg_initval_fct2;
422 + unsigned int reg_initval_fpa2;
423 + unsigned int reg_led_polarity;
424 +
425 +
426 + struct switch_dev swdev;
427 + bool global_vlan_enable;
428 + bool alt_vlan_disable;
429 + int bc_storm_protect;
430 + int led_frequency;
431 + struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
432 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
433 +
434 +};
435 +
436 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
437 +{
438 + __raw_writel(val, esw->base + reg);
439 +}
440 +
441 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
442 +{
443 + return __raw_readl(esw->base + reg);
444 +}
445 +
446 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
447 + unsigned long val)
448 +{
449 + unsigned long t;
450 +
451 + t = __raw_readl(esw->base + reg) & ~mask;
452 + __raw_writel(t | val, esw->base + reg);
453 +}
454 +
455 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
456 + unsigned long val)
457 +{
458 + unsigned long flags;
459 +
460 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
461 + esw_rmw_raw(esw, reg, mask, val);
462 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
463 +}
464 +
465 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
466 + u32 write_data)
467 +{
468 + unsigned long t_start = jiffies;
469 + int ret = 0;
470 +
471 + while (1) {
472 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
473 + RT305X_ESW_PCR1_WT_DONE))
474 + break;
475 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
476 + ret = 1;
477 + goto out;
478 + }
479 + }
480 +
481 + write_data &= 0xffff;
482 + esw_w32(esw,
483 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
484 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
485 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
486 + RT305X_ESW_REG_PCR0);
487 +
488 + t_start = jiffies;
489 + while (1) {
490 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
491 + RT305X_ESW_PCR1_WT_DONE)
492 + break;
493 +
494 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
495 + ret = 1;
496 + break;
497 + }
498 + }
499 +out:
500 + if (ret)
501 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
502 + return ret;
503 +}
504 +
505 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
506 +{
507 + unsigned s;
508 + unsigned val;
509 +
510 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
511 + val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
512 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
513 +
514 + return val;
515 +}
516 +
517 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
518 +{
519 + unsigned s;
520 +
521 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
522 + esw_rmw(esw,
523 + RT305X_ESW_REG_VLANI(vlan / 2),
524 + RT305X_ESW_VLANI_VID_M << s,
525 + (vid & RT305X_ESW_VLANI_VID_M) << s);
526 +}
527 +
528 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
529 +{
530 + unsigned s, val;
531 +
532 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
533 + val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
534 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
535 +}
536 +
537 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
538 +{
539 + unsigned s;
540 +
541 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
542 + esw_rmw(esw,
543 + RT305X_ESW_REG_PVIDC(port / 2),
544 + RT305X_ESW_PVIDC_PVID_M << s,
545 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
546 +}
547 +
548 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
549 +{
550 + unsigned s, val;
551 +
552 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
553 + val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
554 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
555 +
556 + return val;
557 +}
558 +
559 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
560 +{
561 + unsigned s;
562 +
563 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
564 + esw_rmw(esw,
565 + RT305X_ESW_REG_VMSC(vlan / 4),
566 + RT305X_ESW_VMSC_MSC_M << s,
567 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
568 +}
569 +
570 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
571 +{
572 + unsigned reg;
573 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
574 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
575 + RT305X_ESW_POC0_DIS_PORT_M;
576 +}
577 +
578 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
579 +{
580 + unsigned old_mask;
581 + unsigned enable_mask;
582 + unsigned changed;
583 + int i;
584 +
585 + old_mask = esw_get_port_disable(esw);
586 + changed = old_mask ^ disable_mask;
587 + enable_mask = old_mask & disable_mask;
588 +
589 + /* enable before writing to MII */
590 + esw_rmw(esw, RT305X_ESW_REG_POC0,
591 + (RT305X_ESW_POC0_DIS_PORT_M <<
592 + RT305X_ESW_POC0_DIS_PORT_S),
593 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
594 +
595 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
596 + if (!(changed & (1 << i)))
597 + continue;
598 + if (disable_mask & (1 << i)) {
599 + /* disable */
600 + rt305x_mii_write(esw, i, MII_BMCR,
601 + BMCR_PDOWN);
602 + } else {
603 + /* enable */
604 + rt305x_mii_write(esw, i, MII_BMCR,
605 + BMCR_FULLDPLX |
606 + BMCR_ANENABLE |
607 + BMCR_ANRESTART |
608 + BMCR_SPEED100);
609 + }
610 + }
611 +
612 + /* disable after writing to MII */
613 + esw_rmw(esw, RT305X_ESW_REG_POC0,
614 + (RT305X_ESW_POC0_DIS_PORT_M <<
615 + RT305X_ESW_POC0_DIS_PORT_S),
616 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
617 +}
618 +
619 +static void esw_set_gsc(struct rt305x_esw *esw)
620 +{
621 + esw_rmw(esw, RT305X_ESW_REG_SGC,
622 + RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
623 + esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
624 + esw_rmw(esw, RT305X_ESW_REG_SGC,
625 + RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
626 + esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
627 +}
628 +
629 +static int esw_apply_config(struct switch_dev *dev);
630 +
631 +static void esw_hw_init(struct rt305x_esw *esw)
632 +{
633 + int i;
634 + u8 port_disable = 0;
635 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
636 +
637 + /* vodoo from original driver */
638 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
639 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
640 + /* Port priority 1 for all ports, vlan enabled. */
641 + esw_w32(esw, 0x00005555 |
642 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
643 + RT305X_ESW_REG_PFC1);
644 +
645 + /* Enable Back Pressure, and Flow Control */
646 + esw_w32(esw,
647 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
648 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
649 + RT305X_ESW_REG_POC0);
650 +
651 + /* Enable Aging, and VLAN TAG removal */
652 + esw_w32(esw,
653 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
654 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
655 + RT305X_ESW_REG_POC2);
656 +
657 + if (esw->reg_initval_fct2)
658 + esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
659 + else
660 + esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
661 +
662 + /*
663 + * 300s aging timer, max packet len 1536, broadcast storm prevention
664 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
665 + * pressure jam, GMII disable was_transmit, back pressure disabled,
666 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
667 + * ports.
668 + */
669 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
670 +
671 + /* Setup SoC Port control register */
672 + esw_w32(esw,
673 + (RT305X_ESW_SOCPC_CRC_PADDING |
674 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
675 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
676 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
677 + RT305X_ESW_REG_SOCPC);
678 +
679 + if (esw->reg_initval_fpa2)
680 + esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
681 + else
682 + esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
683 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
684 +
685 + /* Force Link/Activity on ports */
686 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
687 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
688 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
689 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
690 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
691 +
692 + /* Copy disabled port configuration from bootloader setup */
693 + port_disable = esw_get_port_disable(esw);
694 + for (i = 0; i < 6; i++)
695 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
696 +
697 + if (soc_is_rt3352()) {
698 + /* reset EPHY */
699 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
700 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
701 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
702 +
703 + rt305x_mii_write(esw, 0, 31, 0x8000);
704 + for (i = 0; i < 5; i++) {
705 + if (esw->ports[i].disable) {
706 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
707 + } else {
708 + rt305x_mii_write(esw, i, MII_BMCR,
709 + BMCR_FULLDPLX |
710 + BMCR_ANENABLE |
711 + BMCR_SPEED100);
712 + }
713 + /* TX10 waveform coefficient LSB=0 disable PHY */
714 + rt305x_mii_write(esw, i, 26, 0x1601);
715 + /* TX100/TX10 AD/DA current bias */
716 + rt305x_mii_write(esw, i, 29, 0x7016);
717 + /* TX100 slew rate control */
718 + rt305x_mii_write(esw, i, 30, 0x0038);
719 + }
720 +
721 + /* select global register */
722 + rt305x_mii_write(esw, 0, 31, 0x0);
723 + /* enlarge agcsel threshold 3 and threshold 2 */
724 + rt305x_mii_write(esw, 0, 1, 0x4a40);
725 + /* enlarge agcsel threshold 5 and threshold 4 */
726 + rt305x_mii_write(esw, 0, 2, 0x6254);
727 + /* enlarge agcsel threshold */
728 + rt305x_mii_write(esw, 0, 3, 0xa17f);
729 + rt305x_mii_write(esw, 0,12, 0x7eaa);
730 + /* longer TP_IDL tail length */
731 + rt305x_mii_write(esw, 0, 14, 0x65);
732 + /* increased squelch pulse count threshold. */
733 + rt305x_mii_write(esw, 0, 16, 0x0684);
734 + /* set TX10 signal amplitude threshold to minimum */
735 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
736 + /* set squelch amplitude to higher threshold */
737 + rt305x_mii_write(esw, 0, 18, 0x40ba);
738 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
739 + rt305x_mii_write(esw, 0, 22, 0x253f);
740 + /* set PLL/Receive bias current are calibrated */
741 + rt305x_mii_write(esw, 0, 27, 0x2fda);
742 + /* change PLL/Receive bias current to internal(RT3350) */
743 + rt305x_mii_write(esw, 0, 28, 0xc410);
744 + /* change PLL bias current to internal(RT3052_MP3) */
745 + rt305x_mii_write(esw, 0, 29, 0x598b);
746 + /* select local register */
747 + rt305x_mii_write(esw, 0, 31, 0x8000);
748 + } else if (soc_is_rt5350()) {
749 + /* reset EPHY */
750 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
751 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
752 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
753 +
754 + /* set the led polarity */
755 + esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
756 +
757 + /* local registers */
758 + rt305x_mii_write(esw, 0, 31, 0x8000);
759 + for (i = 0; i < 5; i++) {
760 + if (esw->ports[i].disable) {
761 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
762 + } else {
763 + rt305x_mii_write(esw, i, MII_BMCR,
764 + BMCR_FULLDPLX |
765 + BMCR_ANENABLE |
766 + BMCR_SPEED100);
767 + }
768 + /* TX10 waveform coefficient LSB=0 disable PHY */
769 + rt305x_mii_write(esw, i, 26, 0x1601);
770 + /* TX100/TX10 AD/DA current bias */
771 + rt305x_mii_write(esw, i, 29, 0x7015);
772 + /* TX100 slew rate control */
773 + rt305x_mii_write(esw, i, 30, 0x0038);
774 + }
775 +
776 + /* global registers */
777 + rt305x_mii_write(esw, 0, 31, 0x0);
778 + /* enlarge agcsel threshold 3 and threshold 2 */
779 + rt305x_mii_write(esw, 0, 1, 0x4a40);
780 + /* enlarge agcsel threshold 5 and threshold 4 */
781 + rt305x_mii_write(esw, 0, 2, 0x6254);
782 + /* enlarge agcsel threshold 6 */
783 + rt305x_mii_write(esw, 0, 3, 0xa17f);
784 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
785 + /* longer TP_IDL tail length */
786 + rt305x_mii_write(esw, 0, 14, 0x65);
787 + /* increased squelch pulse count threshold. */
788 + rt305x_mii_write(esw, 0, 16, 0x0684);
789 + /* set TX10 signal amplitude threshold to minimum */
790 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
791 + /* set squelch amplitude to higher threshold */
792 + rt305x_mii_write(esw, 0, 18, 0x40ba);
793 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
794 + rt305x_mii_write(esw, 0, 22, 0x253f);
795 + /* set PLL/Receive bias current are calibrated */
796 + rt305x_mii_write(esw, 0, 27, 0x2fda);
797 + /* change PLL/Receive bias current to internal(RT3350) */
798 + rt305x_mii_write(esw, 0, 28, 0xc410);
799 + /* change PLL bias current to internal(RT3052_MP3) */
800 + rt305x_mii_write(esw, 0, 29, 0x598b);
801 + /* select local register */
802 + rt305x_mii_write(esw, 0, 31, 0x8000);
803 + } else {
804 + rt305x_mii_write(esw, 0, 31, 0x8000);
805 + for (i = 0; i < 5; i++) {
806 + if (esw->ports[i].disable) {
807 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
808 + } else {
809 + rt305x_mii_write(esw, i, MII_BMCR,
810 + BMCR_FULLDPLX |
811 + BMCR_ANENABLE |
812 + BMCR_SPEED100);
813 + }
814 + /* TX10 waveform coefficient */
815 + rt305x_mii_write(esw, i, 26, 0x1601);
816 + /* TX100/TX10 AD/DA current bias */
817 + rt305x_mii_write(esw, i, 29, 0x7058);
818 + /* TX100 slew rate control */
819 + rt305x_mii_write(esw, i, 30, 0x0018);
820 + }
821 +
822 + /* PHY IOT */
823 + /* select global register */
824 + rt305x_mii_write(esw, 0, 31, 0x0);
825 + /* tune TP_IDL tail and head waveform */
826 + rt305x_mii_write(esw, 0, 22, 0x052f);
827 + /* set TX10 signal amplitude threshold to minimum */
828 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
829 + /* set squelch amplitude to higher threshold */
830 + rt305x_mii_write(esw, 0, 18, 0x40ba);
831 + /* longer TP_IDL tail length */
832 + rt305x_mii_write(esw, 0, 14, 0x65);
833 + /* select local register */
834 + rt305x_mii_write(esw, 0, 31, 0x8000);
835 + }
836 +
837 + if (esw->port_map)
838 + port_map = esw->port_map;
839 + else
840 + port_map = RT305X_ESW_PMAP_LLLLLL;
841 +
842 + /*
843 + * Unused HW feature, but still nice to be consistent here...
844 + * This is also exported to userspace ('lan' attribute) so it's
845 + * conveniently usable to decide which ports go into the wan vlan by
846 + * default.
847 + */
848 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
849 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
850 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
851 +
852 + /* make the switch leds blink */
853 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
854 + esw->ports[i].led = 0x05;
855 +
856 + /* Apply the empty config. */
857 + esw_apply_config(&esw->swdev);
858 +
859 + /* Only unmask the port change interrupt */
860 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
861 +}
862 +
863 +static irqreturn_t esw_interrupt(int irq, void *_esw)
864 +{
865 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
866 + u32 status;
867 +
868 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
869 + if (status & RT305X_ESW_PORT_ST_CHG) {
870 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
871 + link >>= RT305X_ESW_POA_LINK_SHIFT;
872 + link &= RT305X_ESW_POA_LINK_MASK;
873 + dev_info(esw->dev, "link changed 0x%02X\n", link);
874 + }
875 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
876 +
877 + return IRQ_HANDLED;
878 +}
879 +
880 +static int esw_apply_config(struct switch_dev *dev)
881 +{
882 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
883 + int i;
884 + u8 disable = 0;
885 + u8 doubletag = 0;
886 + u8 en_vlan = 0;
887 + u8 untag = 0;
888 +
889 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
890 + u32 vid, vmsc;
891 + if (esw->global_vlan_enable) {
892 + vid = esw->vlans[i].vid;
893 + vmsc = esw->vlans[i].ports;
894 + } else {
895 + vid = RT305X_ESW_VLAN_NONE;
896 + vmsc = RT305X_ESW_PORTS_NONE;
897 + }
898 + esw_set_vlan_id(esw, i, vid);
899 + esw_set_vmsc(esw, i, vmsc);
900 + }
901 +
902 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
903 + u32 pvid;
904 + disable |= esw->ports[i].disable << i;
905 + if (esw->global_vlan_enable) {
906 + doubletag |= esw->ports[i].doubletag << i;
907 + en_vlan |= 1 << i;
908 + untag |= esw->ports[i].untag << i;
909 + pvid = esw->ports[i].pvid;
910 + } else {
911 + int x = esw->alt_vlan_disable ? 0 : 1;
912 + doubletag |= x << i;
913 + en_vlan |= x << i;
914 + untag |= x << i;
915 + pvid = 0;
916 + }
917 + esw_set_pvid(esw, i, pvid);
918 + if (i < RT305X_ESW_NUM_LEDS)
919 + esw_w32(esw, esw->ports[i].led,
920 + RT305X_ESW_REG_P0LED + 4*i);
921 + }
922 +
923 + esw_set_gsc(esw);
924 + esw_set_port_disable(esw, disable);
925 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
926 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
927 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
928 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
929 + esw_rmw(esw, RT305X_ESW_REG_PFC1,
930 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
931 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
932 + esw_rmw(esw, RT305X_ESW_REG_POC2,
933 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
934 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
935 +
936 + if (!esw->global_vlan_enable) {
937 + /*
938 + * Still need to put all ports into vlan 0 or they'll be
939 + * isolated.
940 + * NOTE: vlan 0 is special, no vlan tag is prepended
941 + */
942 + esw_set_vlan_id(esw, 0, 0);
943 + esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
944 + }
945 +
946 + return 0;
947 +}
948 +
949 +static int esw_reset_switch(struct switch_dev *dev)
950 +{
951 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
952 +
953 + esw->global_vlan_enable = 0;
954 + memset(esw->ports, 0, sizeof(esw->ports));
955 + memset(esw->vlans, 0, sizeof(esw->vlans));
956 + esw_hw_init(esw);
957 +
958 + return 0;
959 +}
960 +
961 +static int esw_get_vlan_enable(struct switch_dev *dev,
962 + const struct switch_attr *attr,
963 + struct switch_val *val)
964 +{
965 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
966 +
967 + val->value.i = esw->global_vlan_enable;
968 +
969 + return 0;
970 +}
971 +
972 +static int esw_set_vlan_enable(struct switch_dev *dev,
973 + const struct switch_attr *attr,
974 + struct switch_val *val)
975 +{
976 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
977 +
978 + esw->global_vlan_enable = val->value.i != 0;
979 +
980 + return 0;
981 +}
982 +
983 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
984 + const struct switch_attr *attr,
985 + struct switch_val *val)
986 +{
987 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
988 +
989 + val->value.i = esw->alt_vlan_disable;
990 +
991 + return 0;
992 +}
993 +
994 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
995 + const struct switch_attr *attr,
996 + struct switch_val *val)
997 +{
998 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
999 +
1000 + esw->alt_vlan_disable = val->value.i != 0;
1001 +
1002 + return 0;
1003 +}
1004 +
1005 +static int
1006 +rt305x_esw_set_bc_status(struct switch_dev *dev,
1007 + const struct switch_attr *attr,
1008 + struct switch_val *val)
1009 +{
1010 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1011 +
1012 + esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1013 +
1014 + return 0;
1015 +}
1016 +
1017 +static int
1018 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1019 + const struct switch_attr *attr,
1020 + struct switch_val *val)
1021 +{
1022 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1023 +
1024 + val->value.i = esw->bc_storm_protect;
1025 +
1026 + return 0;
1027 +}
1028 +
1029 +static int
1030 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1031 + const struct switch_attr *attr,
1032 + struct switch_val *val)
1033 +{
1034 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1035 +
1036 + esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1037 +
1038 + return 0;
1039 +}
1040 +
1041 +static int
1042 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1043 + const struct switch_attr *attr,
1044 + struct switch_val *val)
1045 +{
1046 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1047 +
1048 + val->value.i = esw->led_frequency;
1049 +
1050 + return 0;
1051 +}
1052 +
1053 +static int esw_get_port_link(struct switch_dev *dev,
1054 + int port,
1055 + struct switch_port_link *link)
1056 +{
1057 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1058 + u32 speed, poa;
1059 +
1060 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1061 + return -EINVAL;
1062 +
1063 + poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1064 +
1065 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1066 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1067 + if (port < RT305X_ESW_NUM_LEDS) {
1068 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
1069 + } else {
1070 + if (port == RT305X_ESW_NUM_PORTS - 1)
1071 + poa >>= 1;
1072 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
1073 + }
1074 + switch (speed) {
1075 + case 0:
1076 + link->speed = SWITCH_PORT_SPEED_10;
1077 + break;
1078 + case 1:
1079 + link->speed = SWITCH_PORT_SPEED_100;
1080 + break;
1081 + case 2:
1082 + case 3: /* forced gige speed can be 2 or 3 */
1083 + link->speed = SWITCH_PORT_SPEED_1000;
1084 + break;
1085 + default:
1086 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1087 + break;
1088 + }
1089 +
1090 + return 0;
1091 +}
1092 +
1093 +static int esw_get_port_bool(struct switch_dev *dev,
1094 + const struct switch_attr *attr,
1095 + struct switch_val *val)
1096 +{
1097 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1098 + int idx = val->port_vlan;
1099 + u32 x, reg, shift;
1100 +
1101 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1102 + return -EINVAL;
1103 +
1104 + switch (attr->id) {
1105 + case RT305X_ESW_ATTR_PORT_DISABLE:
1106 + reg = RT305X_ESW_REG_POC0;
1107 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1108 + break;
1109 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1110 + reg = RT305X_ESW_REG_SGC2;
1111 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1112 + break;
1113 + case RT305X_ESW_ATTR_PORT_UNTAG:
1114 + reg = RT305X_ESW_REG_POC2;
1115 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1116 + break;
1117 + case RT305X_ESW_ATTR_PORT_LAN:
1118 + reg = RT305X_ESW_REG_SGC2;
1119 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1120 + if (idx >= RT305X_ESW_NUM_LANWAN)
1121 + return -EINVAL;
1122 + break;
1123 + default:
1124 + return -EINVAL;
1125 + }
1126 +
1127 + x = esw_r32(esw, reg);
1128 + val->value.i = (x >> (idx + shift)) & 1;
1129 +
1130 + return 0;
1131 +}
1132 +
1133 +static int esw_set_port_bool(struct switch_dev *dev,
1134 + const struct switch_attr *attr,
1135 + struct switch_val *val)
1136 +{
1137 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1138 + int idx = val->port_vlan;
1139 +
1140 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1141 + val->value.i < 0 || val->value.i > 1)
1142 + return -EINVAL;
1143 +
1144 + switch (attr->id) {
1145 + case RT305X_ESW_ATTR_PORT_DISABLE:
1146 + esw->ports[idx].disable = val->value.i;
1147 + break;
1148 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1149 + esw->ports[idx].doubletag = val->value.i;
1150 + break;
1151 + case RT305X_ESW_ATTR_PORT_UNTAG:
1152 + esw->ports[idx].untag = val->value.i;
1153 + break;
1154 + default:
1155 + return -EINVAL;
1156 + }
1157 +
1158 + return 0;
1159 +}
1160 +
1161 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1162 + const struct switch_attr *attr,
1163 + struct switch_val *val)
1164 +{
1165 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1166 + int idx = val->port_vlan;
1167 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1168 + u32 reg;
1169 +
1170 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1171 + return -EINVAL;
1172 + reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1173 + val->value.i = (reg >> shift) & 0xffff;
1174 +
1175 + return 0;
1176 +}
1177 +
1178 +static int
1179 +esw_get_port_tr_badgood(struct switch_dev *dev,
1180 + const struct switch_attr *attr,
1181 + struct switch_val *val)
1182 +{
1183 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1184 +
1185 + int idx = val->port_vlan;
1186 + int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1187 + u32 reg;
1188 +
1189 + if (!soc_is_rt5350())
1190 + return -EINVAL;
1191 +
1192 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1193 + return -EINVAL;
1194 +
1195 + reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1196 + val->value.i = (reg >> shift) & 0xffff;
1197 +
1198 + return 0;
1199 +}
1200 +
1201 +static int esw_get_port_led(struct switch_dev *dev,
1202 + const struct switch_attr *attr,
1203 + struct switch_val *val)
1204 +{
1205 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1206 + int idx = val->port_vlan;
1207 +
1208 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1209 + idx >= RT305X_ESW_NUM_LEDS)
1210 + return -EINVAL;
1211 +
1212 + val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1213 +
1214 + return 0;
1215 +}
1216 +
1217 +static int esw_set_port_led(struct switch_dev *dev,
1218 + const struct switch_attr *attr,
1219 + struct switch_val *val)
1220 +{
1221 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1222 + int idx = val->port_vlan;
1223 +
1224 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1225 + return -EINVAL;
1226 +
1227 + esw->ports[idx].led = val->value.i;
1228 +
1229 + return 0;
1230 +}
1231 +
1232 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1233 +{
1234 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1235 +
1236 + if (port >= RT305X_ESW_NUM_PORTS)
1237 + return -EINVAL;
1238 +
1239 + *val = esw_get_pvid(esw, port);
1240 +
1241 + return 0;
1242 +}
1243 +
1244 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1245 +{
1246 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1247 +
1248 + if (port >= RT305X_ESW_NUM_PORTS)
1249 + return -EINVAL;
1250 +
1251 + esw->ports[port].pvid = val;
1252 +
1253 + return 0;
1254 +}
1255 +
1256 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1257 +{
1258 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1259 + u32 vmsc, poc2;
1260 + int vlan_idx = -1;
1261 + int i;
1262 +
1263 + val->len = 0;
1264 +
1265 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1266 + return -EINVAL;
1267 +
1268 + /* valid vlan? */
1269 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1270 + if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1271 + esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1272 + vlan_idx = i;
1273 + break;
1274 + }
1275 + }
1276 +
1277 + if (vlan_idx == -1)
1278 + return -EINVAL;
1279 +
1280 + vmsc = esw_get_vmsc(esw, vlan_idx);
1281 + poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1282 +
1283 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1284 + struct switch_port *p;
1285 + int port_mask = 1 << i;
1286 +
1287 + if (!(vmsc & port_mask))
1288 + continue;
1289 +
1290 + p = &val->value.ports[val->len++];
1291 + p->id = i;
1292 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1293 + p->flags = 0;
1294 + else
1295 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1296 + }
1297 +
1298 + return 0;
1299 +}
1300 +
1301 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1302 +{
1303 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1304 + int ports;
1305 + int vlan_idx = -1;
1306 + int i;
1307 +
1308 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1309 + val->len > RT305X_ESW_NUM_PORTS)
1310 + return -EINVAL;
1311 +
1312 + /* one of the already defined vlans? */
1313 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1314 + if (esw->vlans[i].vid == val->port_vlan &&
1315 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1316 + vlan_idx = i;
1317 + break;
1318 + }
1319 + }
1320 +
1321 + /* select a free slot */
1322 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1323 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1324 + vlan_idx = i;
1325 + }
1326 +
1327 + /* bail if all slots are in use */
1328 + if (vlan_idx == -1)
1329 + return -EINVAL;
1330 +
1331 + ports = RT305X_ESW_PORTS_NONE;
1332 + for (i = 0; i < val->len; i++) {
1333 + struct switch_port *p = &val->value.ports[i];
1334 + int port_mask = 1 << p->id;
1335 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1336 +
1337 + if (p->id >= RT305X_ESW_NUM_PORTS)
1338 + return -EINVAL;
1339 +
1340 + ports |= port_mask;
1341 + esw->ports[p->id].untag = untagged;
1342 + }
1343 + esw->vlans[vlan_idx].ports = ports;
1344 + if (ports == RT305X_ESW_PORTS_NONE)
1345 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1346 + else
1347 + esw->vlans[vlan_idx].vid = val->port_vlan;
1348 +
1349 + return 0;
1350 +}
1351 +
1352 +static const struct switch_attr esw_global[] = {
1353 + {
1354 + .type = SWITCH_TYPE_INT,
1355 + .name = "enable_vlan",
1356 + .description = "VLAN mode (1:enabled)",
1357 + .max = 1,
1358 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1359 + .get = esw_get_vlan_enable,
1360 + .set = esw_set_vlan_enable,
1361 + },
1362 + {
1363 + .type = SWITCH_TYPE_INT,
1364 + .name = "alternate_vlan_disable",
1365 + .description = "Use en_vlan instead of doubletag to disable"
1366 + " VLAN mode",
1367 + .max = 1,
1368 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1369 + .get = esw_get_alt_vlan_disable,
1370 + .set = esw_set_alt_vlan_disable,
1371 + },
1372 + {
1373 + .type = SWITCH_TYPE_INT,
1374 + .name = "bc_storm_protect",
1375 + .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1376 + .max = 3,
1377 + .id = RT305X_ESW_ATTR_BC_STATUS,
1378 + .get = rt305x_esw_get_bc_status,
1379 + .set = rt305x_esw_set_bc_status,
1380 + },
1381 + {
1382 + .type = SWITCH_TYPE_INT,
1383 + .name = "led_frequency",
1384 + .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1385 + .max = 3,
1386 + .id = RT305X_ESW_ATTR_LED_FREQ,
1387 + .get = rt305x_esw_get_led_freq,
1388 + .set = rt305x_esw_set_led_freq,
1389 + }
1390 +};
1391 +
1392 +static const struct switch_attr esw_port[] = {
1393 + {
1394 + .type = SWITCH_TYPE_INT,
1395 + .name = "disable",
1396 + .description = "Port state (1:disabled)",
1397 + .max = 1,
1398 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1399 + .get = esw_get_port_bool,
1400 + .set = esw_set_port_bool,
1401 + },
1402 + {
1403 + .type = SWITCH_TYPE_INT,
1404 + .name = "doubletag",
1405 + .description = "Double tagging for incoming vlan packets "
1406 + "(1:enabled)",
1407 + .max = 1,
1408 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1409 + .get = esw_get_port_bool,
1410 + .set = esw_set_port_bool,
1411 + },
1412 + {
1413 + .type = SWITCH_TYPE_INT,
1414 + .name = "untag",
1415 + .description = "Untag (1:strip outgoing vlan tag)",
1416 + .max = 1,
1417 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1418 + .get = esw_get_port_bool,
1419 + .set = esw_set_port_bool,
1420 + },
1421 + {
1422 + .type = SWITCH_TYPE_INT,
1423 + .name = "led",
1424 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1425 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1426 + " 8:100mact, 10:blink, 11:off, 12:on)",
1427 + .max = 15,
1428 + .id = RT305X_ESW_ATTR_PORT_LED,
1429 + .get = esw_get_port_led,
1430 + .set = esw_set_port_led,
1431 + },
1432 + {
1433 + .type = SWITCH_TYPE_INT,
1434 + .name = "lan",
1435 + .description = "HW port group (0:wan, 1:lan)",
1436 + .max = 1,
1437 + .id = RT305X_ESW_ATTR_PORT_LAN,
1438 + .get = esw_get_port_bool,
1439 + },
1440 + {
1441 + .type = SWITCH_TYPE_INT,
1442 + .name = "recv_bad",
1443 + .description = "Receive bad packet counter",
1444 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1445 + .get = esw_get_port_recv_badgood,
1446 + },
1447 + {
1448 + .type = SWITCH_TYPE_INT,
1449 + .name = "recv_good",
1450 + .description = "Receive good packet counter",
1451 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1452 + .get = esw_get_port_recv_badgood,
1453 + },
1454 + {
1455 + .type = SWITCH_TYPE_INT,
1456 + .name = "tr_bad",
1457 +
1458 + .description = "Transmit bad packet counter. rt5350 only",
1459 + .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1460 + .get = esw_get_port_tr_badgood,
1461 + },
1462 + {
1463 + .type = SWITCH_TYPE_INT,
1464 + .name = "tr_good",
1465 +
1466 + .description = "Transmit good packet counter. rt5350 only",
1467 + .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1468 + .get = esw_get_port_tr_badgood,
1469 + },
1470 +};
1471 +
1472 +static const struct switch_attr esw_vlan[] = {
1473 +};
1474 +
1475 +static const struct switch_dev_ops esw_ops = {
1476 + .attr_global = {
1477 + .attr = esw_global,
1478 + .n_attr = ARRAY_SIZE(esw_global),
1479 + },
1480 + .attr_port = {
1481 + .attr = esw_port,
1482 + .n_attr = ARRAY_SIZE(esw_port),
1483 + },
1484 + .attr_vlan = {
1485 + .attr = esw_vlan,
1486 + .n_attr = ARRAY_SIZE(esw_vlan),
1487 + },
1488 + .get_vlan_ports = esw_get_vlan_ports,
1489 + .set_vlan_ports = esw_set_vlan_ports,
1490 + .get_port_pvid = esw_get_port_pvid,
1491 + .set_port_pvid = esw_set_port_pvid,
1492 + .get_port_link = esw_get_port_link,
1493 + .apply_config = esw_apply_config,
1494 + .reset_switch = esw_reset_switch,
1495 +};
1496 +
1497 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1498 + /* All ports are LAN ports. */
1499 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1500 + .reg_initval_fct2 = 0x00d6500c,
1501 + /*
1502 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1503 + * turbo mii off, rgmi 3.3v off
1504 + * port5: disabled
1505 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1506 + */
1507 + .reg_initval_fpa2 = 0x3f502b28,
1508 +};
1509 +
1510 +static const struct of_device_id ralink_esw_match[] = {
1511 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1512 + {},
1513 +};
1514 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1515 +
1516 +static int esw_probe(struct platform_device *pdev)
1517 +{
1518 + struct device_node *np = pdev->dev.of_node;
1519 + const struct rt305x_esw_platform_data *pdata;
1520 + const __be32 *port_map, *reg_init;
1521 + struct rt305x_esw *esw;
1522 + struct switch_dev *swdev;
1523 + struct resource *res, *irq;
1524 + int err;
1525 +
1526 + pdata = pdev->dev.platform_data;
1527 + if (!pdata) {
1528 + const struct of_device_id *match;
1529 + match = of_match_device(ralink_esw_match, &pdev->dev);
1530 + if (match)
1531 + pdata = (struct rt305x_esw_platform_data *) match->data;
1532 + }
1533 + if (!pdata)
1534 + return -EINVAL;
1535 +
1536 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537 + if (!res) {
1538 + dev_err(&pdev->dev, "no memory resource found\n");
1539 + return -ENOMEM;
1540 + }
1541 +
1542 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1543 + if (!irq) {
1544 + dev_err(&pdev->dev, "no irq resource found\n");
1545 + return -ENOMEM;
1546 + }
1547 +
1548 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1549 + if (!esw) {
1550 + dev_err(&pdev->dev, "no memory for private data\n");
1551 + return -ENOMEM;
1552 + }
1553 +
1554 + esw->dev = &pdev->dev;
1555 + esw->irq = irq->start;
1556 + esw->base = ioremap(res->start, resource_size(res));
1557 + if (!esw->base) {
1558 + dev_err(&pdev->dev, "ioremap failed\n");
1559 + err = -ENOMEM;
1560 + goto free_esw;
1561 + }
1562 +
1563 + port_map = of_get_property(np, "ralink,portmap", NULL);
1564 + if (port_map)
1565 + esw->port_map = be32_to_cpu(*port_map);
1566 +
1567 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1568 + if (reg_init)
1569 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1570 +
1571 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1572 + if (reg_init)
1573 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1574 +
1575 + reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1576 + if (reg_init)
1577 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
1578 +
1579 + swdev = &esw->swdev;
1580 + swdev->of_node = pdev->dev.of_node;
1581 + swdev->name = "rt305x-esw";
1582 + swdev->alias = "rt305x";
1583 + swdev->cpu_port = RT305X_ESW_PORT6;
1584 + swdev->ports = RT305X_ESW_NUM_PORTS;
1585 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1586 + swdev->ops = &esw_ops;
1587 +
1588 + err = register_switch(swdev, NULL);
1589 + if (err < 0) {
1590 + dev_err(&pdev->dev, "register_switch failed\n");
1591 + goto unmap_base;
1592 + }
1593 +
1594 + platform_set_drvdata(pdev, esw);
1595 +
1596 + esw->pdata = pdata;
1597 + spin_lock_init(&esw->reg_rw_lock);
1598 +
1599 + esw_hw_init(esw);
1600 +
1601 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1602 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1603 + request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1604 +
1605 + return 0;
1606 +
1607 +unmap_base:
1608 + iounmap(esw->base);
1609 +free_esw:
1610 + kfree(esw);
1611 + return err;
1612 +}
1613 +
1614 +static int esw_remove(struct platform_device *pdev)
1615 +{
1616 + struct rt305x_esw *esw;
1617 +
1618 + esw = platform_get_drvdata(pdev);
1619 + if (esw) {
1620 + unregister_switch(&esw->swdev);
1621 + platform_set_drvdata(pdev, NULL);
1622 + iounmap(esw->base);
1623 + kfree(esw);
1624 + }
1625 +
1626 + return 0;
1627 +}
1628 +
1629 +static struct platform_driver esw_driver = {
1630 + .probe = esw_probe,
1631 + .remove = esw_remove,
1632 + .driver = {
1633 + .name = "rt305x-esw",
1634 + .owner = THIS_MODULE,
1635 + .of_match_table = ralink_esw_match,
1636 + },
1637 +};
1638 +
1639 +int __init rtesw_init(void)
1640 +{
1641 + return platform_driver_register(&esw_driver);
1642 +}
1643 +
1644 +void rtesw_exit(void)
1645 +{
1646 + platform_driver_unregister(&esw_driver);
1647 +}
1648 Index: linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.h
1649 ===================================================================
1650 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1651 +++ linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.h 2014-10-29 20:25:55.433357519 +0100
1652 @@ -0,0 +1,32 @@
1653 +/*
1654 + * This program is free software; you can redistribute it and/or modify
1655 + * it under the terms of the GNU General Public License as published by
1656 + * the Free Software Foundation; version 2 of the License
1657 + *
1658 + * This program is distributed in the hope that it will be useful,
1659 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1660 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1661 + * GNU General Public License for more details.
1662 + *
1663 + * You should have received a copy of the GNU General Public License
1664 + * along with this program; if not, write to the Free Software
1665 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1666 + *
1667 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1668 + */
1669 +
1670 +#ifndef _RALINK_ESW_RT3052_H__
1671 +#define _RALINK_ESW_RT3052_H__
1672 +
1673 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1674 +
1675 +int __init rtesw_init(void);
1676 +void rtesw_exit(void);
1677 +
1678 +#else
1679 +
1680 +static inline int __init rtesw_init(void) { return 0; }
1681 +static inline void rtesw_exit(void) { }
1682 +
1683 +#endif
1684 +#endif
1685 Index: linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.c
1686 ===================================================================
1687 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1688 +++ linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.c 2014-10-29 20:33:38.670422146 +0100
1689 @@ -0,0 +1,569 @@
1690 +/*
1691 + * This program is free software; you can redistribute it and/or modify
1692 + * it under the terms of the GNU General Public License as published by
1693 + * the Free Software Foundation; version 2 of the License
1694 + *
1695 + * This program is distributed in the hope that it will be useful,
1696 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1697 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1698 + * GNU General Public License for more details.
1699 + *
1700 + * You should have received a copy of the GNU General Public License
1701 + * along with this program; if not, write to the Free Software
1702 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1703 + *
1704 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1705 + */
1706 +
1707 +#include <linux/module.h>
1708 +#include <linux/kernel.h>
1709 +#include <linux/types.h>
1710 +#include <linux/dma-mapping.h>
1711 +#include <linux/init.h>
1712 +#include <linux/skbuff.h>
1713 +#include <linux/etherdevice.h>
1714 +#include <linux/ethtool.h>
1715 +#include <linux/platform_device.h>
1716 +#include <linux/of_device.h>
1717 +#include <linux/clk.h>
1718 +#include <linux/of_net.h>
1719 +#include <linux/of_mdio.h>
1720 +#include <linux/of_irq.h>
1721 +#include <linux/of_address.h>
1722 +#include <linux/switch.h>
1723 +
1724 +#include <asm/mach-ralink/ralink_regs.h>
1725 +
1726 +#include "ralink_soc_eth.h"
1727 +
1728 +#include <linux/ioport.h>
1729 +#include <linux/switch.h>
1730 +#include <linux/mii.h>
1731 +
1732 +#include <ralink_regs.h>
1733 +#include <asm/mach-ralink/mt7620.h>
1734 +
1735 +#include "ralink_soc_eth.h"
1736 +#include "gsw_mt7620a.h"
1737 +#include "mt7530.h"
1738 +#include "mdio.h"
1739 +
1740 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
1741 +
1742 +#define MT7620A_GSW_REG_PIAC 0x7004
1743 +
1744 +#define GSW_NUM_VLANS 16
1745 +#define GSW_NUM_VIDS 4096
1746 +#define GSW_NUM_PORTS 7
1747 +#define GSW_PORT6 6
1748 +
1749 +#define GSW_MDIO_ACCESS BIT(31)
1750 +#define GSW_MDIO_READ BIT(19)
1751 +#define GSW_MDIO_WRITE BIT(18)
1752 +#define GSW_MDIO_START BIT(16)
1753 +#define GSW_MDIO_ADDR_SHIFT 20
1754 +#define GSW_MDIO_REG_SHIFT 25
1755 +
1756 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
1757 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1758 +#define GSW_REG_SMACCR0 0x3fE4
1759 +#define GSW_REG_SMACCR1 0x3fE8
1760 +#define GSW_REG_CKGCR 0x3ff0
1761 +
1762 +#define GSW_REG_IMR 0x7008
1763 +#define GSW_REG_ISR 0x700c
1764 +
1765 +#define SYSC_REG_CFG1 0x14
1766 +
1767 +#define PORT_IRQ_ST_CHG 0x7f
1768 +
1769 +#define SYSCFG1 0x14
1770 +
1771 +#define ESW_PHY_POLLING 0x7000
1772 +
1773 +#define PMCR_IPG BIT(18)
1774 +#define PMCR_MAC_MODE BIT(16)
1775 +#define PMCR_FORCE BIT(15)
1776 +#define PMCR_TX_EN BIT(14)
1777 +#define PMCR_RX_EN BIT(13)
1778 +#define PMCR_BACKOFF BIT(9)
1779 +#define PMCR_BACKPRES BIT(8)
1780 +#define PMCR_RX_FC BIT(5)
1781 +#define PMCR_TX_FC BIT(4)
1782 +#define PMCR_SPEED(_x) (_x << 2)
1783 +#define PMCR_DUPLEX BIT(1)
1784 +#define PMCR_LINK BIT(0)
1785 +
1786 +#define PHY_AN_EN BIT(31)
1787 +#define PHY_PRE_EN BIT(30)
1788 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
1789 +
1790 +enum {
1791 + /* Global attributes. */
1792 + GSW_ATTR_ENABLE_VLAN,
1793 + /* Port attributes. */
1794 + GSW_ATTR_PORT_UNTAG,
1795 +};
1796 +
1797 +enum {
1798 + PORT4_EPHY = 0,
1799 + PORT4_EXT,
1800 +};
1801 +
1802 +struct mt7620_gsw {
1803 + struct device *dev;
1804 + void __iomem *base;
1805 + int irq;
1806 + int port4;
1807 + long unsigned int autopoll;
1808 +};
1809 +
1810 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1811 +{
1812 + iowrite32(val, gsw->base + reg);
1813 +}
1814 +
1815 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1816 +{
1817 + return ioread32(gsw->base + reg);
1818 +}
1819 +
1820 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1821 +{
1822 + unsigned long t_start = jiffies;
1823 +
1824 + while (1) {
1825 + if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1826 + return 0;
1827 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1828 + break;
1829 + }
1830 + }
1831 +
1832 + printk(KERN_ERR "mdio: MDIO timeout\n");
1833 + return -1;
1834 +}
1835 +
1836 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1837 + u32 write_data)
1838 +{
1839 + if (mt7620_mii_busy_wait(gsw))
1840 + return -1;
1841 +
1842 + write_data &= 0xffff;
1843 +
1844 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1845 + (phy_register << GSW_MDIO_REG_SHIFT) |
1846 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1847 + MT7620A_GSW_REG_PIAC);
1848 +
1849 + if (mt7620_mii_busy_wait(gsw))
1850 + return -1;
1851 +
1852 + return 0;
1853 +}
1854 +
1855 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1856 +{
1857 + u32 d;
1858 +
1859 + if (mt7620_mii_busy_wait(gsw))
1860 + return 0xffff;
1861 +
1862 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1863 + (phy_reg << GSW_MDIO_REG_SHIFT) |
1864 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
1865 + MT7620A_GSW_REG_PIAC);
1866 +
1867 + if (mt7620_mii_busy_wait(gsw))
1868 + return 0xffff;
1869 +
1870 + d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1871 +
1872 + return d;
1873 +}
1874 +
1875 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1876 +{
1877 + struct fe_priv *priv = bus->priv;
1878 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1879 +
1880 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1881 +}
1882 +
1883 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1884 +{
1885 + struct fe_priv *priv = bus->priv;
1886 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1887 +
1888 + return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1889 +}
1890 +
1891 +static unsigned char *fe_speed_str(int speed)
1892 +{
1893 + switch (speed) {
1894 + case 2:
1895 + case SPEED_1000:
1896 + return "1000";
1897 + case 1:
1898 + case SPEED_100:
1899 + return "100";
1900 + case 0:
1901 + case SPEED_10:
1902 + return "10";
1903 + }
1904 +
1905 + return "? ";
1906 +}
1907 +
1908 +int mt7620a_has_carrier(struct fe_priv *priv)
1909 +{
1910 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1911 + int i;
1912 +
1913 + for (i = 0; i < GSW_PORT6; i++)
1914 + if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1915 + return 1;
1916 + return 0;
1917 +}
1918 +
1919 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1920 +{
1921 + if (!priv->phy)
1922 + return;
1923 +
1924 + if (mt7620a_has_carrier(priv))
1925 + netif_carrier_on(priv->netdev);
1926 + else
1927 + netif_carrier_off(priv->netdev);
1928 +}
1929 +
1930 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1931 +{
1932 + if (priv->link[port])
1933 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1934 + port, fe_speed_str(priv->phy->speed[port]),
1935 + (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1936 + else
1937 + netdev_info(priv->netdev, "port %d link down\n", port);
1938 + mt7620a_handle_carrier(priv);
1939 +}
1940 +
1941 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1942 +{
1943 + struct fe_priv *priv = (struct fe_priv *) _priv;
1944 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1945 + u32 status;
1946 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1947 +
1948 + status = gsw_r32(gsw, GSW_REG_ISR);
1949 + if (status & PORT_IRQ_ST_CHG)
1950 + for (i = 0; i <= max; i++) {
1951 + u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1952 + int link = status & 0x1;
1953 +
1954 + if (link != priv->link[i]) {
1955 + if (link)
1956 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1957 + i, fe_speed_str((status >> 2) & 3),
1958 + (status & 0x2) ? "Full" : "Half");
1959 + else
1960 + netdev_info(priv->netdev, "port %d link down\n", i);
1961 + }
1962 +
1963 + priv->link[i] = link;
1964 + }
1965 + mt7620a_handle_carrier(priv);
1966 +
1967 + gsw_w32(gsw, status, GSW_REG_ISR);
1968 +
1969 + return IRQ_HANDLED;
1970 +}
1971 +
1972 +static int mt7620_is_bga(void)
1973 +{
1974 + u32 bga = rt_sysc_r32(0x0c);
1975 +
1976 + return (bga >> 16) & 1;
1977 +}
1978 +
1979 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1980 +{
1981 + int phy;
1982 + int lsb = -1, msb = 0;
1983 +
1984 + for_each_set_bit(phy, &gsw->autopoll, 32) {
1985 + if (lsb < 0)
1986 + lsb = phy;
1987 + msb = phy;
1988 + }
1989 +
1990 + gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1991 +}
1992 +
1993 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
1994 +{
1995 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1996 + const __be32 *_id = of_get_property(np, "reg", NULL);
1997 + int phy_mode, size, id;
1998 + int shift = 12;
1999 + u32 val, mask = 0;
2000 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
2001 +
2002 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2003 + if (_id)
2004 + pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2005 + else
2006 + pr_err("%s: invalid port id\n", np->name);
2007 + return;
2008 + }
2009 +
2010 + id = be32_to_cpu(*_id);
2011 +
2012 + if (id == 4)
2013 + shift = 14;
2014 +
2015 + priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2016 + if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2017 + pr_err("%s: invalid fixed link property\n", np->name);
2018 + priv->phy->phy_fixed[id] = NULL;
2019 + return;
2020 + }
2021 +
2022 + phy_mode = of_get_phy_mode(np);
2023 + switch (phy_mode) {
2024 + case PHY_INTERFACE_MODE_RGMII:
2025 + mask = 0;
2026 + break;
2027 + case PHY_INTERFACE_MODE_MII:
2028 + mask = 1;
2029 + break;
2030 + case PHY_INTERFACE_MODE_RMII:
2031 + mask = 2;
2032 + break;
2033 + default:
2034 + dev_err(priv->device, "port %d - invalid phy mode\n", id);
2035 + return;
2036 + }
2037 +
2038 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2039 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2040 + return;
2041 +
2042 + val = rt_sysc_r32(SYSCFG1);
2043 + val &= ~(3 << shift);
2044 + val |= mask << shift;
2045 + rt_sysc_w32(val, SYSCFG1);
2046 +
2047 + if (priv->phy->phy_fixed[id]) {
2048 + const __be32 *link = priv->phy->phy_fixed[id];
2049 + int tx_fc, rx_fc;
2050 + u32 val = 0;
2051 +
2052 + priv->phy->speed[id] = be32_to_cpup(link++);
2053 + tx_fc = be32_to_cpup(link++);
2054 + rx_fc = be32_to_cpup(link++);
2055 + priv->phy->duplex[id] = be32_to_cpup(link++);
2056 + priv->link[id] = 1;
2057 +
2058 + switch (priv->phy->speed[id]) {
2059 + case SPEED_10:
2060 + val = 0;
2061 + break;
2062 + case SPEED_100:
2063 + val = 1;
2064 + break;
2065 + case SPEED_1000:
2066 + val = 2;
2067 + break;
2068 + default:
2069 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2070 + priv->phy->phy_fixed[id] = 0;
2071 + return;
2072 + }
2073 + val = PMCR_SPEED(val);
2074 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2075 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2076 + if (tx_fc)
2077 + val |= PMCR_TX_FC;
2078 + if (rx_fc)
2079 + val |= PMCR_RX_FC;
2080 + if (priv->phy->duplex[id])
2081 + val |= PMCR_DUPLEX;
2082 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2083 + dev_info(priv->device, "using fixed link parameters\n");
2084 + return;
2085 + }
2086 +
2087 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2088 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2089 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
2090 +
2091 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2092 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2093 + gsw->autopoll |= BIT(id);
2094 + gsw_auto_poll(gsw);
2095 + return;
2096 + }
2097 +}
2098 +
2099 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2100 +{
2101 + u32 is_BGA = mt7620_is_bga();
2102 +
2103 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2104 + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2105 +
2106 + /*correct PHY setting L3.0 BGA*/
2107 + _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2108 +
2109 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
2110 + if (is_BGA)
2111 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
2112 + else
2113 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
2114 +
2115 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2116 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
2117 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
2118 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
2119 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
2120 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
2121 +
2122 + _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2123 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
2124 +
2125 + _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2126 + if (is_BGA) {
2127 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
2128 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
2129 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2130 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2131 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2132 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2133 + } else {
2134 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
2135 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2136 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2137 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2138 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2139 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2140 + }
2141 + _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2142 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2143 +
2144 + _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2145 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
2146 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
2147 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
2148 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
2149 +
2150 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2151 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2152 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2153 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2154 +
2155 + _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2156 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
2157 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
2158 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
2159 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2160 +
2161 + /* CPU Port6 Force Link 1G, FC ON */
2162 + gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2163 + /* Set Port6 CPU Port */
2164 + gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2165 +
2166 + /* setup port 4 */
2167 + if (gsw->port4 == PORT4_EPHY) {
2168 + u32 val = rt_sysc_r32(SYSCFG1);
2169 + val |= 3 << 14;
2170 + rt_sysc_w32(val, SYSCFG1);
2171 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
2172 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2173 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
2174 + pr_info("gsw: setting port4 to ephy mode\n");
2175 + }
2176 +}
2177 +
2178 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2179 +{
2180 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2181 + unsigned long flags;
2182 +
2183 + spin_lock_irqsave(&priv->page_lock, flags);
2184 + gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2185 + gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2186 + GSW_REG_SMACCR0);
2187 + spin_unlock_irqrestore(&priv->page_lock, flags);
2188 +}
2189 +
2190 +static struct of_device_id gsw_match[] = {
2191 + { .compatible = "ralink,mt7620a-gsw" },
2192 + {}
2193 +};
2194 +
2195 +int mt7620_gsw_config(struct fe_priv *priv)
2196 +{
2197 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2198 +
2199 + /* is the mt7530 internal or external */
2200 + if ((_mt7620_mii_read(gsw, 0x1f, 2) == 1) && (_mt7620_mii_read(gsw, 0x1f, 3) == 0xbeef)) {
2201 + mt7530_probe(priv->device, gsw->base, NULL, 0);
2202 + mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
2203 + } else {
2204 + mt7530_probe(priv->device, gsw->base, NULL, 1);
2205 + }
2206 +
2207 + return 0;
2208 +}
2209 +
2210 +int mt7620_gsw_probe(struct fe_priv *priv)
2211 +{
2212 + struct mt7620_gsw *gsw;
2213 + struct device_node *np;
2214 + const char *port4 = NULL;
2215 +
2216 + np = of_find_matching_node(NULL, gsw_match);
2217 + if (!np) {
2218 + dev_err(priv->device, "no gsw node found\n");
2219 + return -EINVAL;
2220 + }
2221 + np = of_node_get(np);
2222 +
2223 + gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2224 + if (!gsw) {
2225 + dev_err(priv->device, "no gsw memory for private data\n");
2226 + return -ENOMEM;
2227 + }
2228 +
2229 + gsw->irq = irq_of_parse_and_map(np, 0);
2230 + if (!gsw->irq) {
2231 + dev_err(priv->device, "no gsw irq resource found\n");
2232 + return -ENOMEM;
2233 + }
2234 +
2235 + gsw->base = of_iomap(np, 0);
2236 + if (!gsw->base) {
2237 + dev_err(priv->device, "gsw ioremap failed\n");
2238 + return -ENOMEM;
2239 + }
2240 +
2241 + gsw->dev = priv->device;
2242 + priv->soc->swpriv = gsw;
2243 +
2244 + of_property_read_string(np, "ralink,port4", &port4);
2245 + if (port4 && !strcmp(port4, "ephy"))
2246 + gsw->port4 = PORT4_EPHY;
2247 + else if (port4 && !strcmp(port4, "gmac"))
2248 + gsw->port4 = PORT4_EXT;
2249 + else
2250 + WARN_ON(port4);
2251 +
2252 + gsw_hw_init(gsw);
2253 +
2254 + gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2255 + request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2256 +
2257 + return 0;
2258 +}
2259 Index: linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.h
2260 ===================================================================
2261 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2262 +++ linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.h 2014-10-29 20:25:55.433357519 +0100
2263 @@ -0,0 +1,30 @@
2264 +/*
2265 + * This program is free software; you can redistribute it and/or modify
2266 + * it under the terms of the GNU General Public License as published by
2267 + * the Free Software Foundation; version 2 of the License
2268 + *
2269 + * This program is distributed in the hope that it will be useful,
2270 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2271 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2272 + * GNU General Public License for more details.
2273 + *
2274 + * You should have received a copy of the GNU General Public License
2275 + * along with this program; if not, write to the Free Software
2276 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2277 + *
2278 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2279 + */
2280 +
2281 +#ifndef _RALINK_GSW_MT7620_H__
2282 +#define _RALINK_GSW_MT7620_H__
2283 +
2284 +extern int mt7620_gsw_config(struct fe_priv *priv);
2285 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2286 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2287 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2288 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2289 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2290 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2291 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2292 +
2293 +#endif
2294 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio.c
2295 ===================================================================
2296 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2297 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio.c 2014-10-29 20:25:55.433357519 +0100
2298 @@ -0,0 +1,275 @@
2299 +/*
2300 + * This program is free software; you can redistribute it and/or modify
2301 + * it under the terms of the GNU General Public License as published by
2302 + * the Free Software Foundation; version 2 of the License
2303 + *
2304 + * This program is distributed in the hope that it will be useful,
2305 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2306 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2307 + * GNU General Public License for more details.
2308 + *
2309 + * You should have received a copy of the GNU General Public License
2310 + * along with this program; if not, write to the Free Software
2311 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2312 + *
2313 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2314 + */
2315 +
2316 +#include <linux/module.h>
2317 +#include <linux/kernel.h>
2318 +#include <linux/types.h>
2319 +#include <linux/dma-mapping.h>
2320 +#include <linux/init.h>
2321 +#include <linux/skbuff.h>
2322 +#include <linux/etherdevice.h>
2323 +#include <linux/ethtool.h>
2324 +#include <linux/platform_device.h>
2325 +#include <linux/phy.h>
2326 +#include <linux/of_device.h>
2327 +#include <linux/clk.h>
2328 +#include <linux/of_net.h>
2329 +#include <linux/of_mdio.h>
2330 +
2331 +#include "ralink_soc_eth.h"
2332 +#include "mdio.h"
2333 +
2334 +static int fe_mdio_reset(struct mii_bus *bus)
2335 +{
2336 + /* TODO */
2337 + return 0;
2338 +}
2339 +
2340 +static void fe_phy_link_adjust(struct net_device *dev)
2341 +{
2342 + struct fe_priv *priv = netdev_priv(dev);
2343 + unsigned long flags;
2344 + int i;
2345 +
2346 + spin_lock_irqsave(&priv->phy->lock, flags);
2347 + for (i = 0; i < 8; i++) {
2348 + if (priv->phy->phy_node[i]) {
2349 + struct phy_device *phydev = priv->phy->phy[i];
2350 + int status_change = 0;
2351 +
2352 + if (phydev->link)
2353 + if (priv->phy->duplex[i] != phydev->duplex ||
2354 + priv->phy->speed[i] != phydev->speed)
2355 + status_change = 1;
2356 +
2357 + if (phydev->link != priv->link[i])
2358 + status_change = 1;
2359 +
2360 + switch (phydev->speed) {
2361 + case SPEED_1000:
2362 + case SPEED_100:
2363 + case SPEED_10:
2364 + priv->link[i] = phydev->link;
2365 + priv->phy->duplex[i] = phydev->duplex;
2366 + priv->phy->speed[i] = phydev->speed;
2367 +
2368 + if (status_change && priv->soc->mdio_adjust_link)
2369 + priv->soc->mdio_adjust_link(priv, i);
2370 + break;
2371 + }
2372 + }
2373 + }
2374 +}
2375 +
2376 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2377 +{
2378 + const __be32 *_port = NULL;
2379 + struct phy_device *phydev;
2380 + int phy_mode, port;
2381 +
2382 + _port = of_get_property(phy_node, "reg", NULL);
2383 +
2384 + if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2385 + pr_err("%s: invalid port id\n", phy_node->name);
2386 + return -EINVAL;
2387 + }
2388 + port = be32_to_cpu(*_port);
2389 + phy_mode = of_get_phy_mode(phy_node);
2390 + if (phy_mode < 0) {
2391 + dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2392 + priv->phy->phy_node[port] = NULL;
2393 + return -EINVAL;
2394 + }
2395 +
2396 + phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2397 + 0, phy_mode);
2398 + if (IS_ERR(phydev)) {
2399 + dev_err(priv->device, "could not connect to PHY\n");
2400 + priv->phy->phy_node[port] = NULL;
2401 + return PTR_ERR(phydev);
2402 + }
2403 +
2404 + phydev->supported &= PHY_GBIT_FEATURES;
2405 + phydev->advertising = phydev->supported;
2406 + phydev->no_auto_carrier_off = 1;
2407 +
2408 + dev_info(priv->device,
2409 + "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2410 + port, dev_name(&phydev->dev), phydev->phy_id,
2411 + phydev->drv->name);
2412 +
2413 + priv->phy->phy[port] = phydev;
2414 + priv->link[port] = 0;
2415 +
2416 + return 0;
2417 +}
2418 +
2419 +static void phy_init(struct fe_priv *priv, struct phy_device *phy)
2420 +{
2421 + phy_attach(priv->netdev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
2422 +
2423 + phy->autoneg = AUTONEG_ENABLE;
2424 + phy->speed = 0;
2425 + phy->duplex = 0;
2426 + phy->supported &= PHY_BASIC_FEATURES;
2427 + phy->advertising = phy->supported | ADVERTISED_Autoneg;
2428 +
2429 + phy_start_aneg(phy);
2430 +}
2431 +
2432 +static int fe_phy_connect(struct fe_priv *priv)
2433 +{
2434 + int i;
2435 +
2436 + for (i = 0; i < 8; i++) {
2437 + if (priv->phy->phy_node[i]) {
2438 + if (!priv->phy_dev) {
2439 + priv->phy_dev = priv->phy->phy[i];
2440 + priv->phy_flags = FE_PHY_FLAG_PORT;
2441 + }
2442 + } else if (priv->mii_bus && priv->mii_bus->phy_map[i]) {
2443 + phy_init(priv, priv->mii_bus->phy_map[i]);
2444 + if (!priv->phy_dev) {
2445 + priv->phy_dev = priv->mii_bus->phy_map[i];
2446 + priv->phy_flags = FE_PHY_FLAG_ATTACH;
2447 + }
2448 + }
2449 + }
2450 +
2451 + return 0;
2452 +}
2453 +
2454 +static void fe_phy_disconnect(struct fe_priv *priv)
2455 +{
2456 + unsigned long flags;
2457 + int i;
2458 +
2459 + for (i = 0; i < 8; i++)
2460 + if (priv->phy->phy_fixed[i]) {
2461 + spin_lock_irqsave(&priv->phy->lock, flags);
2462 + priv->link[i] = 0;
2463 + if (priv->soc->mdio_adjust_link)
2464 + priv->soc->mdio_adjust_link(priv, i);
2465 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2466 + } else if (priv->phy->phy[i]) {
2467 + phy_disconnect(priv->phy->phy[i]);
2468 + } else if (priv->mii_bus && priv->mii_bus->phy_map[i]) {
2469 + phy_detach(priv->mii_bus->phy_map[i]);
2470 + }
2471 +}
2472 +
2473 +static void fe_phy_start(struct fe_priv *priv)
2474 +{
2475 + unsigned long flags;
2476 + int i;
2477 +
2478 + for (i = 0; i < 8; i++) {
2479 + if (priv->phy->phy_fixed[i]) {
2480 + spin_lock_irqsave(&priv->phy->lock, flags);
2481 + priv->link[i] = 1;
2482 + if (priv->soc->mdio_adjust_link)
2483 + priv->soc->mdio_adjust_link(priv, i);
2484 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2485 + } else if (priv->phy->phy[i]) {
2486 + phy_start(priv->phy->phy[i]);
2487 + }
2488 + }
2489 +}
2490 +
2491 +static void fe_phy_stop(struct fe_priv *priv)
2492 +{
2493 + unsigned long flags;
2494 + int i;
2495 +
2496 + for (i = 0; i < 8; i++)
2497 + if (priv->phy->phy_fixed[i]) {
2498 + spin_lock_irqsave(&priv->phy->lock, flags);
2499 + priv->link[i] = 0;
2500 + if (priv->soc->mdio_adjust_link)
2501 + priv->soc->mdio_adjust_link(priv, i);
2502 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2503 + } else if (priv->phy->phy[i]) {
2504 + phy_stop(priv->phy->phy[i]);
2505 + }
2506 +}
2507 +
2508 +static struct fe_phy phy_ralink = {
2509 + .connect = fe_phy_connect,
2510 + .disconnect = fe_phy_disconnect,
2511 + .start = fe_phy_start,
2512 + .stop = fe_phy_stop,
2513 +};
2514 +
2515 +int fe_mdio_init(struct fe_priv *priv)
2516 +{
2517 + struct device_node *mii_np;
2518 + int err;
2519 +
2520 + if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2521 + return 0;
2522 +
2523 + spin_lock_init(&phy_ralink.lock);
2524 + priv->phy = &phy_ralink;
2525 +
2526 + mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2527 + if (!mii_np) {
2528 + dev_err(priv->device, "no %s child node found", "mdio-bus");
2529 + return -ENODEV;
2530 + }
2531 +
2532 + if (!of_device_is_available(mii_np)) {
2533 + err = 0;
2534 + goto err_put_node;
2535 + }
2536 +
2537 + priv->mii_bus = mdiobus_alloc();
2538 + if (priv->mii_bus == NULL) {
2539 + err = -ENOMEM;
2540 + goto err_put_node;
2541 + }
2542 +
2543 + priv->mii_bus->name = "mdio";
2544 + priv->mii_bus->read = priv->soc->mdio_read;
2545 + priv->mii_bus->write = priv->soc->mdio_write;
2546 + priv->mii_bus->reset = fe_mdio_reset;
2547 + priv->mii_bus->priv = priv;
2548 + priv->mii_bus->parent = priv->device;
2549 +
2550 + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2551 + err = of_mdiobus_register(priv->mii_bus, mii_np);
2552 + if (err)
2553 + goto err_free_bus;
2554 +
2555 + return 0;
2556 +
2557 +err_free_bus:
2558 + kfree(priv->mii_bus);
2559 +err_put_node:
2560 + of_node_put(mii_np);
2561 + priv->mii_bus = NULL;
2562 + return err;
2563 +}
2564 +
2565 +void fe_mdio_cleanup(struct fe_priv *priv)
2566 +{
2567 + if (!priv->mii_bus)
2568 + return;
2569 +
2570 + mdiobus_unregister(priv->mii_bus);
2571 + of_node_put(priv->mii_bus->dev.of_node);
2572 + kfree(priv->mii_bus);
2573 +}
2574 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio.h
2575 ===================================================================
2576 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2577 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio.h 2014-10-29 20:25:55.433357519 +0100
2578 @@ -0,0 +1,29 @@
2579 +/*
2580 + * This program is free software; you can redistribute it and/or modify
2581 + * it under the terms of the GNU General Public License as published by
2582 + * the Free Software Foundation; version 2 of the License
2583 + *
2584 + * This program is distributed in the hope that it will be useful,
2585 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2586 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2587 + * GNU General Public License for more details.
2588 + *
2589 + * You should have received a copy of the GNU General Public License
2590 + * along with this program; if not, write to the Free Software
2591 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2592 + *
2593 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2594 + */
2595 +
2596 +#ifndef _RALINK_MDIO_H__
2597 +#define _RALINK_MDIO_H__
2598 +
2599 +#ifdef CONFIG_NET_RALINK_MDIO
2600 +extern int fe_mdio_init(struct fe_priv *priv);
2601 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2602 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2603 +#else
2604 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2605 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2606 +#endif
2607 +#endif
2608 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.c
2609 ===================================================================
2610 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2611 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.c 2014-10-29 20:25:55.433357519 +0100
2612 @@ -0,0 +1,232 @@
2613 +/*
2614 + * This program is free software; you can redistribute it and/or modify
2615 + * it under the terms of the GNU General Public License as published by
2616 + * the Free Software Foundation; version 2 of the License
2617 + *
2618 + * This program is distributed in the hope that it will be useful,
2619 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2620 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2621 + * GNU General Public License for more details.
2622 + *
2623 + * You should have received a copy of the GNU General Public License
2624 + * along with this program; if not, write to the Free Software
2625 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2626 + *
2627 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2628 + */
2629 +
2630 +#include <linux/module.h>
2631 +#include <linux/kernel.h>
2632 +#include <linux/types.h>
2633 +#include <linux/dma-mapping.h>
2634 +#include <linux/init.h>
2635 +#include <linux/skbuff.h>
2636 +#include <linux/etherdevice.h>
2637 +#include <linux/ethtool.h>
2638 +#include <linux/platform_device.h>
2639 +#include <linux/phy.h>
2640 +#include <linux/of_device.h>
2641 +#include <linux/clk.h>
2642 +#include <linux/of_net.h>
2643 +#include <linux/of_mdio.h>
2644 +
2645 +#include "ralink_soc_eth.h"
2646 +#include "mdio_rt2880.h"
2647 +#include "mdio.h"
2648 +
2649 +#define FE_MDIO_RETRY 1000
2650 +
2651 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2652 +{
2653 + switch (priv->phy->speed[0]) {
2654 + case SPEED_1000:
2655 + return "1000";
2656 + case SPEED_100:
2657 + return "100";
2658 + case SPEED_10:
2659 + return "10";
2660 + }
2661 +
2662 + return "?";
2663 +}
2664 +
2665 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2666 +{
2667 + u32 mdio_cfg;
2668 +
2669 + if (!priv->link[0]) {
2670 + netif_carrier_off(priv->netdev);
2671 + netdev_info(priv->netdev, "link down\n");
2672 + return;
2673 + }
2674 +
2675 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2676 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
2677 + FE_MDIO_CFG_GP1_FRC_EN;
2678 +
2679 + if (priv->phy->duplex[0] == DUPLEX_FULL)
2680 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2681 +
2682 + if (priv->phy->tx_fc[0])
2683 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2684 +
2685 + if (priv->phy->rx_fc[0])
2686 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2687 +
2688 + switch (priv->phy->speed[0]) {
2689 + case SPEED_10:
2690 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2691 + break;
2692 + case SPEED_100:
2693 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2694 + break;
2695 + case SPEED_1000:
2696 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2697 + break;
2698 + default:
2699 + BUG();
2700 + }
2701 +
2702 + fe_w32(mdio_cfg, FE_MDIO_CFG);
2703 +
2704 + netif_carrier_on(priv->netdev);
2705 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2706 + rt2880_speed_str(priv),
2707 + (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2708 +}
2709 +
2710 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2711 +{
2712 + int retries;
2713 +
2714 + retries = FE_MDIO_RETRY;
2715 + while (1) {
2716 + u32 t;
2717 +
2718 + t = fe_r32(FE_MDIO_ACCESS);
2719 + if ((t & (0x1 << 31)) == 0)
2720 + return 0;
2721 +
2722 + if (retries-- == 0)
2723 + break;
2724 +
2725 + udelay(1);
2726 + }
2727 +
2728 + dev_err(priv->device, "MDIO operation timed out\n");
2729 + return -ETIMEDOUT;
2730 +}
2731 +
2732 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2733 +{
2734 + struct fe_priv *priv = bus->priv;
2735 + int err;
2736 + u32 t;
2737 +
2738 + err = rt2880_mdio_wait_ready(priv);
2739 + if (err)
2740 + return 0xffff;
2741 +
2742 + t = (phy_addr << 24) | (phy_reg << 16);
2743 + fe_w32(t, FE_MDIO_ACCESS);
2744 + t |= (1 << 31);
2745 + fe_w32(t, FE_MDIO_ACCESS);
2746 +
2747 + err = rt2880_mdio_wait_ready(priv);
2748 + if (err)
2749 + return 0xffff;
2750 +
2751 + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2752 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2753 +
2754 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2755 +}
2756 +
2757 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2758 +{
2759 + struct fe_priv *priv = bus->priv;
2760 + int err;
2761 + u32 t;
2762 +
2763 + pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2764 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2765 +
2766 + err = rt2880_mdio_wait_ready(priv);
2767 + if (err)
2768 + return err;
2769 +
2770 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2771 + fe_w32(t, FE_MDIO_ACCESS);
2772 + t |= (1 << 31);
2773 + fe_w32(t, FE_MDIO_ACCESS);
2774 +
2775 + return rt2880_mdio_wait_ready(priv);
2776 +}
2777 +
2778 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2779 +{
2780 + const __be32 *id = of_get_property(np, "reg", NULL);
2781 + const __be32 *link;
2782 + int size;
2783 + int phy_mode;
2784 +
2785 + if (!id || (be32_to_cpu(*id) != 0)) {
2786 + pr_err("%s: invalid port id\n", np->name);
2787 + return;
2788 + }
2789 +
2790 + priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2791 + if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2792 + pr_err("%s: invalid fixed link property\n", np->name);
2793 + priv->phy->phy_fixed[0] = NULL;
2794 + return;
2795 + }
2796 +
2797 + phy_mode = of_get_phy_mode(np);
2798 + switch (phy_mode) {
2799 + case PHY_INTERFACE_MODE_RGMII:
2800 + break;
2801 + case PHY_INTERFACE_MODE_MII:
2802 + break;
2803 + case PHY_INTERFACE_MODE_RMII:
2804 + break;
2805 + default:
2806 + if (!priv->phy->phy_fixed[0])
2807 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2808 + break;
2809 + }
2810 +
2811 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2812 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2813 + return;
2814 +
2815 + if (priv->phy->phy_fixed[0]) {
2816 + link = priv->phy->phy_fixed[0];
2817 + priv->phy->speed[0] = be32_to_cpup(link++);
2818 + priv->phy->duplex[0] = be32_to_cpup(link++);
2819 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
2820 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
2821 +
2822 + priv->link[0] = 1;
2823 + switch (priv->phy->speed[0]) {
2824 + case SPEED_10:
2825 + break;
2826 + case SPEED_100:
2827 + break;
2828 + case SPEED_1000:
2829 + break;
2830 + default:
2831 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2832 + priv->phy->phy_fixed[0] = 0;
2833 + return;
2834 + }
2835 + dev_info(priv->device, "using fixed link parameters\n");
2836 + rt2880_mdio_link_adjust(priv, 0);
2837 + return;
2838 + }
2839 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2840 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2841 + }
2842 +
2843 + return;
2844 +}
2845 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.h
2846 ===================================================================
2847 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2848 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.h 2014-10-29 20:25:55.433357519 +0100
2849 @@ -0,0 +1,26 @@
2850 +/*
2851 + * This program is free software; you can redistribute it and/or modify
2852 + * it under the terms of the GNU General Public License as published by
2853 + * the Free Software Foundation; version 2 of the License
2854 + *
2855 + * This program is distributed in the hope that it will be useful,
2856 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2857 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2858 + * GNU General Public License for more details.
2859 + *
2860 + * You should have received a copy of the GNU General Public License
2861 + * along with this program; if not, write to the Free Software
2862 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2863 + *
2864 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2865 + */
2866 +
2867 +#ifndef _RALINK_MDIO_RT2880_H__
2868 +#define _RALINK_MDIO_RT2880_H__
2869 +
2870 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2871 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2872 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2873 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2874 +
2875 +#endif
2876 Index: linux-3.14.18/drivers/net/ethernet/ralink/mt7530.c
2877 ===================================================================
2878 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2879 +++ linux-3.14.18/drivers/net/ethernet/ralink/mt7530.c 2014-10-29 20:32:49.124597652 +0100
2880 @@ -0,0 +1,582 @@
2881 +/*
2882 + * This program is free software; you can redistribute it and/or
2883 + * modify it under the terms of the GNU General Public License
2884 + * as published by the Free Software Foundation; either version 2
2885 + * of the License, or (at your option) any later version.
2886 + *
2887 + * This program is distributed in the hope that it will be useful,
2888 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2889 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2890 + * GNU General Public License for more details.
2891 + *
2892 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
2893 + */
2894 +
2895 +#include <linux/if.h>
2896 +#include <linux/module.h>
2897 +#include <linux/init.h>
2898 +#include <linux/list.h>
2899 +#include <linux/if_ether.h>
2900 +#include <linux/skbuff.h>
2901 +#include <linux/netdevice.h>
2902 +#include <linux/netlink.h>
2903 +#include <linux/bitops.h>
2904 +#include <net/genetlink.h>
2905 +#include <linux/switch.h>
2906 +#include <linux/delay.h>
2907 +#include <linux/phy.h>
2908 +#include <linux/netdevice.h>
2909 +#include <linux/etherdevice.h>
2910 +#include <linux/lockdep.h>
2911 +#include <linux/workqueue.h>
2912 +#include <linux/of_device.h>
2913 +
2914 +#include "mt7530.h"
2915 +
2916 +#define MT7530_CPU_PORT 6
2917 +#define MT7530_NUM_PORTS 8
2918 +#define MT7530_NUM_VLANS 16
2919 +#define MT7530_MAX_VID 4095
2920 +#define MT7530_MIN_VID 0
2921 +
2922 +/* registers */
2923 +#define REG_ESW_VLAN_VTCR 0x90
2924 +#define REG_ESW_VLAN_VAWD1 0x94
2925 +#define REG_ESW_VLAN_VAWD2 0x98
2926 +#define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
2927 +
2928 +#define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
2929 +#define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
2930 +#define REG_ESW_VLAN_VAWD1_VALID BIT(0)
2931 +
2932 +/* vlan egress mode */
2933 +enum {
2934 + ETAG_CTRL_UNTAG = 0,
2935 + ETAG_CTRL_TAG = 2,
2936 + ETAG_CTRL_SWAP = 1,
2937 + ETAG_CTRL_STACK = 3,
2938 +};
2939 +
2940 +#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
2941 +#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
2942 +#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
2943 +enum {
2944 + /* Global attributes. */
2945 + MT7530_ATTR_ENABLE_VLAN,
2946 +};
2947 +
2948 +struct mt7530_port_entry {
2949 + u16 pvid;
2950 +};
2951 +
2952 +struct mt7530_vlan_entry {
2953 + u16 vid;
2954 + u8 member;
2955 + u8 etags;
2956 +};
2957 +
2958 +struct mt7530_priv {
2959 + void __iomem *base;
2960 + struct mii_bus *bus;
2961 + struct switch_dev swdev;
2962 +
2963 + bool global_vlan_enable;
2964 + struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
2965 + struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
2966 +};
2967 +
2968 +struct mt7530_mapping {
2969 + char *name;
2970 + u16 pvids[MT7530_NUM_PORTS];
2971 + u8 members[MT7530_NUM_VLANS];
2972 + u8 etags[MT7530_NUM_VLANS];
2973 + u16 vids[MT7530_NUM_VLANS];
2974 +} mt7530_defaults[] = {
2975 + {
2976 + .name = "llllw",
2977 + .pvids = { 1, 1, 1, 1, 2, 1, 1 },
2978 + .members = { 0, 0x6f, 0x50 },
2979 + .etags = { 0, 0x40, 0x40 },
2980 + .vids = { 0, 1, 2 },
2981 + }, {
2982 + .name = "wllll",
2983 + .pvids = { 2, 1, 1, 1, 1, 1, 1 },
2984 + .members = { 0, 0x7e, 0x41 },
2985 + .etags = { 0, 0x40, 0x40 },
2986 + .vids = { 0, 1, 2 },
2987 + },
2988 +};
2989 +
2990 +struct mt7530_mapping*
2991 +mt7530_find_mapping(struct device_node *np)
2992 +{
2993 + const char *map;
2994 + int i;
2995 +
2996 + if (of_property_read_string(np, "ralink,port-map", &map))
2997 + return NULL;
2998 +
2999 + for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
3000 + if (!strcmp(map, mt7530_defaults[i].name))
3001 + return &mt7530_defaults[i];
3002 +
3003 + return NULL;
3004 +}
3005 +
3006 +static void
3007 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
3008 +{
3009 + int i = 0;
3010 +
3011 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3012 + mt7530->port_entries[i].pvid = map->pvids[i];
3013 +
3014 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
3015 + mt7530->vlan_entries[i].member = map->members[i];
3016 + mt7530->vlan_entries[i].etags = map->etags[i];
3017 + mt7530->vlan_entries[i].vid = map->vids[i];
3018 + }
3019 +}
3020 +
3021 +static int
3022 +mt7530_reset_switch(struct switch_dev *dev)
3023 +{
3024 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3025 + int i;
3026 +
3027 + memset(priv->port_entries, 0, sizeof(priv->port_entries));
3028 + memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
3029 +
3030 + /* set default vid of each vlan to the same number of vlan, so the vid
3031 + * won't need be set explicitly.
3032 + */
3033 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
3034 + priv->vlan_entries[i].vid = i;
3035 + }
3036 +
3037 + return 0;
3038 +}
3039 +
3040 +static int
3041 +mt7530_get_vlan_enable(struct switch_dev *dev,
3042 + const struct switch_attr *attr,
3043 + struct switch_val *val)
3044 +{
3045 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3046 +
3047 + val->value.i = priv->global_vlan_enable;
3048 +
3049 + return 0;
3050 +}
3051 +
3052 +static int
3053 +mt7530_set_vlan_enable(struct switch_dev *dev,
3054 + const struct switch_attr *attr,
3055 + struct switch_val *val)
3056 +{
3057 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3058 +
3059 + priv->global_vlan_enable = val->value.i != 0;
3060 +
3061 + return 0;
3062 +}
3063 +
3064 +static u32
3065 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
3066 +{
3067 + u32 val;
3068 + if (priv->bus) {
3069 + u16 high, low;
3070 +
3071 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3072 + low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
3073 + high = mdiobus_read(priv->bus, 0x1f, 0x10);
3074 +
3075 + return (high << 16) | (low & 0xffff);
3076 + }
3077 +
3078 + val = ioread32(priv->base + reg);
3079 + pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
3080 +
3081 + return val;
3082 +}
3083 +
3084 +static void
3085 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
3086 +{
3087 + if (priv->bus) {
3088 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3089 + mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
3090 + mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
3091 + return;
3092 + }
3093 +
3094 + pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
3095 + iowrite32(val, priv->base + reg);
3096 +}
3097 +
3098 +static void
3099 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
3100 +{
3101 + int i;
3102 +
3103 + mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
3104 +
3105 + for (i = 0; i < 20; i++) {
3106 + u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
3107 +
3108 + if ((val & BIT(31)) == 0)
3109 + break;
3110 +
3111 + udelay(1000);
3112 + }
3113 + if (i == 20)
3114 + printk("mt7530: vtcr timeout\n");
3115 +}
3116 +
3117 +static int
3118 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
3119 +{
3120 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3121 +
3122 + if (port >= MT7530_NUM_PORTS)
3123 + return -EINVAL;
3124 +
3125 + *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
3126 + *val &= 0xfff;
3127 +
3128 + return 0;
3129 +}
3130 +
3131 +static int
3132 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
3133 +{
3134 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3135 +
3136 + if (port >= MT7530_NUM_PORTS)
3137 + return -EINVAL;
3138 +
3139 + if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
3140 + return -EINVAL;
3141 +
3142 + priv->port_entries[port].pvid = pvid;
3143 +
3144 + return 0;
3145 +}
3146 +
3147 +static int
3148 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3149 +{
3150 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3151 + u32 member;
3152 + u32 etags;
3153 + int i;
3154 +
3155 + val->len = 0;
3156 +
3157 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
3158 + return -EINVAL;
3159 +
3160 + mt7530_vtcr(priv, 0, val->port_vlan);
3161 +
3162 + member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
3163 + member >>= 16;
3164 + member &= 0xff;
3165 +
3166 + etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
3167 +
3168 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
3169 + struct switch_port *p;
3170 + int etag;
3171 +
3172 + if (!(member & BIT(i)))
3173 + continue;
3174 +
3175 + p = &val->value.ports[val->len++];
3176 + p->id = i;
3177 +
3178 + etag = (etags >> (i * 2)) & 0x3;
3179 +
3180 + if (etag == ETAG_CTRL_TAG)
3181 + p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
3182 + else if (etag != ETAG_CTRL_UNTAG)
3183 + printk("vlan egress tag control neither untag nor tag.\n");
3184 + }
3185 +
3186 + return 0;
3187 +}
3188 +
3189 +static int
3190 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3191 +{
3192 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3193 + u8 member = 0;
3194 + u8 etags = 0;
3195 + int i;
3196 +
3197 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
3198 + val->len > MT7530_NUM_PORTS)
3199 + return -EINVAL;
3200 +
3201 + for (i = 0; i < val->len; i++) {
3202 + struct switch_port *p = &val->value.ports[i];
3203 +
3204 + if (p->id >= MT7530_NUM_PORTS)
3205 + return -EINVAL;
3206 +
3207 + member |= BIT(p->id);
3208 +
3209 + if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
3210 + etags |= BIT(p->id);
3211 + }
3212 + priv->vlan_entries[val->port_vlan].member = member;
3213 + priv->vlan_entries[val->port_vlan].etags = etags;
3214 +
3215 + return 0;
3216 +}
3217 +
3218 +static int
3219 +mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
3220 + struct switch_val *val)
3221 +{
3222 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3223 + int vlan;
3224 + u16 vid;
3225 +
3226 + vlan = val->port_vlan;
3227 + vid = (u16)val->value.i;
3228 +
3229 + if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
3230 + return -EINVAL;
3231 +
3232 + if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
3233 + return -EINVAL;
3234 +
3235 + priv->vlan_entries[vlan].vid = vid;
3236 + return 0;
3237 +}
3238 +
3239 +static int
3240 +mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
3241 + struct switch_val *val)
3242 +{
3243 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3244 + u32 vid;
3245 + int vlan;
3246 +
3247 + vlan = val->port_vlan;
3248 +
3249 + vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
3250 + if (vlan & 1)
3251 + vid = vid >> 12;
3252 + vid &= 0xfff;
3253 +
3254 + val->value.i = vid;
3255 + return 0;
3256 +}
3257 +
3258 +static int
3259 +mt7530_apply_config(struct switch_dev *dev)
3260 +{
3261 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3262 + int i, j;
3263 +
3264 + if (!priv->global_vlan_enable) {
3265 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3266 + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0000);
3267 +
3268 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3269 + mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
3270 +
3271 + return 0;
3272 + }
3273 +
3274 + /* set all ports as security mode */
3275 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3276 + mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
3277 +
3278 + /* set all ports as user port */
3279 + for (i = 0; i < MT7530_NUM_PORTS; i++)
3280 + mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x81000000);
3281 +
3282 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
3283 + u16 vid = priv->vlan_entries[i].vid;
3284 + u8 member = priv->vlan_entries[i].member;
3285 + u8 etags = priv->vlan_entries[i].etags;
3286 + u32 val;
3287 +
3288 + /* vid of vlan */
3289 + val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
3290 + if (i % 2 == 0) {
3291 + val &= 0xfff000;
3292 + val |= vid;
3293 + } else {
3294 + val &= 0xfff;
3295 + val |= (vid << 12);
3296 + }
3297 + mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
3298 +
3299 + /* vlan port membership */
3300 + if (member)
3301 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
3302 + REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
3303 + REG_ESW_VLAN_VAWD1_VALID);
3304 + else
3305 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
3306 +
3307 + /* egress mode */
3308 + val = 0;
3309 + for (j = 0; j < MT7530_NUM_PORTS; j++) {
3310 + if (etags & BIT(j))
3311 + val |= ETAG_CTRL_TAG << (j * 2);
3312 + else
3313 + val |= ETAG_CTRL_UNTAG << (j * 2);
3314 + }
3315 + mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
3316 +
3317 + /* write to vlan table */
3318 + mt7530_vtcr(priv, 1, i);
3319 + }
3320 +
3321 + /* Port Default PVID */
3322 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
3323 + u32 val;
3324 + val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
3325 + val &= ~0xfff;
3326 + val |= priv->port_entries[i].pvid;
3327 + mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
3328 + }
3329 +
3330 + return 0;
3331 +}
3332 +
3333 +static int
3334 +mt7530_get_port_link(struct switch_dev *dev, int port,
3335 + struct switch_port_link *link)
3336 +{
3337 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3338 + u32 speed, pmsr;
3339 +
3340 + if (port < 0 || port >= MT7530_NUM_PORTS)
3341 + return -EINVAL;
3342 +
3343 + pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
3344 +
3345 + link->link = pmsr & 1;
3346 + link->duplex = (pmsr >> 1) & 1;
3347 + speed = (pmsr >> 2) & 3;
3348 +
3349 + switch (speed) {
3350 + case 0:
3351 + link->speed = SWITCH_PORT_SPEED_10;
3352 + break;
3353 + case 1:
3354 + link->speed = SWITCH_PORT_SPEED_100;
3355 + break;
3356 + case 2:
3357 + case 3: /* forced gige speed can be 2 or 3 */
3358 + link->speed = SWITCH_PORT_SPEED_1000;
3359 + break;
3360 + default:
3361 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
3362 + break;
3363 + }
3364 +
3365 + return 0;
3366 +}
3367 +
3368 +static const struct switch_attr mt7530_global[] = {
3369 + {
3370 + .type = SWITCH_TYPE_INT,
3371 + .name = "enable_vlan",
3372 + .description = "VLAN mode (1:enabled)",
3373 + .max = 1,
3374 + .id = MT7530_ATTR_ENABLE_VLAN,
3375 + .get = mt7530_get_vlan_enable,
3376 + .set = mt7530_set_vlan_enable,
3377 + },
3378 +};
3379 +
3380 +static const struct switch_attr mt7530_port[] = {
3381 +};
3382 +
3383 +static const struct switch_attr mt7530_vlan[] = {
3384 + {
3385 + .type = SWITCH_TYPE_INT,
3386 + .name = "vid",
3387 + .description = "VLAN ID (0-4094)",
3388 + .set = mt7530_set_vid,
3389 + .get = mt7530_get_vid,
3390 + .max = 4094,
3391 + },
3392 +};
3393 +
3394 +static const struct switch_dev_ops mt7530_ops = {
3395 + .attr_global = {
3396 + .attr = mt7530_global,
3397 + .n_attr = ARRAY_SIZE(mt7530_global),
3398 + },
3399 + .attr_port = {
3400 + .attr = mt7530_port,
3401 + .n_attr = ARRAY_SIZE(mt7530_port),
3402 + },
3403 + .attr_vlan = {
3404 + .attr = mt7530_vlan,
3405 + .n_attr = ARRAY_SIZE(mt7530_vlan),
3406 + },
3407 + .get_vlan_ports = mt7530_get_vlan_ports,
3408 + .set_vlan_ports = mt7530_set_vlan_ports,
3409 + .get_port_pvid = mt7530_get_port_pvid,
3410 + .set_port_pvid = mt7530_set_port_pvid,
3411 + .get_port_link = mt7530_get_port_link,
3412 + .apply_config = mt7530_apply_config,
3413 + .reset_switch = mt7530_reset_switch,
3414 +};
3415 +
3416 +int
3417 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
3418 +{
3419 + struct switch_dev *swdev;
3420 + struct mt7530_priv *mt7530;
3421 + struct mt7530_mapping *map;
3422 + int ret;
3423 +
3424 + if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
3425 + return 0;
3426 +
3427 + mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
3428 + if (!mt7530)
3429 + return -ENOMEM;
3430 +
3431 + mt7530->base = base;
3432 + mt7530->bus = bus;
3433 + mt7530->global_vlan_enable = vlan;
3434 +
3435 + swdev = &mt7530->swdev;
3436 + if (bus) {
3437 + swdev->alias = "mt7530";
3438 + swdev->name = "mt7530";
3439 + } else {
3440 + swdev->alias = "mt7620";
3441 + swdev->name = "mt7620";
3442 + }
3443 + swdev->cpu_port = MT7530_CPU_PORT;
3444 + swdev->ports = MT7530_NUM_PORTS;
3445 + swdev->vlans = MT7530_NUM_VLANS;
3446 + swdev->ops = &mt7530_ops;
3447 +
3448 + ret = register_switch(swdev, NULL);
3449 + if (ret) {
3450 + dev_err(dev, "failed to register mt7530\n");
3451 + return ret;
3452 + }
3453 +
3454 + dev_info(dev, "loaded %s driver\n", swdev->name);
3455 +
3456 + map = mt7530_find_mapping(dev->of_node);
3457 + if (map)
3458 + mt7530_apply_mapping(mt7530, map);
3459 + mt7530_apply_config(swdev);
3460 +
3461 + return 0;
3462 +}
3463 Index: linux-3.14.18/drivers/net/ethernet/ralink/mt7530.h
3464 ===================================================================
3465 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3466 +++ linux-3.14.18/drivers/net/ethernet/ralink/mt7530.h 2014-10-29 20:30:49.296185172 +0100
3467 @@ -0,0 +1,20 @@
3468 +/*
3469 + * This program is free software; you can redistribute it and/or
3470 + * modify it under the terms of the GNU General Public License
3471 + * as published by the Free Software Foundation; either version 2
3472 + * of the License, or (at your option) any later version.
3473 + *
3474 + * This program is distributed in the hope that it will be useful,
3475 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3476 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3477 + * GNU General Public License for more details.
3478 + *
3479 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
3480 + */
3481 +
3482 +#ifndef _MT7530_H__
3483 +#define _MT7530_H__
3484 +
3485 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
3486 +
3487 +#endif
3488 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.c
3489 ===================================================================
3490 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3491 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.c 2014-10-29 20:25:55.433357519 +0100
3492 @@ -0,0 +1,1331 @@
3493 +/*
3494 + * This program is free software; you can redistribute it and/or modify
3495 + * it under the terms of the GNU General Public License as published by
3496 + * the Free Software Foundation; version 2 of the License
3497 + *
3498 + * This program is distributed in the hope that it will be useful,
3499 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3500 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3501 + * GNU General Public License for more details.
3502 + *
3503 + * You should have received a copy of the GNU General Public License
3504 + * along with this program; if not, write to the Free Software
3505 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3506 + *
3507 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3508 + */
3509 +
3510 +#include <linux/module.h>
3511 +#include <linux/kernel.h>
3512 +#include <linux/types.h>
3513 +#include <linux/dma-mapping.h>
3514 +#include <linux/init.h>
3515 +#include <linux/skbuff.h>
3516 +#include <linux/etherdevice.h>
3517 +#include <linux/ethtool.h>
3518 +#include <linux/platform_device.h>
3519 +#include <linux/of_device.h>
3520 +#include <linux/clk.h>
3521 +#include <linux/of_net.h>
3522 +#include <linux/of_mdio.h>
3523 +#include <linux/if_vlan.h>
3524 +#include <linux/reset.h>
3525 +#include <linux/tcp.h>
3526 +#include <linux/io.h>
3527 +
3528 +#include <asm/mach-ralink/ralink_regs.h>
3529 +
3530 +#include "ralink_soc_eth.h"
3531 +#include "esw_rt3052.h"
3532 +#include "mdio.h"
3533 +#include "ralink_ethtool.h"
3534 +
3535 +#define TX_TIMEOUT (2 * HZ)
3536 +#define MAX_RX_LENGTH 1536
3537 +#define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
3538 +#define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
3539 + ETH_FCS_LEN)
3540 +#define DMA_DUMMY_DESC 0xffffffff
3541 +#define FE_DEFAULT_MSG_ENABLE \
3542 + (NETIF_MSG_DRV | \
3543 + NETIF_MSG_PROBE | \
3544 + NETIF_MSG_LINK | \
3545 + NETIF_MSG_TIMER | \
3546 + NETIF_MSG_IFDOWN | \
3547 + NETIF_MSG_IFUP | \
3548 + NETIF_MSG_RX_ERR | \
3549 + NETIF_MSG_TX_ERR)
3550 +
3551 +#define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
3552 +#define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
3553 +#define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
3554 +#define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
3555 +
3556 +static int fe_msg_level = -1;
3557 +module_param_named(msg_level, fe_msg_level, int, 0);
3558 +MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
3559 +
3560 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3561 + [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3562 + [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3563 + [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3564 + [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3565 + [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3566 + [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3567 + [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3568 + [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3569 + [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3570 + [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3571 + [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3572 + [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
3573 + [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
3574 +};
3575 +
3576 +static const u32 *fe_reg_table = fe_reg_table_default;
3577 +
3578 +static void __iomem *fe_base = 0;
3579 +
3580 +void fe_w32(u32 val, unsigned reg)
3581 +{
3582 + __raw_writel(val, fe_base + reg);
3583 +}
3584 +
3585 +u32 fe_r32(unsigned reg)
3586 +{
3587 + return __raw_readl(fe_base + reg);
3588 +}
3589 +
3590 +void fe_reg_w32(u32 val, enum fe_reg reg)
3591 +{
3592 + fe_w32(val, fe_reg_table[reg]);
3593 +}
3594 +
3595 +u32 fe_reg_r32(enum fe_reg reg)
3596 +{
3597 + return fe_r32(fe_reg_table[reg]);
3598 +}
3599 +
3600 +static inline void fe_int_disable(u32 mask)
3601 +{
3602 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3603 + FE_REG_FE_INT_ENABLE);
3604 + /* flush write */
3605 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3606 +}
3607 +
3608 +static inline void fe_int_enable(u32 mask)
3609 +{
3610 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3611 + FE_REG_FE_INT_ENABLE);
3612 + /* flush write */
3613 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
3614 +}
3615 +
3616 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3617 +{
3618 + unsigned long flags;
3619 +
3620 + spin_lock_irqsave(&priv->page_lock, flags);
3621 + fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3622 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3623 + FE_GDMA1_MAC_ADRL);
3624 + spin_unlock_irqrestore(&priv->page_lock, flags);
3625 +}
3626 +
3627 +static int fe_set_mac_address(struct net_device *dev, void *p)
3628 +{
3629 + int ret = eth_mac_addr(dev, p);
3630 +
3631 + if (!ret) {
3632 + struct fe_priv *priv = netdev_priv(dev);
3633 +
3634 + if (priv->soc->set_mac)
3635 + priv->soc->set_mac(priv, dev->dev_addr);
3636 + else
3637 + fe_hw_set_macaddr(priv, p);
3638 + }
3639 +
3640 + return ret;
3641 +}
3642 +
3643 +static inline int fe_max_frag_size(int mtu)
3644 +{
3645 + return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
3646 + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3647 +}
3648 +
3649 +static inline int fe_max_buf_size(int frag_size)
3650 +{
3651 + return frag_size - FE_RX_HLEN -
3652 + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3653 +}
3654 +
3655 +static void fe_clean_rx(struct fe_priv *priv)
3656 +{
3657 + int i;
3658 +
3659 + if (priv->rx_data) {
3660 + for (i = 0; i < NUM_DMA_DESC; i++)
3661 + if (priv->rx_data[i]) {
3662 + if (priv->rx_dma && priv->rx_dma[i].rxd1)
3663 + dma_unmap_single(&priv->netdev->dev,
3664 + priv->rx_dma[i].rxd1,
3665 + priv->rx_buf_size,
3666 + DMA_FROM_DEVICE);
3667 + put_page(virt_to_head_page(priv->rx_data[i]));
3668 + }
3669 +
3670 + kfree(priv->rx_data);
3671 + priv->rx_data = NULL;
3672 + }
3673 +
3674 + if (priv->rx_dma) {
3675 + dma_free_coherent(&priv->netdev->dev,
3676 + NUM_DMA_DESC * sizeof(*priv->rx_dma),
3677 + priv->rx_dma,
3678 + priv->rx_phys);
3679 + priv->rx_dma = NULL;
3680 + }
3681 +}
3682 +
3683 +static int fe_alloc_rx(struct fe_priv *priv)
3684 +{
3685 + struct net_device *netdev = priv->netdev;
3686 + int i;
3687 +
3688 + priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
3689 + GFP_KERNEL);
3690 + if (!priv->rx_data)
3691 + goto no_rx_mem;
3692 +
3693 + for (i = 0; i < NUM_DMA_DESC; i++) {
3694 + priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
3695 + if (!priv->rx_data[i])
3696 + goto no_rx_mem;
3697 + }
3698 +
3699 + priv->rx_dma = dma_alloc_coherent(&netdev->dev,
3700 + NUM_DMA_DESC * sizeof(*priv->rx_dma),
3701 + &priv->rx_phys,
3702 + GFP_ATOMIC | __GFP_ZERO);
3703 + if (!priv->rx_dma)
3704 + goto no_rx_mem;
3705 +
3706 + for (i = 0; i < NUM_DMA_DESC; i++) {
3707 + dma_addr_t dma_addr = dma_map_single(&netdev->dev,
3708 + priv->rx_data[i] + FE_RX_OFFSET,
3709 + priv->rx_buf_size,
3710 + DMA_FROM_DEVICE);
3711 + if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
3712 + goto no_rx_mem;
3713 + priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3714 +
3715 + if (priv->soc->rx_dma)
3716 + priv->soc->rx_dma(priv, i, priv->rx_buf_size);
3717 + else
3718 + priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3719 + }
3720 + wmb();
3721 +
3722 + fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3723 + fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3724 + fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3725 + fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3726 +
3727 + return 0;
3728 +
3729 +no_rx_mem:
3730 + return -ENOMEM;
3731 +}
3732 +
3733 +static void fe_clean_tx(struct fe_priv *priv)
3734 +{
3735 + int i;
3736 +
3737 + if (priv->tx_skb) {
3738 + for (i = 0; i < NUM_DMA_DESC; i++) {
3739 + if (priv->tx_skb[i])
3740 + dev_kfree_skb_any(priv->tx_skb[i]);
3741 + }
3742 + kfree(priv->tx_skb);
3743 + priv->tx_skb = NULL;
3744 + }
3745 +
3746 + if (priv->tx_dma) {
3747 + dma_free_coherent(&priv->netdev->dev,
3748 + NUM_DMA_DESC * sizeof(*priv->tx_dma),
3749 + priv->tx_dma,
3750 + priv->tx_phys);
3751 + priv->tx_dma = NULL;
3752 + }
3753 +}
3754 +
3755 +static int fe_alloc_tx(struct fe_priv *priv)
3756 +{
3757 + int i;
3758 +
3759 + priv->tx_free_idx = 0;
3760 +
3761 + priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
3762 + GFP_KERNEL);
3763 + if (!priv->tx_skb)
3764 + goto no_tx_mem;
3765 +
3766 + priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
3767 + NUM_DMA_DESC * sizeof(*priv->tx_dma),
3768 + &priv->tx_phys,
3769 + GFP_ATOMIC | __GFP_ZERO);
3770 + if (!priv->tx_dma)
3771 + goto no_tx_mem;
3772 +
3773 + for (i = 0; i < NUM_DMA_DESC; i++) {
3774 + if (priv->soc->tx_dma) {
3775 + priv->soc->tx_dma(priv, i, NULL);
3776 + continue;
3777 + }
3778 + priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
3779 + }
3780 + wmb();
3781 +
3782 + fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3783 + fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3784 + fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3785 + fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3786 +
3787 + return 0;
3788 +
3789 +no_tx_mem:
3790 + return -ENOMEM;
3791 +}
3792 +
3793 +static int fe_init_dma(struct fe_priv *priv)
3794 +{
3795 + int err;
3796 +
3797 + err = fe_alloc_tx(priv);
3798 + if (err)
3799 + return err;
3800 +
3801 + err = fe_alloc_rx(priv);
3802 + if (err)
3803 + return err;
3804 +
3805 + return 0;
3806 +}
3807 +
3808 +static void fe_free_dma(struct fe_priv *priv)
3809 +{
3810 + fe_clean_tx(priv);
3811 + fe_clean_rx(priv);
3812 +
3813 + netdev_reset_queue(priv->netdev);
3814 +}
3815 +
3816 +static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
3817 +{
3818 + if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
3819 + dma_unmap_single(dev, txd->txd1,
3820 + TX_DMA_GET_PLEN0(txd->txd2),
3821 + DMA_TO_DEVICE);
3822 +}
3823 +
3824 +static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
3825 +{
3826 + if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
3827 + dma_unmap_page(dev, txd->txd1,
3828 + TX_DMA_GET_PLEN0(txd->txd2),
3829 + DMA_TO_DEVICE);
3830 +}
3831 +
3832 +static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
3833 +{
3834 + if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
3835 + dma_unmap_page(dev, txd->txd3,
3836 + TX_DMA_GET_PLEN1(txd->txd2),
3837 + DMA_TO_DEVICE);
3838 +}
3839 +
3840 +void fe_stats_update(struct fe_priv *priv)
3841 +{
3842 + struct fe_hw_stats *hwstats = priv->hw_stats;
3843 + unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
3844 +
3845 + u64_stats_update_begin(&hwstats->syncp);
3846 +
3847 + hwstats->tx_bytes += fe_r32(base);
3848 + hwstats->tx_packets += fe_r32(base + 0x04);
3849 + hwstats->tx_skip += fe_r32(base + 0x08);
3850 + hwstats->tx_collisions += fe_r32(base + 0x0c);
3851 + hwstats->rx_bytes += fe_r32(base + 0x20);
3852 + hwstats->rx_packets += fe_r32(base + 0x24);
3853 + hwstats->rx_overflow += fe_r32(base + 0x28);
3854 + hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
3855 + hwstats->rx_short_errors += fe_r32(base + 0x30);
3856 + hwstats->rx_long_errors += fe_r32(base + 0x34);
3857 + hwstats->rx_checksum_errors += fe_r32(base + 0x38);
3858 + hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
3859 +
3860 + u64_stats_update_end(&hwstats->syncp);
3861 +}
3862 +
3863 +static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
3864 + struct rtnl_link_stats64 *storage)
3865 +{
3866 + struct fe_priv *priv = netdev_priv(dev);
3867 + struct fe_hw_stats *hwstats = priv->hw_stats;
3868 + unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
3869 + unsigned int start;
3870 +
3871 + if (!base) {
3872 + netdev_stats_to_stats64(storage, &dev->stats);
3873 + return storage;
3874 + }
3875 +
3876 + if (netif_running(dev) && netif_device_present(dev)) {
3877 + if (spin_trylock(&hwstats->stats_lock)) {
3878 + fe_stats_update(priv);
3879 + spin_unlock(&hwstats->stats_lock);
3880 + }
3881 + }
3882 +
3883 + do {
3884 + start = u64_stats_fetch_begin_bh(&hwstats->syncp);
3885 + storage->rx_packets = hwstats->rx_packets;
3886 + storage->tx_packets = hwstats->tx_packets;
3887 + storage->rx_bytes = hwstats->rx_bytes;
3888 + storage->tx_bytes = hwstats->tx_bytes;
3889 + storage->collisions = hwstats->tx_collisions;
3890 + storage->rx_length_errors = hwstats->rx_short_errors +
3891 + hwstats->rx_long_errors;
3892 + storage->rx_over_errors = hwstats->rx_overflow;
3893 + storage->rx_crc_errors = hwstats->rx_fcs_errors;
3894 + storage->rx_errors = hwstats->rx_checksum_errors;
3895 + storage->tx_aborted_errors = hwstats->tx_skip;
3896 + } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
3897 +
3898 + storage->tx_errors = priv->netdev->stats.tx_errors;
3899 + storage->rx_dropped = priv->netdev->stats.rx_dropped;
3900 + storage->tx_dropped = priv->netdev->stats.tx_dropped;
3901 +
3902 + return storage;
3903 +}
3904 +
3905 +static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
3906 + int idx)
3907 +{
3908 + struct fe_priv *priv = netdev_priv(dev);
3909 + struct skb_frag_struct *frag;
3910 + struct fe_tx_dma *txd;
3911 + dma_addr_t mapped_addr;
3912 + unsigned int nr_frags;
3913 + u32 def_txd4, txd2;
3914 + int i, j, unmap_idx, tx_num;
3915 +
3916 + txd = &priv->tx_dma[idx];
3917 + nr_frags = skb_shinfo(skb)->nr_frags;
3918 + tx_num = 1 + (nr_frags >> 1);
3919 +
3920 + /* init tx descriptor */
3921 + if (priv->soc->tx_dma)
3922 + priv->soc->tx_dma(priv, idx, skb);
3923 + else
3924 + txd->txd4 = TX_DMA_DESP4_DEF;
3925 + def_txd4 = txd->txd4;
3926 +
3927 + /* use dma_unmap_single to free it */
3928 + txd->txd4 |= priv->soc->tx_udf_bit;
3929 +
3930 + /* TX Checksum offload */
3931 + if (skb->ip_summed == CHECKSUM_PARTIAL)
3932 + txd->txd4 |= TX_DMA_CHKSUM;
3933 +
3934 + /* VLAN header offload */
3935 + if (vlan_tx_tag_present(skb)) {
3936 + txd->txd4 |= TX_DMA_INS_VLAN |
3937 + ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
3938 + (vlan_tx_tag_get(skb) & 0xF);
3939 + }
3940 +
3941 + /* TSO: fill MSS info in tcp checksum field */
3942 + if (skb_is_gso(skb)) {
3943 + if (skb_cow_head(skb, 0)) {
3944 + netif_warn(priv, tx_err, dev,
3945 + "GSO expand head fail.\n");
3946 + goto err_out;
3947 + }
3948 + if (skb_shinfo(skb)->gso_type &
3949 + (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3950 + txd->txd4 |= TX_DMA_TSO;
3951 + tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
3952 + }
3953 + }
3954 +
3955 + mapped_addr = dma_map_single(&dev->dev, skb->data,
3956 + skb_headlen(skb), DMA_TO_DEVICE);
3957 + if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
3958 + goto err_out;
3959 + txd->txd1 = mapped_addr;
3960 + txd2 = TX_DMA_PLEN0(skb_headlen(skb));
3961 +
3962 + /* TX SG offload */
3963 + j = idx;
3964 + for (i = 0; i < nr_frags; i++) {
3965 +
3966 + frag = &skb_shinfo(skb)->frags[i];
3967 + mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
3968 + skb_frag_size(frag), DMA_TO_DEVICE);
3969 + if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
3970 + goto err_dma;
3971 +
3972 + if (i & 0x1) {
3973 + j = NEXT_TX_DESP_IDX(j);
3974 + txd = &priv->tx_dma[j];
3975 + txd->txd1 = mapped_addr;
3976 + txd2 = TX_DMA_PLEN0(frag->size);
3977 + txd->txd4 = def_txd4;
3978 + } else {
3979 + txd->txd3 = mapped_addr;
3980 + txd2 |= TX_DMA_PLEN1(frag->size);
3981 + if (i != (nr_frags -1))
3982 + txd->txd2 = txd2;
3983 + priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
3984 + }
3985 + }
3986 +
3987 + /* set last segment */
3988 + if (nr_frags & 0x1)
3989 + txd->txd2 = (txd2 | TX_DMA_LS1);
3990 + else
3991 + txd->txd2 = (txd2 | TX_DMA_LS0);
3992 +
3993 + /* store skb to cleanup */
3994 + priv->tx_skb[j] = skb;
3995 +
3996 + wmb();
3997 + j = NEXT_TX_DESP_IDX(j);
3998 + fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
3999 +
4000 + return 0;
4001 +
4002 +err_dma:
4003 + /* unmap dma */
4004 + txd = &priv->tx_dma[idx];
4005 + txd_unmap_single(&dev->dev, txd);
4006 +
4007 + j = idx;
4008 + unmap_idx = i;
4009 + for (i = 0; i < unmap_idx; i++) {
4010 + if (i & 0x1) {
4011 + j = NEXT_TX_DESP_IDX(j);
4012 + txd = &priv->tx_dma[j];
4013 + txd_unmap_page0(&dev->dev, txd);
4014 + } else {
4015 + txd_unmap_page1(&dev->dev, txd);
4016 + }
4017 + }
4018 +
4019 +err_out:
4020 + /* reinit descriptors and skb */
4021 + j = idx;
4022 + for (i = 0; i < tx_num; i++) {
4023 + priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
4024 + priv->tx_skb[j] = NULL;
4025 + j = NEXT_TX_DESP_IDX(j);
4026 + }
4027 + wmb();
4028 +
4029 + return -1;
4030 +}
4031 +
4032 +static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
4033 + unsigned int len;
4034 + int ret;
4035 +
4036 + ret = 0;
4037 + if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
4038 + if ((priv->flags & FE_FLAG_PADDING_64B) &&
4039 + !(priv->flags & FE_FLAG_PADDING_BUG))
4040 + return ret;
4041 +
4042 + if (vlan_tx_tag_present(skb))
4043 + len = ETH_ZLEN;
4044 + else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4045 + len = VLAN_ETH_ZLEN;
4046 + else if(!(priv->flags & FE_FLAG_PADDING_64B))
4047 + len = ETH_ZLEN;
4048 + else
4049 + return ret;
4050 +
4051 + if (skb->len < len) {
4052 + if ((ret = skb_pad(skb, len - skb->len)) < 0)
4053 + return ret;
4054 + skb->len = len;
4055 + skb_set_tail_pointer(skb, len);
4056 + }
4057 + }
4058 +
4059 + return ret;
4060 +}
4061 +
4062 +static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
4063 +{
4064 + return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
4065 + (NUM_DMA_DESC - 1)));
4066 +}
4067 +
4068 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
4069 +{
4070 + struct fe_priv *priv = netdev_priv(dev);
4071 + struct net_device_stats *stats = &dev->stats;
4072 + u32 tx;
4073 + int tx_num;
4074 +
4075 + if (fe_skb_padto(skb, priv)) {
4076 + netif_warn(priv, tx_err, dev, "tx padding failed!\n");
4077 + return NETDEV_TX_OK;
4078 + }
4079 +
4080 + spin_lock(&priv->page_lock);
4081 + tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
4082 + tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
4083 + if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
4084 + {
4085 + netif_stop_queue(dev);
4086 + spin_unlock(&priv->page_lock);
4087 + netif_err(priv, tx_queued,dev,
4088 + "Tx Ring full when queue awake!\n");
4089 + return NETDEV_TX_BUSY;
4090 + }
4091 +
4092 + if (fe_tx_map_dma(skb, dev, tx) < 0) {
4093 + kfree_skb(skb);
4094 +
4095 + stats->tx_dropped++;
4096 + } else {
4097 + netdev_sent_queue(dev, skb->len);
4098 + skb_tx_timestamp(skb);
4099 +
4100 + stats->tx_packets++;
4101 + stats->tx_bytes += skb->len;
4102 + }
4103 +
4104 + spin_unlock(&priv->page_lock);
4105 +
4106 + return NETDEV_TX_OK;
4107 +}
4108 +
4109 +static inline void fe_rx_vlan(struct sk_buff *skb)
4110 +{
4111 + struct ethhdr *ehdr;
4112 + u16 vlanid;
4113 +
4114 + if (!__vlan_get_tag(skb, &vlanid)) {
4115 + /* pop the vlan tag */
4116 + ehdr = (struct ethhdr *)skb->data;
4117 + memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
4118 + skb_pull(skb, VLAN_HLEN);
4119 + __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
4120 + }
4121 +}
4122 +
4123 +static int fe_poll_rx(struct napi_struct *napi, int budget,
4124 + struct fe_priv *priv)
4125 +{
4126 + struct net_device *netdev = priv->netdev;
4127 + struct net_device_stats *stats = &netdev->stats;
4128 + struct fe_soc_data *soc = priv->soc;
4129 + u32 checksum_bit;
4130 + int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
4131 + struct sk_buff *skb;
4132 + u8 *data, *new_data;
4133 + struct fe_rx_dma *rxd;
4134 + int done = 0;
4135 + bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
4136 +
4137 + if (netdev->features & NETIF_F_RXCSUM)
4138 + checksum_bit = soc->checksum_bit;
4139 + else
4140 + checksum_bit = 0;
4141 +
4142 + while (done < budget) {
4143 + unsigned int pktlen;
4144 + dma_addr_t dma_addr;
4145 + idx = NEXT_RX_DESP_IDX(idx);
4146 + rxd = &priv->rx_dma[idx];
4147 + data = priv->rx_data[idx];
4148 +
4149 + if (!(rxd->rxd2 & RX_DMA_DONE))
4150 + break;
4151 +
4152 + /* alloc new buffer */
4153 + new_data = netdev_alloc_frag(priv->frag_size);
4154 + if (unlikely(!new_data)) {
4155 + stats->rx_dropped++;
4156 + goto release_desc;
4157 + }
4158 + dma_addr = dma_map_single(&netdev->dev,
4159 + new_data + FE_RX_OFFSET,
4160 + priv->rx_buf_size,
4161 + DMA_FROM_DEVICE);
4162 + if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
4163 + put_page(virt_to_head_page(new_data));
4164 + goto release_desc;
4165 + }
4166 +
4167 + /* receive data */
4168 + skb = build_skb(data, priv->frag_size);
4169 + if (unlikely(!skb)) {
4170 + put_page(virt_to_head_page(new_data));
4171 + goto release_desc;
4172 + }
4173 + skb_reserve(skb, FE_RX_OFFSET);
4174 +
4175 + dma_unmap_single(&netdev->dev, rxd->rxd1,
4176 + priv->rx_buf_size, DMA_FROM_DEVICE);
4177 + pktlen = RX_DMA_PLEN0(rxd->rxd2);
4178 + skb_put(skb, pktlen);
4179 + skb->dev = netdev;
4180 + if (rxd->rxd4 & checksum_bit) {
4181 + skb->ip_summed = CHECKSUM_UNNECESSARY;
4182 + } else {
4183 + skb_checksum_none_assert(skb);
4184 + }
4185 + if (rx_vlan)
4186 + fe_rx_vlan(skb);
4187 + skb->protocol = eth_type_trans(skb, netdev);
4188 +
4189 + stats->rx_packets++;
4190 + stats->rx_bytes += pktlen;
4191 +
4192 + napi_gro_receive(napi, skb);
4193 +
4194 + priv->rx_data[idx] = new_data;
4195 + rxd->rxd1 = (unsigned int) dma_addr;
4196 +
4197 +release_desc:
4198 + if (soc->rx_dma)
4199 + soc->rx_dma(priv, idx, priv->rx_buf_size);
4200 + else
4201 + rxd->rxd2 = RX_DMA_LSO;
4202 +
4203 + wmb();
4204 + fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
4205 + done++;
4206 + }
4207 +
4208 + return done;
4209 +}
4210 +
4211 +static int fe_poll_tx(struct fe_priv *priv, int budget)
4212 +{
4213 + struct net_device *netdev = priv->netdev;
4214 + struct device *dev = &netdev->dev;
4215 + unsigned int bytes_compl = 0;
4216 + struct sk_buff *skb;
4217 + struct fe_tx_dma *txd;
4218 + int done = 0, idx;
4219 + u32 udf_bit = priv->soc->tx_udf_bit;
4220 +
4221 + idx = priv->tx_free_idx;
4222 + while (done < budget) {
4223 + txd = &priv->tx_dma[idx];
4224 + skb = priv->tx_skb[idx];
4225 +
4226 + if (!(txd->txd2 & TX_DMA_DONE) || !skb)
4227 + break;
4228 +
4229 + txd_unmap_page1(dev, txd);
4230 +
4231 + if (txd->txd4 & udf_bit)
4232 + txd_unmap_single(dev, txd);
4233 + else
4234 + txd_unmap_page0(dev, txd);
4235 +
4236 + if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
4237 + bytes_compl += skb->len;
4238 + dev_kfree_skb_any(skb);
4239 + done++;
4240 + }
4241 + priv->tx_skb[idx] = NULL;
4242 + idx = NEXT_TX_DESP_IDX(idx);
4243 + }
4244 + priv->tx_free_idx = idx;
4245 +
4246 + if (!done)
4247 + return 0;
4248 +
4249 + netdev_completed_queue(netdev, done, bytes_compl);
4250 + if (unlikely(netif_queue_stopped(netdev) &&
4251 + netif_carrier_ok(netdev))) {
4252 + netif_wake_queue(netdev);
4253 + }
4254 +
4255 + return done;
4256 +}
4257 +
4258 +static int fe_poll(struct napi_struct *napi, int budget)
4259 +{
4260 + struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
4261 + struct fe_hw_stats *hwstat = priv->hw_stats;
4262 + int tx_done, rx_done;
4263 + u32 status, mask;
4264 + u32 tx_intr, rx_intr;
4265 +
4266 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
4267 + tx_intr = priv->soc->tx_dly_int;
4268 + rx_intr = priv->soc->rx_dly_int;
4269 + tx_done = rx_done = 0;
4270 +
4271 +poll_again:
4272 + if (status & tx_intr) {
4273 + tx_done += fe_poll_tx(priv, budget - tx_done);
4274 + if (tx_done < budget) {
4275 + fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
4276 + }
4277 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
4278 + }
4279 +
4280 + if (status & rx_intr) {
4281 + rx_done += fe_poll_rx(napi, budget - rx_done, priv);
4282 + if (rx_done < budget) {
4283 + fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
4284 + }
4285 + }
4286 +
4287 + if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
4288 + if (spin_trylock(&hwstat->stats_lock)) {
4289 + fe_stats_update(priv);
4290 + spin_unlock(&hwstat->stats_lock);
4291 + }
4292 + fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
4293 + }
4294 +
4295 + if (unlikely(netif_msg_intr(priv))) {
4296 + mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
4297 + netdev_info(priv->netdev,
4298 + "done tx %d, rx %d, intr 0x%x/0x%x\n",
4299 + tx_done, rx_done, status, mask);
4300 + }
4301 +
4302 + if ((tx_done < budget) && (rx_done < budget)) {
4303 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
4304 + if (status & (tx_intr | rx_intr )) {
4305 + goto poll_again;
4306 + }
4307 + napi_complete(napi);
4308 + fe_int_enable(tx_intr | rx_intr);
4309 + }
4310 +
4311 + return rx_done;
4312 +}
4313 +
4314 +static void fe_tx_timeout(struct net_device *dev)
4315 +{
4316 + struct fe_priv *priv = netdev_priv(dev);
4317 +
4318 + priv->netdev->stats.tx_errors++;
4319 + netif_err(priv, tx_err, dev,
4320 + "transmit timed out, waking up the queue\n");
4321 + netif_info(priv, drv, dev, ": dma_cfg:%08x, free_idx:%d, " \
4322 + "dma_ctx_idx=%u, dma_crx_idx=%u\n",
4323 + fe_reg_r32(FE_REG_PDMA_GLO_CFG), priv->tx_free_idx,
4324 + fe_reg_r32(FE_REG_TX_CTX_IDX0),
4325 + fe_reg_r32(FE_REG_RX_CALC_IDX0));
4326 + netif_wake_queue(dev);
4327 +}
4328 +
4329 +static irqreturn_t fe_handle_irq(int irq, void *dev)
4330 +{
4331 + struct fe_priv *priv = netdev_priv(dev);
4332 + u32 status, dly_int;
4333 +
4334 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
4335 +
4336 + if (unlikely(!status))
4337 + return IRQ_NONE;
4338 +
4339 + dly_int = (priv->soc->rx_dly_int | priv->soc->tx_dly_int);
4340 + if (likely(status & dly_int)) {
4341 + fe_int_disable(dly_int);
4342 + napi_schedule(&priv->rx_napi);
4343 + } else {
4344 + fe_reg_w32(status, FE_REG_FE_INT_STATUS);
4345 + }
4346 +
4347 + return IRQ_HANDLED;
4348 +}
4349 +
4350 +int fe_set_clock_cycle(struct fe_priv *priv)
4351 +{
4352 + unsigned long sysclk = priv->sysclk;
4353 +
4354 + if (!sysclk) {
4355 + return -EINVAL;
4356 + }
4357 +
4358 + sysclk /= FE_US_CYC_CNT_DIVISOR;
4359 + sysclk <<= FE_US_CYC_CNT_SHIFT;
4360 +
4361 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
4362 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
4363 + sysclk,
4364 + FE_FE_GLO_CFG);
4365 + return 0;
4366 +}
4367 +
4368 +void fe_fwd_config(struct fe_priv *priv)
4369 +{
4370 + u32 fwd_cfg;
4371 +
4372 + fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
4373 +
4374 + /* disable jumbo frame */
4375 + if (priv->flags & FE_FLAG_JUMBO_FRAME)
4376 + fwd_cfg &= ~FE_GDM1_JMB_EN;
4377 +
4378 + /* set unicast/multicast/broadcast frame to cpu */
4379 + fwd_cfg &= ~0xffff;
4380 +
4381 + fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
4382 +}
4383 +
4384 +static void fe_rxcsum_config(bool enable)
4385 +{
4386 + if (enable)
4387 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
4388 + FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
4389 + FE_GDMA1_FWD_CFG);
4390 + else
4391 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
4392 + FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
4393 + FE_GDMA1_FWD_CFG);
4394 +}
4395 +
4396 +static void fe_txcsum_config(bool enable)
4397 +{
4398 + if (enable)
4399 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
4400 + FE_TCS_GEN_EN | FE_UCS_GEN_EN),
4401 + FE_CDMA_CSG_CFG);
4402 + else
4403 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
4404 + FE_TCS_GEN_EN | FE_UCS_GEN_EN),
4405 + FE_CDMA_CSG_CFG);
4406 +}
4407 +
4408 +void fe_csum_config(struct fe_priv *priv)
4409 +{
4410 + struct net_device *dev = priv_netdev(priv);
4411 +
4412 + fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
4413 + fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
4414 +}
4415 +
4416 +static int fe_hw_init(struct net_device *dev)
4417 +{
4418 + struct fe_priv *priv = netdev_priv(dev);
4419 + int i, err;
4420 +
4421 + err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
4422 + dev_name(priv->device), dev);
4423 + if (err)
4424 + return err;
4425 +
4426 + if (priv->soc->set_mac)
4427 + priv->soc->set_mac(priv, dev->dev_addr);
4428 + else
4429 + fe_hw_set_macaddr(priv, dev->dev_addr);
4430 +
4431 + fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
4432 +
4433 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4434 +
4435 + /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
4436 + if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
4437 + for (i = 0; i < 16; i += 2)
4438 + fe_w32(((i + 1) << 16) + i,
4439 + fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
4440 + (i * 2));
4441 +
4442 + BUG_ON(!priv->soc->fwd_config);
4443 + if (priv->soc->fwd_config(priv))
4444 + netdev_err(dev, "unable to get clock\n");
4445 +
4446 + fe_w32(1, FE_FE_RST_GL);
4447 + fe_w32(0, FE_FE_RST_GL);
4448 +
4449 + return 0;
4450 +}
4451 +
4452 +static int fe_open(struct net_device *dev)
4453 +{
4454 + struct fe_priv *priv = netdev_priv(dev);
4455 + unsigned long flags;
4456 + u32 val;
4457 + int err;
4458 +
4459 + err = fe_init_dma(priv);
4460 + if (err)
4461 + goto err_out;
4462 +
4463 + spin_lock_irqsave(&priv->page_lock, flags);
4464 + napi_enable(&priv->rx_napi);
4465 +
4466 + val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
4467 + val |= priv->soc->pdma_glo_cfg;
4468 + fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
4469 +
4470 + spin_unlock_irqrestore(&priv->page_lock, flags);
4471 +
4472 + if (priv->phy)
4473 + priv->phy->start(priv);
4474 +
4475 + if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
4476 + netif_carrier_on(dev);
4477 +
4478 + netif_start_queue(dev);
4479 + fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4480 +
4481 + return 0;
4482 +
4483 +err_out:
4484 + fe_free_dma(priv);
4485 + return err;
4486 +}
4487 +
4488 +static int fe_stop(struct net_device *dev)
4489 +{
4490 + struct fe_priv *priv = netdev_priv(dev);
4491 + unsigned long flags;
4492 + int i;
4493 +
4494 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4495 +
4496 + netif_tx_disable(dev);
4497 +
4498 + if (priv->phy)
4499 + priv->phy->stop(priv);
4500 +
4501 + spin_lock_irqsave(&priv->page_lock, flags);
4502 + napi_disable(&priv->rx_napi);
4503 +
4504 + fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
4505 + ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
4506 + FE_REG_PDMA_GLO_CFG);
4507 + spin_unlock_irqrestore(&priv->page_lock, flags);
4508 +
4509 + /* wait dma stop */
4510 + for (i = 0; i < 10; i++) {
4511 + if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
4512 + (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
4513 + msleep(10);
4514 + continue;
4515 + }
4516 + break;
4517 + }
4518 +
4519 + fe_free_dma(priv);
4520 +
4521 + return 0;
4522 +}
4523 +
4524 +static int __init fe_init(struct net_device *dev)
4525 +{
4526 + struct fe_priv *priv = netdev_priv(dev);
4527 + struct device_node *port;
4528 + int err;
4529 +
4530 + BUG_ON(!priv->soc->reset_fe);
4531 + priv->soc->reset_fe();
4532 +
4533 + if (priv->soc->switch_init)
4534 + priv->soc->switch_init(priv);
4535 +
4536 + memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
4537 + of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
4538 +
4539 + err = fe_mdio_init(priv);
4540 + if (err)
4541 + return err;
4542 +
4543 + if (priv->soc->port_init)
4544 + for_each_child_of_node(priv->device->of_node, port)
4545 + if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
4546 + priv->soc->port_init(priv, port);
4547 +
4548 + if (priv->phy) {
4549 + err = priv->phy->connect(priv);
4550 + if (err)
4551 + goto err_phy_disconnect;
4552 + }
4553 +
4554 + err = fe_hw_init(dev);
4555 + if (err)
4556 + goto err_phy_disconnect;
4557 +
4558 + if (priv->soc->switch_config)
4559 + priv->soc->switch_config(priv);
4560 +
4561 + return 0;
4562 +
4563 +err_phy_disconnect:
4564 + if (priv->phy)
4565 + priv->phy->disconnect(priv);
4566 + fe_mdio_cleanup(priv);
4567 +
4568 + return err;
4569 +}
4570 +
4571 +static void fe_uninit(struct net_device *dev)
4572 +{
4573 + struct fe_priv *priv = netdev_priv(dev);
4574 +
4575 + if (priv->phy)
4576 + priv->phy->disconnect(priv);
4577 + fe_mdio_cleanup(priv);
4578 +
4579 + fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
4580 + free_irq(dev->irq, dev);
4581 +}
4582 +
4583 +static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4584 +{
4585 + struct fe_priv *priv = netdev_priv(dev);
4586 +
4587 + if (!priv->phy_dev)
4588 + return -ENODEV;
4589 +
4590 + switch (cmd) {
4591 + case SIOCETHTOOL:
4592 + return phy_ethtool_ioctl(priv->phy_dev,
4593 + (void *) ifr->ifr_data);
4594 + case SIOCGMIIPHY:
4595 + case SIOCGMIIREG:
4596 + case SIOCSMIIREG:
4597 + return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
4598 + default:
4599 + break;
4600 + }
4601 +
4602 + return -EOPNOTSUPP;
4603 +}
4604 +
4605 +static int fe_change_mtu(struct net_device *dev, int new_mtu)
4606 +{
4607 + struct fe_priv *priv = netdev_priv(dev);
4608 + int frag_size, old_mtu;
4609 + u32 fwd_cfg;
4610 +
4611 + if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
4612 + return eth_change_mtu(dev, new_mtu);
4613 +
4614 + frag_size = fe_max_frag_size(new_mtu);
4615 + if (new_mtu < 68 || frag_size > PAGE_SIZE)
4616 + return -EINVAL;
4617 +
4618 + old_mtu = dev->mtu;
4619 + dev->mtu = new_mtu;
4620 +
4621 + /* return early if the buffer sizes will not change */
4622 + if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
4623 + return 0;
4624 + if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
4625 + return 0;
4626 +
4627 + if (new_mtu <= ETH_DATA_LEN) {
4628 + priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
4629 + priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
4630 + } else {
4631 + priv->frag_size = PAGE_SIZE;
4632 + priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
4633 + }
4634 +
4635 + if (!netif_running(dev))
4636 + return 0;
4637 +
4638 + fe_stop(dev);
4639 + fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
4640 + if (new_mtu <= ETH_DATA_LEN)
4641 + fwd_cfg &= ~FE_GDM1_JMB_EN;
4642 + else {
4643 + fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
4644 + fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
4645 + FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
4646 + }
4647 + fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
4648 +
4649 + return fe_open(dev);
4650 +}
4651 +
4652 +static const struct net_device_ops fe_netdev_ops = {
4653 + .ndo_init = fe_init,
4654 + .ndo_uninit = fe_uninit,
4655 + .ndo_open = fe_open,
4656 + .ndo_stop = fe_stop,
4657 + .ndo_start_xmit = fe_start_xmit,
4658 + .ndo_set_mac_address = fe_set_mac_address,
4659 + .ndo_validate_addr = eth_validate_addr,
4660 + .ndo_do_ioctl = fe_do_ioctl,
4661 + .ndo_change_mtu = fe_change_mtu,
4662 + .ndo_tx_timeout = fe_tx_timeout,
4663 + .ndo_get_stats64 = fe_get_stats64,
4664 +};
4665 +
4666 +static int fe_probe(struct platform_device *pdev)
4667 +{
4668 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4669 + const struct of_device_id *match;
4670 + struct fe_soc_data *soc;
4671 + struct net_device *netdev;
4672 + struct fe_priv *priv;
4673 + struct clk *sysclk;
4674 + int err;
4675 +
4676 + device_reset(&pdev->dev);
4677 +
4678 + match = of_match_device(of_fe_match, &pdev->dev);
4679 + soc = (struct fe_soc_data *) match->data;
4680 +
4681 + if (soc->reg_table)
4682 + fe_reg_table = soc->reg_table;
4683 + else
4684 + soc->reg_table = fe_reg_table;
4685 +
4686 + fe_base = devm_request_and_ioremap(&pdev->dev, res);
4687 + if (!fe_base) {
4688 + err = -EADDRNOTAVAIL;
4689 + goto err_out;
4690 + }
4691 +
4692 + netdev = alloc_etherdev(sizeof(*priv));
4693 + if (!netdev) {
4694 + dev_err(&pdev->dev, "alloc_etherdev failed\n");
4695 + err = -ENOMEM;
4696 + goto err_iounmap;
4697 + }
4698 +
4699 + SET_NETDEV_DEV(netdev, &pdev->dev);
4700 + netdev->netdev_ops = &fe_netdev_ops;
4701 + netdev->base_addr = (unsigned long) fe_base;
4702 + netdev->watchdog_timeo = TX_TIMEOUT;
4703 +
4704 + netdev->irq = platform_get_irq(pdev, 0);
4705 + if (netdev->irq < 0) {
4706 + dev_err(&pdev->dev, "no IRQ resource found\n");
4707 + err = -ENXIO;
4708 + goto err_free_dev;
4709 + }
4710 +
4711 + if (soc->init_data)
4712 + soc->init_data(soc, netdev);
4713 + /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
4714 + netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4715 + netdev->vlan_features = netdev->hw_features &
4716 + ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
4717 + netdev->features |= netdev->hw_features;
4718 +
4719 + priv = netdev_priv(netdev);
4720 + spin_lock_init(&priv->page_lock);
4721 + if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
4722 + priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
4723 + if (!priv->hw_stats) {
4724 + err = -ENOMEM;
4725 + goto err_free_dev;
4726 + }
4727 + spin_lock_init(&priv->hw_stats->stats_lock);
4728 + }
4729 +
4730 + sysclk = devm_clk_get(&pdev->dev, NULL);
4731 + if (!IS_ERR(sysclk))
4732 + priv->sysclk = clk_get_rate(sysclk);
4733 +
4734 + priv->netdev = netdev;
4735 + priv->device = &pdev->dev;
4736 + priv->soc = soc;
4737 + priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
4738 + priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
4739 + priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
4740 + if (priv->frag_size > PAGE_SIZE) {
4741 + dev_err(&pdev->dev, "error frag size.\n");
4742 + err = -EINVAL;
4743 + goto err_free_dev;
4744 + }
4745 +
4746 + netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
4747 + fe_set_ethtool_ops(netdev);
4748 +
4749 + err = register_netdev(netdev);
4750 + if (err) {
4751 + dev_err(&pdev->dev, "error bringing up device\n");
4752 + goto err_free_dev;
4753 + }
4754 +
4755 + platform_set_drvdata(pdev, netdev);
4756 +
4757 + netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
4758 + netdev->base_addr, netdev->irq);
4759 +
4760 + return 0;
4761 +
4762 +err_free_dev:
4763 + free_netdev(netdev);
4764 +err_iounmap:
4765 + devm_iounmap(&pdev->dev, fe_base);
4766 +err_out:
4767 + return err;
4768 +}
4769 +
4770 +static int fe_remove(struct platform_device *pdev)
4771 +{
4772 + struct net_device *dev = platform_get_drvdata(pdev);
4773 + struct fe_priv *priv = netdev_priv(dev);
4774 +
4775 + netif_napi_del(&priv->rx_napi);
4776 + if (priv->hw_stats)
4777 + kfree(priv->hw_stats);
4778 +
4779 + unregister_netdev(dev);
4780 + free_netdev(dev);
4781 + platform_set_drvdata(pdev, NULL);
4782 +
4783 + return 0;
4784 +}
4785 +
4786 +static struct platform_driver fe_driver = {
4787 + .probe = fe_probe,
4788 + .remove = fe_remove,
4789 + .driver = {
4790 + .name = "ralink_soc_eth",
4791 + .owner = THIS_MODULE,
4792 + .of_match_table = of_fe_match,
4793 + },
4794 +};
4795 +
4796 +static int __init init_rtfe(void)
4797 +{
4798 + int ret;
4799 +
4800 + ret = rtesw_init();
4801 + if (ret)
4802 + return ret;
4803 +
4804 + ret = platform_driver_register(&fe_driver);
4805 + if (ret)
4806 + rtesw_exit();
4807 +
4808 + return ret;
4809 +}
4810 +
4811 +static void __exit exit_rtfe(void)
4812 +{
4813 + platform_driver_unregister(&fe_driver);
4814 + rtesw_exit();
4815 +}
4816 +
4817 +module_init(init_rtfe);
4818 +module_exit(exit_rtfe);
4819 +
4820 +MODULE_LICENSE("GPL");
4821 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4822 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4823 +MODULE_VERSION(FE_DRV_VERSION);
4824 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.h
4825 ===================================================================
4826 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4827 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.h 2014-10-29 20:25:55.433357519 +0100
4828 @@ -0,0 +1,448 @@
4829 +/*
4830 + * This program is free software; you can redistribute it and/or modify
4831 + * it under the terms of the GNU General Public License as published by
4832 + * the Free Software Foundation; version 2 of the License
4833 + *
4834 + * This program is distributed in the hope that it will be useful,
4835 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4836 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4837 + * GNU General Public License for more details.
4838 + *
4839 + * You should have received a copy of the GNU General Public License
4840 + * along with this program; if not, write to the Free Software
4841 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4842 + *
4843 + * based on Ralink SDK3.3
4844 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4845 + */
4846 +
4847 +#ifndef FE_ETH_H
4848 +#define FE_ETH_H
4849 +
4850 +#include <linux/mii.h>
4851 +#include <linux/interrupt.h>
4852 +#include <linux/netdevice.h>
4853 +#include <linux/dma-mapping.h>
4854 +#include <linux/phy.h>
4855 +#include <linux/ethtool.h>
4856 +
4857 +enum fe_reg {
4858 + FE_REG_PDMA_GLO_CFG = 0,
4859 + FE_REG_PDMA_RST_CFG,
4860 + FE_REG_DLY_INT_CFG,
4861 + FE_REG_TX_BASE_PTR0,
4862 + FE_REG_TX_MAX_CNT0,
4863 + FE_REG_TX_CTX_IDX0,
4864 + FE_REG_RX_BASE_PTR0,
4865 + FE_REG_RX_MAX_CNT0,
4866 + FE_REG_RX_CALC_IDX0,
4867 + FE_REG_FE_INT_ENABLE,
4868 + FE_REG_FE_INT_STATUS,
4869 + FE_REG_FE_DMA_VID_BASE,
4870 + FE_REG_FE_COUNTER_BASE,
4871 + FE_REG_COUNT
4872 +};
4873 +
4874 +#define FE_DRV_VERSION "0.1.0"
4875 +
4876 +/* power of 2 to let NEXT_TX_DESP_IDX work */
4877 +#define NUM_DMA_DESC (1 << 7)
4878 +#define MAX_DMA_DESC 0xfff
4879 +
4880 +#define FE_DELAY_EN_INT 0x80
4881 +#define FE_DELAY_MAX_INT 0x04
4882 +#define FE_DELAY_MAX_TOUT 0x04
4883 +#define FE_DELAY_TIME 20
4884 +#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4885 +#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4886 +#define FE_PSE_FQFC_CFG_INIT 0x80504000
4887 +#define FE_PSE_FQFC_CFG_256Q 0xff908000
4888 +
4889 +/* interrupt bits */
4890 +#define FE_CNT_PPE_AF BIT(31)
4891 +#define FE_CNT_GDM_AF BIT(29)
4892 +#define FE_PSE_P2_FC BIT(26)
4893 +#define FE_PSE_BUF_DROP BIT(24)
4894 +#define FE_GDM_OTHER_DROP BIT(23)
4895 +#define FE_PSE_P1_FC BIT(22)
4896 +#define FE_PSE_P0_FC BIT(21)
4897 +#define FE_PSE_FQ_EMPTY BIT(20)
4898 +#define FE_GE1_STA_CHG BIT(18)
4899 +#define FE_TX_COHERENT BIT(17)
4900 +#define FE_RX_COHERENT BIT(16)
4901 +#define FE_TX_DONE_INT3 BIT(11)
4902 +#define FE_TX_DONE_INT2 BIT(10)
4903 +#define FE_TX_DONE_INT1 BIT(9)
4904 +#define FE_TX_DONE_INT0 BIT(8)
4905 +#define FE_RX_DONE_INT0 BIT(2)
4906 +#define FE_TX_DLY_INT BIT(1)
4907 +#define FE_RX_DLY_INT BIT(0)
4908 +
4909 +#define RT5350_RX_DLY_INT BIT(30)
4910 +#define RT5350_TX_DLY_INT BIT(28)
4911 +
4912 +/* registers */
4913 +#define FE_FE_OFFSET 0x0000
4914 +#define FE_GDMA_OFFSET 0x0020
4915 +#define FE_PSE_OFFSET 0x0040
4916 +#define FE_GDMA2_OFFSET 0x0060
4917 +#define FE_CDMA_OFFSET 0x0080
4918 +#define FE_DMA_VID0 0x00a8
4919 +#define FE_PDMA_OFFSET 0x0100
4920 +#define FE_PPE_OFFSET 0x0200
4921 +#define FE_CMTABLE_OFFSET 0x0400
4922 +#define FE_POLICYTABLE_OFFSET 0x1000
4923 +
4924 +#define RT5350_PDMA_OFFSET 0x0800
4925 +#define RT5350_SDM_OFFSET 0x0c00
4926 +
4927 +#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
4928 +#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
4929 +#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
4930 +#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
4931 +#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
4932 +#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
4933 +#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
4934 +#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
4935 +
4936 +#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
4937 +#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
4938 +#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
4939 +#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
4940 +#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
4941 +
4942 +#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
4943 +#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
4944 +#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
4945 +#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
4946 +#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
4947 +
4948 +#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
4949 +#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
4950 +#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
4951 +#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
4952 +
4953 +#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
4954 +#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
4955 +
4956 +#define MT7620A_GDMA_OFFSET 0x0600
4957 +#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
4958 +#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
4959 +#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
4960 +#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
4961 +#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
4962 +
4963 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
4964 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
4965 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
4966 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
4967 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
4968 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
4969 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
4970 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
4971 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
4972 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
4973 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
4974 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
4975 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
4976 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
4977 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
4978 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
4979 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
4980 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
4981 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
4982 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
4983 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
4984 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
4985 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
4986 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
4987 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
4988 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
4989 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
4990 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
4991 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
4992 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
4993 +
4994 +#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
4995 +#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
4996 +#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
4997 +#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
4998 +#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
4999 +#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
5000 +#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
5001 +#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
5002 +#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
5003 +#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
5004 +#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
5005 +#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
5006 +#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
5007 +#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
5008 +#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
5009 +#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
5010 +#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
5011 +#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
5012 +#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
5013 +#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
5014 +#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
5015 +#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
5016 +#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
5017 +#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
5018 +#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
5019 +#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
5020 +#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
5021 +#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
5022 +
5023 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
5024 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
5025 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
5026 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
5027 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
5028 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
5029 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
5030 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
5031 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
5032 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
5033 +
5034 +#define RT5350_SDM_ICS_EN BIT(16)
5035 +#define RT5350_SDM_TCS_EN BIT(17)
5036 +#define RT5350_SDM_UCS_EN BIT(18)
5037 +
5038 +
5039 +/* MDIO_CFG register bits */
5040 +#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
5041 +#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
5042 +#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
5043 +#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
5044 +#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
5045 +#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
5046 +#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
5047 +#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
5048 +#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
5049 +#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
5050 +#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
5051 +#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
5052 +#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
5053 +#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
5054 +#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
5055 +#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
5056 +#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
5057 +#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
5058 +#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
5059 +#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
5060 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
5061 +#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
5062 +#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
5063 +#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
5064 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
5065 +
5066 +/* uni-cast port */
5067 +#define FE_GDM1_JMB_LEN_MASK 0xf
5068 +#define FE_GDM1_JMB_LEN_SHIFT 28
5069 +#define FE_GDM1_ICS_EN BIT(22)
5070 +#define FE_GDM1_TCS_EN BIT(21)
5071 +#define FE_GDM1_UCS_EN BIT(20)
5072 +#define FE_GDM1_JMB_EN BIT(19)
5073 +#define FE_GDM1_STRPCRC BIT(16)
5074 +#define FE_GDM1_UFRC_P_CPU (0 << 12)
5075 +#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
5076 +#define FE_GDM1_UFRC_P_PPE (6 << 12)
5077 +
5078 +/* checksums */
5079 +#define FE_ICS_GEN_EN BIT(2)
5080 +#define FE_UCS_GEN_EN BIT(1)
5081 +#define FE_TCS_GEN_EN BIT(0)
5082 +
5083 +/* dma ring */
5084 +#define FE_PST_DRX_IDX0 BIT(16)
5085 +#define FE_PST_DTX_IDX3 BIT(3)
5086 +#define FE_PST_DTX_IDX2 BIT(2)
5087 +#define FE_PST_DTX_IDX1 BIT(1)
5088 +#define FE_PST_DTX_IDX0 BIT(0)
5089 +
5090 +#define FE_TX_WB_DDONE BIT(6)
5091 +#define FE_RX_DMA_BUSY BIT(3)
5092 +#define FE_TX_DMA_BUSY BIT(1)
5093 +#define FE_RX_DMA_EN BIT(2)
5094 +#define FE_TX_DMA_EN BIT(0)
5095 +
5096 +#define FE_PDMA_SIZE_4DWORDS (0 << 4)
5097 +#define FE_PDMA_SIZE_8DWORDS (1 << 4)
5098 +#define FE_PDMA_SIZE_16DWORDS (2 << 4)
5099 +
5100 +#define FE_US_CYC_CNT_MASK 0xff
5101 +#define FE_US_CYC_CNT_SHIFT 0x8
5102 +#define FE_US_CYC_CNT_DIVISOR 1000000
5103 +
5104 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
5105 +#define RX_DMA_LSO BIT(30)
5106 +#define RX_DMA_DONE BIT(31)
5107 +#define RX_DMA_L4VALID BIT(30)
5108 +
5109 +struct fe_rx_dma {
5110 + unsigned int rxd1;
5111 + unsigned int rxd2;
5112 + unsigned int rxd3;
5113 + unsigned int rxd4;
5114 +} __packed __aligned(4);
5115 +
5116 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
5117 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
5118 +#define TX_DMA_PLEN1(_x) ((_x) & 0x3fff)
5119 +#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & 0x3fff)
5120 +#define TX_DMA_GET_PLEN1(_x) ((_x) & 0x3fff)
5121 +#define TX_DMA_LS1 BIT(14)
5122 +#define TX_DMA_LS0 BIT(30)
5123 +#define TX_DMA_DONE BIT(31)
5124 +
5125 +#define TX_DMA_INS_VLAN BIT(7)
5126 +#define TX_DMA_INS_PPPOE BIT(12)
5127 +#define TX_DMA_QN(_x) ((_x) << 16)
5128 +#define TX_DMA_PN(_x) ((_x) << 24)
5129 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
5130 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
5131 +#define TX_DMA_UDF BIT(20)
5132 +#define TX_DMA_CHKSUM (0x7 << 29)
5133 +#define TX_DMA_TSO BIT(28)
5134 +
5135 +/* frame engine counters */
5136 +#define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
5137 +#define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
5138 +#define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
5139 +
5140 +/* phy device flags */
5141 +#define FE_PHY_FLAG_PORT BIT(0)
5142 +#define FE_PHY_FLAG_ATTACH BIT(1)
5143 +
5144 +struct fe_tx_dma {
5145 + unsigned int txd1;
5146 + unsigned int txd2;
5147 + unsigned int txd3;
5148 + unsigned int txd4;
5149 +} __packed __aligned(4);
5150 +
5151 +struct fe_priv;
5152 +
5153 +struct fe_phy {
5154 + struct phy_device *phy[8];
5155 + struct device_node *phy_node[8];
5156 + const __be32 *phy_fixed[8];
5157 + int duplex[8];
5158 + int speed[8];
5159 + int tx_fc[8];
5160 + int rx_fc[8];
5161 + spinlock_t lock;
5162 +
5163 + int (*connect)(struct fe_priv *priv);
5164 + void (*disconnect)(struct fe_priv *priv);
5165 + void (*start)(struct fe_priv *priv);
5166 + void (*stop)(struct fe_priv *priv);
5167 +};
5168 +
5169 +struct fe_soc_data
5170 +{
5171 + unsigned char mac[6];
5172 + const u32 *reg_table;
5173 +
5174 + void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
5175 + void (*reset_fe)(void);
5176 + void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
5177 + int (*fwd_config)(struct fe_priv *priv);
5178 + void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
5179 + void (*rx_dma)(struct fe_priv *priv, int idx, int len);
5180 + int (*switch_init)(struct fe_priv *priv);
5181 + int (*switch_config)(struct fe_priv *priv);
5182 + void (*port_init)(struct fe_priv *priv, struct device_node *port);
5183 + int (*has_carrier)(struct fe_priv *priv);
5184 + int (*mdio_init)(struct fe_priv *priv);
5185 + void (*mdio_cleanup)(struct fe_priv *priv);
5186 + int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
5187 + int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
5188 + void (*mdio_adjust_link)(struct fe_priv *priv, int port);
5189 +
5190 + void *swpriv;
5191 + u32 pdma_glo_cfg;
5192 + u32 rx_dly_int;
5193 + u32 tx_dly_int;
5194 + u32 checksum_bit;
5195 + u32 tx_udf_bit;
5196 +};
5197 +
5198 +#define FE_FLAG_PADDING_64B BIT(0)
5199 +#define FE_FLAG_PADDING_BUG BIT(1)
5200 +#define FE_FLAG_JUMBO_FRAME BIT(2)
5201 +
5202 +#define FE_STAT_REG_DECLARE \
5203 + _FE(tx_bytes) \
5204 + _FE(tx_packets) \
5205 + _FE(tx_skip) \
5206 + _FE(tx_collisions) \
5207 + _FE(rx_bytes) \
5208 + _FE(rx_packets) \
5209 + _FE(rx_overflow) \
5210 + _FE(rx_fcs_errors) \
5211 + _FE(rx_short_errors) \
5212 + _FE(rx_long_errors) \
5213 + _FE(rx_checksum_errors) \
5214 + _FE(rx_flow_control_packets)
5215 +
5216 +struct fe_hw_stats
5217 +{
5218 + spinlock_t stats_lock;
5219 + struct u64_stats_sync syncp;
5220 +#define _FE(x) u64 x;
5221 +FE_STAT_REG_DECLARE
5222 +#undef _FE
5223 +};
5224 +
5225 +struct fe_priv
5226 +{
5227 + spinlock_t page_lock;
5228 +
5229 + struct fe_soc_data *soc;
5230 + struct net_device *netdev;
5231 + u32 msg_enable;
5232 + u32 flags;
5233 +
5234 + struct device *device;
5235 + unsigned long sysclk;
5236 +
5237 + u16 frag_size;
5238 + u16 rx_buf_size;
5239 + struct fe_rx_dma *rx_dma;
5240 + u8 **rx_data;
5241 + dma_addr_t rx_phys;
5242 + struct napi_struct rx_napi;
5243 +
5244 + struct fe_tx_dma *tx_dma;
5245 + struct sk_buff **tx_skb;
5246 + dma_addr_t tx_phys;
5247 + unsigned int tx_free_idx;
5248 +
5249 + struct fe_phy *phy;
5250 + struct mii_bus *mii_bus;
5251 + struct phy_device *phy_dev;
5252 + u32 phy_flags;
5253 +
5254 + int link[8];
5255 +
5256 + struct fe_hw_stats *hw_stats;
5257 +};
5258 +
5259 +extern const struct of_device_id of_fe_match[];
5260 +
5261 +void fe_w32(u32 val, unsigned reg);
5262 +u32 fe_r32(unsigned reg);
5263 +
5264 +int fe_set_clock_cycle(struct fe_priv *priv);
5265 +void fe_csum_config(struct fe_priv *priv);
5266 +void fe_stats_update(struct fe_priv *priv);
5267 +void fe_fwd_config(struct fe_priv *priv);
5268 +void fe_reg_w32(u32 val, enum fe_reg reg);
5269 +u32 fe_reg_r32(enum fe_reg reg);
5270 +
5271 +static inline void *priv_netdev(struct fe_priv *priv)
5272 +{
5273 + return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
5274 +}
5275 +
5276 +#endif /* FE_ETH_H */
5277 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_mt7620.c
5278 ===================================================================
5279 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5280 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_mt7620.c 2014-10-29 20:25:55.433357519 +0100
5281 @@ -0,0 +1,164 @@
5282 +/*
5283 + * This program is free software; you can redistribute it and/or modify
5284 + * it under the terms of the GNU General Public License as published by
5285 + * the Free Software Foundation; version 2 of the License
5286 + *
5287 + * This program is distributed in the hope that it will be useful,
5288 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5289 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5290 + * GNU General Public License for more details.
5291 + *
5292 + * You should have received a copy of the GNU General Public License
5293 + * along with this program; if not, write to the Free Software
5294 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5295 + *
5296 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5297 + */
5298 +
5299 +#include <linux/module.h>
5300 +#include <linux/platform_device.h>
5301 +#include <linux/if_vlan.h>
5302 +
5303 +#include <asm/mach-ralink/ralink_regs.h>
5304 +
5305 +#include <mt7620.h>
5306 +#include "ralink_soc_eth.h"
5307 +#include "gsw_mt7620a.h"
5308 +
5309 +#define MT7620A_CDMA_CSG_CFG 0x400
5310 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
5311 +#define MT7620A_DMA_2B_OFFSET BIT(31)
5312 +#define MT7620A_RESET_FE BIT(21)
5313 +#define MT7620A_RESET_ESW BIT(23)
5314 +#define MT7620_L4_VALID BIT(23)
5315 +
5316 +#define MT7620_TX_DMA_UDF BIT(15)
5317 +#define TX_DMA_FP_BMAP ((0xff) << 19)
5318 +
5319 +#define SYSC_REG_RESET_CTRL 0x34
5320 +
5321 +#define CDMA_ICS_EN BIT(2)
5322 +#define CDMA_UCS_EN BIT(1)
5323 +#define CDMA_TCS_EN BIT(0)
5324 +
5325 +#define GDMA_ICS_EN BIT(22)
5326 +#define GDMA_TCS_EN BIT(21)
5327 +#define GDMA_UCS_EN BIT(20)
5328 +
5329 +/* frame engine counters */
5330 +#define MT7620_REG_MIB_OFFSET 0x1000
5331 +#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
5332 +#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
5333 +#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
5334 +
5335 +static const u32 mt7620_reg_table[FE_REG_COUNT] = {
5336 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
5337 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
5338 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
5339 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
5340 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
5341 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
5342 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
5343 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
5344 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
5345 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
5346 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
5347 + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
5348 + [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
5349 +};
5350 +
5351 +static void mt7620_fe_reset(void)
5352 +{
5353 + rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
5354 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
5355 +}
5356 +
5357 +static void mt7620_rxcsum_config(bool enable)
5358 +{
5359 + if (enable)
5360 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
5361 + GDMA_TCS_EN | GDMA_UCS_EN),
5362 + MT7620A_GDMA1_FWD_CFG);
5363 + else
5364 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
5365 + GDMA_TCS_EN | GDMA_UCS_EN),
5366 + MT7620A_GDMA1_FWD_CFG);
5367 +}
5368 +
5369 +static void mt7620_txcsum_config(bool enable)
5370 +{
5371 + if (enable)
5372 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
5373 + CDMA_UCS_EN | CDMA_TCS_EN),
5374 + MT7620A_CDMA_CSG_CFG);
5375 + else
5376 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
5377 + CDMA_UCS_EN | CDMA_TCS_EN),
5378 + MT7620A_CDMA_CSG_CFG);
5379 +}
5380 +
5381 +static int mt7620_fwd_config(struct fe_priv *priv)
5382 +{
5383 + struct net_device *dev = priv_netdev(priv);
5384 +
5385 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
5386 +
5387 + mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
5388 + mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
5389 +
5390 + return 0;
5391 +}
5392 +
5393 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
5394 +{
5395 + priv->tx_dma[idx].txd4 = 0;
5396 +}
5397 +
5398 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
5399 +{
5400 + priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
5401 +}
5402 +
5403 +static void mt7620_init_data(struct fe_soc_data *data,
5404 + struct net_device *netdev)
5405 +{
5406 + struct fe_priv *priv = netdev_priv(netdev);
5407 +
5408 + priv->flags = FE_FLAG_PADDING_64B;
5409 + netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5410 + NETIF_F_HW_VLAN_CTAG_TX;
5411 +
5412 + if (mt7620_get_eco() >= 5)
5413 + netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
5414 + NETIF_F_IPV6_CSUM;
5415 +}
5416 +
5417 +static struct fe_soc_data mt7620_data = {
5418 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5419 + .init_data = mt7620_init_data,
5420 + .reset_fe = mt7620_fe_reset,
5421 + .set_mac = mt7620_set_mac,
5422 + .fwd_config = mt7620_fwd_config,
5423 + .tx_dma = mt7620_tx_dma,
5424 + .rx_dma = mt7620_rx_dma,
5425 + .switch_init = mt7620_gsw_probe,
5426 + .switch_config = mt7620_gsw_config,
5427 + .port_init = mt7620_port_init,
5428 + .reg_table = mt7620_reg_table,
5429 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
5430 + .rx_dly_int = RT5350_RX_DLY_INT,
5431 + .tx_dly_int = RT5350_TX_DLY_INT,
5432 + .checksum_bit = MT7620_L4_VALID,
5433 + .tx_udf_bit = MT7620_TX_DMA_UDF,
5434 + .has_carrier = mt7620a_has_carrier,
5435 + .mdio_read = mt7620_mdio_read,
5436 + .mdio_write = mt7620_mdio_write,
5437 + .mdio_adjust_link = mt7620_mdio_link_adjust,
5438 +};
5439 +
5440 +const struct of_device_id of_fe_match[] = {
5441 + { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
5442 + {},
5443 +};
5444 +
5445 +MODULE_DEVICE_TABLE(of, of_fe_match);
5446 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_rt2880.c
5447 ===================================================================
5448 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5449 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_rt2880.c 2014-10-29 20:25:55.433357519 +0100
5450 @@ -0,0 +1,81 @@
5451 +/*
5452 + * This program is free software; you can redistribute it and/or modify
5453 + * it under the terms of the GNU General Public License as published by
5454 + * the Free Software Foundation; version 2 of the License
5455 + *
5456 + * This program is distributed in the hope that it will be useful,
5457 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5458 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5459 + * GNU General Public License for more details.
5460 + *
5461 + * You should have received a copy of the GNU General Public License
5462 + * along with this program; if not, write to the Free Software
5463 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5464 + *
5465 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5466 + */
5467 +
5468 +#include <linux/module.h>
5469 +
5470 +#include <asm/mach-ralink/ralink_regs.h>
5471 +
5472 +#include "ralink_soc_eth.h"
5473 +#include "mdio_rt2880.h"
5474 +
5475 +#define SYSC_REG_RESET_CTRL 0x034
5476 +#define RT2880_RESET_FE BIT(18)
5477 +
5478 +static void rt2880_init_data(struct fe_soc_data *data,
5479 + struct net_device *netdev)
5480 +{
5481 + struct fe_priv *priv = netdev_priv(netdev);
5482 +
5483 + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
5484 + FE_FLAG_JUMBO_FRAME;
5485 + netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
5486 + /* maybe have hardware bug. */
5487 + //netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
5488 +}
5489 +
5490 +void rt2880_fe_reset(void)
5491 +{
5492 + rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
5493 +}
5494 +
5495 +static int rt2880_fwd_config(struct fe_priv *priv)
5496 +{
5497 + int ret;
5498 +
5499 + ret = fe_set_clock_cycle(priv);
5500 + if (ret)
5501 + return ret;
5502 +
5503 + fe_fwd_config(priv);
5504 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
5505 + fe_csum_config(priv);
5506 +
5507 + return ret;
5508 +}
5509 +
5510 +struct fe_soc_data rt2880_data = {
5511 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5512 + .init_data = rt2880_init_data,
5513 + .reset_fe = rt2880_fe_reset,
5514 + .fwd_config = rt2880_fwd_config,
5515 + .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
5516 + .checksum_bit = RX_DMA_L4VALID,
5517 + .tx_udf_bit = TX_DMA_UDF,
5518 + .rx_dly_int = FE_RX_DLY_INT,
5519 + .tx_dly_int = FE_TX_DLY_INT,
5520 + .mdio_read = rt2880_mdio_read,
5521 + .mdio_write = rt2880_mdio_write,
5522 + .mdio_adjust_link = rt2880_mdio_link_adjust,
5523 + .port_init = rt2880_port_init,
5524 +};
5525 +
5526 +const struct of_device_id of_fe_match[] = {
5527 + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
5528 + {},
5529 +};
5530 +
5531 +MODULE_DEVICE_TABLE(of, of_fe_match);
5532 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_rt305x.c
5533 ===================================================================
5534 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5535 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_rt305x.c 2014-10-29 20:25:55.433357519 +0100
5536 @@ -0,0 +1,161 @@
5537 +/*
5538 + * This program is free software; you can redistribute it and/or modify
5539 + * it under the terms of the GNU General Public License as published by
5540 + * the Free Software Foundation; version 2 of the License
5541 + *
5542 + * This program is distributed in the hope that it will be useful,
5543 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5544 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5545 + * GNU General Public License for more details.
5546 + *
5547 + * You should have received a copy of the GNU General Public License
5548 + * along with this program; if not, write to the Free Software
5549 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5550 + *
5551 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5552 + */
5553 +
5554 +#include <linux/module.h>
5555 +
5556 +#include <asm/mach-ralink/ralink_regs.h>
5557 +#include <asm/mach-ralink/rt305x.h>
5558 +
5559 +#include "ralink_soc_eth.h"
5560 +#include "mdio_rt2880.h"
5561 +
5562 +#define RT305X_RESET_FE BIT(21)
5563 +#define RT305X_RESET_ESW BIT(23)
5564 +#define SYSC_REG_RESET_CTRL 0x034
5565 +
5566 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
5567 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
5568 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
5569 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
5570 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
5571 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
5572 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
5573 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
5574 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
5575 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
5576 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
5577 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
5578 + [FE_REG_FE_DMA_VID_BASE] = 0,
5579 +};
5580 +
5581 +static void rt305x_init_data(struct fe_soc_data *data,
5582 + struct net_device *netdev)
5583 +{
5584 + struct fe_priv *priv = netdev_priv(netdev);
5585 +
5586 + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG;
5587 + netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
5588 + NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
5589 +}
5590 +
5591 +static int rt3050_fwd_config(struct fe_priv *priv)
5592 +{
5593 + int ret;
5594 +
5595 + if (soc_is_rt3052()) {
5596 + ret = fe_set_clock_cycle(priv);
5597 + if (ret)
5598 + return ret;
5599 + }
5600 +
5601 + fe_fwd_config(priv);
5602 + if (!soc_is_rt3352())
5603 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
5604 + fe_csum_config(priv);
5605 +
5606 + return 0;
5607 +}
5608 +
5609 +static void rt305x_fe_reset(void)
5610 +{
5611 + rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
5612 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
5613 +}
5614 +
5615 +static void rt5350_init_data(struct fe_soc_data *data,
5616 + struct net_device *netdev)
5617 +{
5618 + netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
5619 +}
5620 +
5621 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
5622 +{
5623 + unsigned long flags;
5624 +
5625 + spin_lock_irqsave(&priv->page_lock, flags);
5626 + fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
5627 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
5628 + RT5350_SDM_MAC_ADRL);
5629 + spin_unlock_irqrestore(&priv->page_lock, flags);
5630 +}
5631 +
5632 +static void rt5350_rxcsum_config(bool enable)
5633 +{
5634 + if (enable)
5635 + fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
5636 + RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
5637 + RT5350_SDM_CFG);
5638 + else
5639 + fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
5640 + RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
5641 + RT5350_SDM_CFG);
5642 +}
5643 +
5644 +static int rt5350_fwd_config(struct fe_priv *priv)
5645 +{
5646 + struct net_device *dev = priv_netdev(priv);
5647 +
5648 + rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
5649 +
5650 + return 0;
5651 +}
5652 +
5653 +static void rt5350_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
5654 +{
5655 + priv->tx_dma[idx].txd4 = 0;
5656 +}
5657 +
5658 +static void rt5350_fe_reset(void)
5659 +{
5660 + rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
5661 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
5662 +}
5663 +
5664 +static struct fe_soc_data rt3050_data = {
5665 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5666 + .init_data = rt305x_init_data,
5667 + .reset_fe = rt305x_fe_reset,
5668 + .fwd_config = rt3050_fwd_config,
5669 + .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
5670 + .checksum_bit = RX_DMA_L4VALID,
5671 + .tx_udf_bit = TX_DMA_UDF,
5672 + .rx_dly_int = FE_RX_DLY_INT,
5673 + .tx_dly_int = FE_TX_DLY_INT,
5674 +};
5675 +
5676 +static struct fe_soc_data rt5350_data = {
5677 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5678 + .init_data = rt5350_init_data,
5679 + .reg_table = rt5350_reg_table,
5680 + .reset_fe = rt5350_fe_reset,
5681 + .set_mac = rt5350_set_mac,
5682 + .fwd_config = rt5350_fwd_config,
5683 + .tx_dma = rt5350_tx_dma,
5684 + .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
5685 + .checksum_bit = RX_DMA_L4VALID,
5686 + .tx_udf_bit = TX_DMA_UDF,
5687 + .rx_dly_int = RT5350_RX_DLY_INT,
5688 + .tx_dly_int = RT5350_TX_DLY_INT,
5689 +};
5690 +
5691 +const struct of_device_id of_fe_match[] = {
5692 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
5693 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
5694 + {},
5695 +};
5696 +
5697 +MODULE_DEVICE_TABLE(of, of_fe_match);
5698 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_rt3883.c
5699 ===================================================================
5700 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5701 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_rt3883.c 2014-10-29 20:25:55.433357519 +0100
5702 @@ -0,0 +1,88 @@
5703 +/*
5704 + * This program is free software; you can redistribute it and/or modify
5705 + * it under the terms of the GNU General Public License as published by
5706 + * the Free Software Foundation; version 2 of the License
5707 + *
5708 + * This program is distributed in the hope that it will be useful,
5709 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5710 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5711 + * GNU General Public License for more details.
5712 + *
5713 + * You should have received a copy of the GNU General Public License
5714 + * along with this program; if not, write to the Free Software
5715 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5716 + *
5717 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5718 + */
5719 +
5720 +#include <linux/module.h>
5721 +
5722 +#include <asm/mach-ralink/ralink_regs.h>
5723 +
5724 +#include "ralink_soc_eth.h"
5725 +#include "mdio_rt2880.h"
5726 +
5727 +#define RT3883_SYSC_REG_RSTCTRL 0x34
5728 +#define RT3883_RSTCTRL_FE BIT(21)
5729 +
5730 +static void rt3883_fe_reset(void)
5731 +{
5732 + u32 t;
5733 +
5734 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
5735 + t |= RT3883_RSTCTRL_FE;
5736 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
5737 +
5738 + t &= ~RT3883_RSTCTRL_FE;
5739 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
5740 +}
5741 +
5742 +static int rt3883_fwd_config(struct fe_priv *priv)
5743 +{
5744 + int ret;
5745 +
5746 + ret = fe_set_clock_cycle(priv);
5747 + if (ret)
5748 + return ret;
5749 +
5750 + fe_fwd_config(priv);
5751 + fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);
5752 + fe_csum_config(priv);
5753 +
5754 + return ret;
5755 +}
5756 +
5757 +static void rt3883_init_data(struct fe_soc_data *data,
5758 + struct net_device *netdev)
5759 +{
5760 + struct fe_priv *priv = netdev_priv(netdev);
5761 +
5762 + priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
5763 + FE_FLAG_JUMBO_FRAME;
5764 + netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
5765 + NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
5766 +}
5767 +
5768 +static struct fe_soc_data rt3883_data = {
5769 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5770 + .init_data = rt3883_init_data,
5771 + .reset_fe = rt3883_fe_reset,
5772 + .fwd_config = rt3883_fwd_config,
5773 + .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
5774 + .rx_dly_int = FE_RX_DLY_INT,
5775 + .tx_dly_int = FE_TX_DLY_INT,
5776 + .checksum_bit = RX_DMA_L4VALID,
5777 + .tx_udf_bit = TX_DMA_UDF,
5778 + .mdio_read = rt2880_mdio_read,
5779 + .mdio_write = rt2880_mdio_write,
5780 + .mdio_adjust_link = rt2880_mdio_link_adjust,
5781 + .port_init = rt2880_port_init,
5782 +};
5783 +
5784 +const struct of_device_id of_fe_match[] = {
5785 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
5786 + {},
5787 +};
5788 +
5789 +MODULE_DEVICE_TABLE(of, of_fe_match);
5790 +
5791 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_ethtool.c
5792 ===================================================================
5793 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
5794 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_ethtool.c 2014-10-29 20:25:55.433357519 +0100
5795 @@ -0,0 +1,262 @@
5796 +/*
5797 + * This program is free software; you can redistribute it and/or modify
5798 + * it under the terms of the GNU General Public License as published by
5799 + * the Free Software Foundation; version 2 of the License
5800 + *
5801 + * This program is distributed in the hope that it will be useful,
5802 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5803 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5804 + * GNU General Public License for more details.
5805 + *
5806 + * You should have received a copy of the GNU General Public License
5807 + * along with this program; if not, write to the Free Software
5808 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5809 + *
5810 + * Copyright (C) 2009-2013 Michael Lee <igvtee@gmail.com>
5811 + */
5812 +
5813 +#include "ralink_soc_eth.h"
5814 +
5815 +static const char fe_gdma_str[][ETH_GSTRING_LEN] = {
5816 +#define _FE(x...) # x,
5817 +FE_STAT_REG_DECLARE
5818 +#undef _FE
5819 +};
5820 +
5821 +static int fe_get_settings(struct net_device *dev,
5822 + struct ethtool_cmd *cmd)
5823 +{
5824 + struct fe_priv *priv = netdev_priv(dev);
5825 + int err;
5826 +
5827 + if (!priv->phy_dev)
5828 + goto out_gset;
5829 +
5830 + if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
5831 + err = phy_read_status(priv->phy_dev);
5832 + if (err)
5833 + goto out_gset;
5834 + }
5835 +
5836 + return phy_ethtool_gset(priv->phy_dev, cmd);
5837 +
5838 +out_gset:
5839 + return -ENODEV;
5840 +}
5841 +
5842 +static int fe_set_settings(struct net_device *dev,
5843 + struct ethtool_cmd *cmd)
5844 +{
5845 + struct fe_priv *priv = netdev_priv(dev);
5846 +
5847 + if (!priv->phy_dev)
5848 + goto out_sset;
5849 +
5850 + if (cmd->phy_address != priv->phy_dev->addr) {
5851 + if (priv->phy->phy_node[cmd->phy_address]) {
5852 + priv->phy_dev = priv->phy->phy[cmd->phy_address];
5853 + priv->phy_flags = FE_PHY_FLAG_PORT;
5854 + } else if (priv->mii_bus &&
5855 + priv->mii_bus->phy_map[cmd->phy_address]) {
5856 + priv->phy_dev = priv->mii_bus->phy_map[cmd->phy_address];
5857 + priv->phy_flags = FE_PHY_FLAG_ATTACH;
5858 + } else
5859 + goto out_sset;
5860 + }
5861 +
5862 + return phy_ethtool_sset(priv->phy_dev, cmd);
5863 +
5864 +out_sset:
5865 + return -ENODEV;
5866 +}
5867 +
5868 +static void fe_get_drvinfo (struct net_device *dev,
5869 + struct ethtool_drvinfo *info)
5870 +{
5871 + struct fe_priv *priv = netdev_priv(dev);
5872 + struct fe_soc_data *soc = priv->soc;
5873 +
5874 + strlcpy(info->driver, priv->device->driver->name, sizeof(info->driver));
5875 + strlcpy(info->version, FE_DRV_VERSION, sizeof(info->version));
5876 + strlcpy(info->bus_info, dev_name(priv->device), sizeof(info->bus_info));
5877 +
5878 + if (soc->reg_table[FE_REG_FE_COUNTER_BASE])
5879 + info->n_stats = ARRAY_SIZE(fe_gdma_str);
5880 +}
5881 +
5882 +static u32 fe_get_msglevel(struct net_device *dev)
5883 +{
5884 + struct fe_priv *priv = netdev_priv(dev);
5885 +
5886 + return priv->msg_enable;
5887 +}
5888 +
5889 +static void fe_set_msglevel(struct net_device *dev, u32 value)
5890 +{
5891 + struct fe_priv *priv = netdev_priv(dev);
5892 +
5893 + priv->msg_enable = value;
5894 +}
5895 +
5896 +static int fe_nway_reset(struct net_device *dev)
5897 +{
5898 + struct fe_priv *priv = netdev_priv(dev);
5899 +
5900 + if (!priv->phy_dev)
5901 + goto out_nway_reset;
5902 +
5903 + return genphy_restart_aneg(priv->phy_dev);
5904 +
5905 +out_nway_reset:
5906 + return -EOPNOTSUPP;
5907 +}
5908 +
5909 +static u32 fe_get_link(struct net_device *dev)
5910 +{
5911 + struct fe_priv *priv = netdev_priv(dev);
5912 + int err;
5913 +
5914 + if (!priv->phy_dev)
5915 + goto out_get_link;
5916 +
5917 + if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
5918 + err = genphy_update_link(priv->phy_dev);
5919 + if (err)
5920 + goto out_get_link;
5921 + }
5922 +
5923 + return priv->phy_dev->link;
5924 +
5925 +out_get_link:
5926 + return ethtool_op_get_link(dev);
5927 +}
5928 +
5929 +static void fe_get_ringparam(struct net_device *dev,
5930 + struct ethtool_ringparam *ring)
5931 +{
5932 + ring->rx_max_pending = MAX_DMA_DESC;
5933 + ring->tx_max_pending = MAX_DMA_DESC;
5934 + ring->rx_pending = NUM_DMA_DESC;
5935 + ring->tx_pending = NUM_DMA_DESC;
5936 +}
5937 +
5938 +static int fe_get_coalesce(struct net_device *dev,
5939 + struct ethtool_coalesce *coal)
5940 +{
5941 + u32 delay_cfg = fe_reg_r32(FE_REG_DLY_INT_CFG);
5942 +
5943 + coal->rx_coalesce_usecs = (delay_cfg & 0xff) * FE_DELAY_TIME;
5944 + coal->rx_max_coalesced_frames = ((delay_cfg >> 8) & 0x7f);
5945 + coal->use_adaptive_rx_coalesce = (delay_cfg >> 15) & 0x1;
5946 +
5947 + coal->tx_coalesce_usecs = ((delay_cfg >> 16 )& 0xff) * FE_DELAY_TIME;
5948 + coal->tx_max_coalesced_frames = ((delay_cfg >> 24) & 0x7f);
5949 + coal->use_adaptive_tx_coalesce = (delay_cfg >> 31) & 0x1;
5950 +
5951 + return 0;
5952 +}
5953 +
5954 +static int fe_set_coalesce(struct net_device *dev,
5955 + struct ethtool_coalesce *coal)
5956 +{
5957 + u32 delay_cfg;
5958 + u32 rx_usecs, tx_usecs;
5959 + u32 rx_frames, tx_frames;
5960 +
5961 + if (!coal->use_adaptive_rx_coalesce || !coal->use_adaptive_tx_coalesce)
5962 + return -EINVAL;
5963 +
5964 + rx_usecs = DIV_ROUND_UP(coal->rx_coalesce_usecs, FE_DELAY_TIME);
5965 + rx_frames = coal->rx_max_coalesced_frames;
5966 + tx_usecs = DIV_ROUND_UP(coal->tx_coalesce_usecs, FE_DELAY_TIME);
5967 + tx_frames = coal->tx_max_coalesced_frames;
5968 +
5969 + if (((tx_usecs == 0) && (tx_frames ==0)) ||
5970 + ((rx_usecs == 0) && (rx_frames ==0)))
5971 + return -EINVAL;
5972 +
5973 + if (rx_usecs > 0xff) rx_usecs = 0xff;
5974 + if (rx_frames > 0x7f) rx_frames = 0x7f;
5975 + if (tx_usecs > 0xff) tx_usecs = 0xff;
5976 + if (tx_frames > 0x7f) tx_frames = 0x7f;
5977 +
5978 + delay_cfg = ((((FE_DELAY_EN_INT | tx_frames) << 8) | tx_usecs) << 16) |
5979 + (((FE_DELAY_EN_INT | rx_frames) << 8) | rx_usecs);
5980 +
5981 + fe_reg_w32(delay_cfg, FE_REG_DLY_INT_CFG);
5982 +
5983 + return 0;
5984 +}
5985 +
5986 +static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5987 +{
5988 + switch (stringset) {
5989 + case ETH_SS_STATS:
5990 + memcpy(data, *fe_gdma_str, sizeof(fe_gdma_str));
5991 + break;
5992 + }
5993 +}
5994 +
5995 +static int fe_get_sset_count(struct net_device *dev, int sset)
5996 +{
5997 + switch (sset) {
5998 + case ETH_SS_STATS:
5999 + return ARRAY_SIZE(fe_gdma_str);
6000 + default:
6001 + return -EOPNOTSUPP;
6002 + }
6003 +}
6004 +
6005 +static void fe_get_ethtool_stats(struct net_device *dev,
6006 + struct ethtool_stats *stats, u64 *data)
6007 +{
6008 + struct fe_priv *priv = netdev_priv(dev);
6009 + struct fe_hw_stats *hwstats = priv->hw_stats;
6010 + u64 *data_src, *data_dst;
6011 + unsigned int start;
6012 + int i;
6013 +
6014 + if (netif_running(dev) && netif_device_present(dev)) {
6015 + if (spin_trylock(&hwstats->stats_lock)) {
6016 + fe_stats_update(priv);
6017 + spin_unlock(&hwstats->stats_lock);
6018 + }
6019 + }
6020 +
6021 + do {
6022 + data_src = &hwstats->tx_bytes;
6023 + data_dst = data;
6024 + start = u64_stats_fetch_begin_bh(&hwstats->syncp);
6025 +
6026 + for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
6027 + *data_dst++ = *data_src++;
6028 +
6029 + } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
6030 +}
6031 +
6032 +static struct ethtool_ops fe_ethtool_ops = {
6033 + .get_settings = fe_get_settings,
6034 + .set_settings = fe_set_settings,
6035 + .get_drvinfo = fe_get_drvinfo,
6036 + .get_msglevel = fe_get_msglevel,
6037 + .set_msglevel = fe_set_msglevel,
6038 + .nway_reset = fe_nway_reset,
6039 + .get_link = fe_get_link,
6040 + .get_ringparam = fe_get_ringparam,
6041 + .get_coalesce = fe_get_coalesce,
6042 + .set_coalesce = fe_set_coalesce,
6043 +};
6044 +
6045 +void fe_set_ethtool_ops(struct net_device *netdev)
6046 +{
6047 + struct fe_priv *priv = netdev_priv(netdev);
6048 + struct fe_soc_data *soc = priv->soc;
6049 +
6050 + if (soc->reg_table[FE_REG_FE_COUNTER_BASE]) {
6051 + fe_ethtool_ops.get_strings = fe_get_strings;
6052 + fe_ethtool_ops.get_sset_count = fe_get_sset_count;
6053 + fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
6054 + }
6055 +
6056 + SET_ETHTOOL_OPS(netdev, &fe_ethtool_ops);
6057 +}
6058 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_ethtool.h
6059 ===================================================================
6060 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
6061 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_ethtool.h 2014-10-29 20:25:55.433357519 +0100
6062 @@ -0,0 +1,25 @@
6063 +/*
6064 + * This program is free software; you can redistribute it and/or modify
6065 + * it under the terms of the GNU General Public License as published by
6066 + * the Free Software Foundation; version 2 of the License
6067 + *
6068 + * This program is distributed in the hope that it will be useful,
6069 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6070 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6071 + * GNU General Public License for more details.
6072 + *
6073 + * You should have received a copy of the GNU General Public License
6074 + * along with this program; if not, write to the Free Software
6075 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
6076 + *
6077 + * Copyright (C) 2009-2013 Michael Lee <igvtee@gmail.com>
6078 + */
6079 +
6080 +#ifndef FE_ETHTOOL_H
6081 +#define FE_ETHTOOL_H
6082 +
6083 +#include <linux/ethtool.h>
6084 +
6085 +void fe_set_ethtool_ops(struct net_device *netdev);
6086 +
6087 +#endif /* FE_ETHTOOL_H */
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