target/linux/ramips/patches-3.14/0047-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch

   1 From 4b23ed96930650076caa524ffdde898cb937bdaa Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 4 Aug 2014 20:36:29 +0200
   4 Subject: [PATCH 47/57] GPIO: MIPS: ralink: add gpio driver for ralink SoC
   5
   6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
   7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Cc: linux-mips@linux-mips.org
  11 Cc: linux-gpio@vger.kernel.org
  12 ---
  13  arch/mips/include/asm/mach-ralink/gpio.h |   24 +++
  14  drivers/gpio/Kconfig                     |    6 +
  15  drivers/gpio/Makefile                    |    1 +
  16  drivers/gpio/gpio-ralink.c               |  345 ++++++++++++++++++++++++++++++
  17  4 files changed, 376 insertions(+)
  18  create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
  19  create mode 100644 drivers/gpio/gpio-ralink.c
  20
  21 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/gpio.h
  22 ===================================================================
  23 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  24 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/gpio.h      2014-09-13 02:13:22.536816660 +0200
  25 @@ -0,0 +1,24 @@
  26 +/*
  27 + *  Ralink SoC GPIO API support
  28 + *
  29 + *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  30 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  31 + *
  32 + *  This program is free software; you can redistribute it and/or modify it
  33 + *  under the terms of the GNU General Public License version 2 as published
  34 + *  by the Free Software Foundation.
  35 + *
  36 + */
  37 +
  38 +#ifndef __ASM_MACH_RALINK_GPIO_H
  39 +#define __ASM_MACH_RALINK_GPIO_H
  40 +
  41 +#define ARCH_NR_GPIOS  128
  42 +#include <asm-generic/gpio.h>
  43 +
  44 +#define gpio_get_value __gpio_get_value
  45 +#define gpio_set_value __gpio_set_value
  46 +#define gpio_cansleep  __gpio_cansleep
  47 +#define gpio_to_irq    __gpio_to_irq
  48 +
  49 +#endif /* __ASM_MACH_RALINK_GPIO_H */
  50 Index: linux-3.14.18/drivers/gpio/Kconfig
  51 ===================================================================
  52 --- linux-3.14.18.orig/drivers/gpio/Kconfig     2014-09-06 01:34:59.000000000 +0200
  53 +++ linux-3.14.18/drivers/gpio/Kconfig  2014-10-02 21:52:28.693719524 +0200
  54 @@ -260,6 +260,12 @@
  55           To compile this driver as a module, choose M here: the module will
  56           be called gpio-sch311x.
  57
  58 +config GPIO_RALINK
  59 +       bool "Ralink GPIO Support"
  60 +       depends on RALINK
  61 +       help
  62 +         Say yes here to support the Ralink SoC GPIO device
  63 +
  64  config GPIO_SPEAR_SPICS
  65         bool "ST SPEAr13xx SPI Chip Select as GPIO support"
  66         depends on PLAT_SPEAR
  67 Index: linux-3.14.18/drivers/gpio/Makefile
  68 ===================================================================
  69 --- linux-3.14.18.orig/drivers/gpio/Makefile    2014-09-06 01:34:59.000000000 +0200
  70 +++ linux-3.14.18/drivers/gpio/Makefile 2014-10-02 21:52:28.693719524 +0200
  71 @@ -63,6 +63,7 @@
  72  obj-$(CONFIG_GPIO_PCH)         += gpio-pch.o
  73  obj-$(CONFIG_GPIO_PL061)       += gpio-pl061.o
  74  obj-$(CONFIG_GPIO_PXA)         += gpio-pxa.o
  75 +obj-$(CONFIG_GPIO_RALINK)      += gpio-ralink.o
  76  obj-$(CONFIG_GPIO_RC5T583)     += gpio-rc5t583.o
  77  obj-$(CONFIG_GPIO_RDC321X)     += gpio-rdc321x.o
  78  obj-$(CONFIG_GPIO_RCAR)                += gpio-rcar.o
  79 Index: linux-3.14.18/drivers/gpio/gpio-ralink.c
  80 ===================================================================
  81 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  82 +++ linux-3.14.18/drivers/gpio/gpio-ralink.c    2014-10-02 21:52:24.081719605 +0200
  83 @@ -0,0 +1,353 @@
  84 +/*
  85 + * This program is free software; you can redistribute it and/or modify it
  86 + * under the terms of the GNU General Public License version 2 as published
  87 + * by the Free Software Foundation.
  88 + *
  89 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  90 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  91 + */
  92 +
  93 +#include <linux/module.h>
  94 +#include <linux/io.h>
  95 +#include <linux/gpio.h>
  96 +#include <linux/spinlock.h>
  97 +#include <linux/platform_device.h>
  98 +#include <linux/of_irq.h>
  99 +#include <linux/irqdomain.h>
 100 +#include <linux/interrupt.h>
 101 +
 102 +enum ralink_gpio_reg {
 103 +       GPIO_REG_INT = 0,
 104 +       GPIO_REG_EDGE,
 105 +       GPIO_REG_RENA,
 106 +       GPIO_REG_FENA,
 107 +       GPIO_REG_DATA,
 108 +       GPIO_REG_DIR,
 109 +       GPIO_REG_POL,
 110 +       GPIO_REG_SET,
 111 +       GPIO_REG_RESET,
 112 +       GPIO_REG_TOGGLE,
 113 +       GPIO_REG_MAX
 114 +};
 115 +
 116 +struct ralink_gpio_chip {
 117 +       struct gpio_chip chip;
 118 +       u8 regs[GPIO_REG_MAX];
 119 +
 120 +       spinlock_t lock;
 121 +       void __iomem *membase;
 122 +       struct irq_domain *domain;
 123 +       int irq;
 124 +
 125 +       u32 rising;
 126 +       u32 falling;
 127 +};
 128 +
 129 +#define MAP_MAX        4
 130 +static struct irq_domain *irq_map[MAP_MAX];
 131 +static int irq_map_count;
 132 +static atomic_t irq_refcount = ATOMIC_INIT(0);
 133 +
 134 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
 135 +{
 136 +       struct ralink_gpio_chip *rg;
 137 +
 138 +       rg = container_of(chip, struct ralink_gpio_chip, chip);
 139 +
 140 +       return rg;
 141 +}
 142 +
 143 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
 144 +{
 145 +       iowrite32(val, rg->membase + rg->regs[reg]);
 146 +}
 147 +
 148 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
 149 +{
 150 +       return ioread32(rg->membase + rg->regs[reg]);
 151 +}
 152 +
 153 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 154 +{
 155 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 156 +
 157 +       rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
 158 +}
 159 +
 160 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
 161 +{
 162 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 163 +
 164 +       return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 165 +}
 166 +
 167 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 168 +{
 169 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 170 +       unsigned long flags;
 171 +       u32 t;
 172 +
 173 +       spin_lock_irqsave(&rg->lock, flags);
 174 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 175 +       t &= ~BIT(offset);
 176 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 177 +       spin_unlock_irqrestore(&rg->lock, flags);
 178 +
 179 +       return 0;
 180 +}
 181 +
 182 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
 183 +                                       unsigned offset, int value)
 184 +{
 185 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 186 +       unsigned long flags;
 187 +       u32 t;
 188 +
 189 +       spin_lock_irqsave(&rg->lock, flags);
 190 +       ralink_gpio_set(chip, offset, value);
 191 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 192 +       t |= BIT(offset);
 193 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 194 +       spin_unlock_irqrestore(&rg->lock, flags);
 195 +
 196 +       return 0;
 197 +}
 198 +
 199 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 200 +{
 201 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 202 +
 203 +       if (rg->irq < 1)
 204 +               return -1;
 205 +
 206 +       return irq_create_mapping(rg->domain, pin);
 207 +}
 208 +
 209 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 210 +{
 211 +       int i;
 212 +
 213 +       for (i = 0; i < irq_map_count; i++) {
 214 +               struct irq_domain *domain = irq_map[i];
 215 +               struct ralink_gpio_chip *rg;
 216 +               unsigned long pending;
 217 +               int bit;
 218 +
 219 +               rg = (struct ralink_gpio_chip *) domain->host_data;
 220 +               pending = rt_gpio_r32(rg, GPIO_REG_INT);
 221 +
 222 +               for_each_set_bit(bit, &pending, rg->chip.ngpio) {
 223 +                       u32 map = irq_find_mapping(domain, bit);
 224 +                       generic_handle_irq(map);
 225 +                       rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
 226 +               }
 227 +       }
 228 +}
 229 +
 230 +static void ralink_gpio_irq_unmask(struct irq_data *d)
 231 +{
 232 +       struct ralink_gpio_chip *rg;
 233 +       unsigned long flags;
 234 +       u32 val;
 235 +
 236 +       rg = (struct ralink_gpio_chip *) d->domain->host_data;
 237 +       val = rt_gpio_r32(rg, GPIO_REG_RENA);
 238 +
 239 +       spin_lock_irqsave(&rg->lock, flags);
 240 +       rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
 241 +       rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
 242 +       spin_unlock_irqrestore(&rg->lock, flags);
 243 +}
 244 +
 245 +static void ralink_gpio_irq_mask(struct irq_data *d)
 246 +{
 247 +       struct ralink_gpio_chip *rg;
 248 +       unsigned long flags;
 249 +       u32 val;
 250 +
 251 +       rg = (struct ralink_gpio_chip *) d->domain->host_data;
 252 +       val = rt_gpio_r32(rg, GPIO_REG_RENA);
 253 +
 254 +       spin_lock_irqsave(&rg->lock, flags);
 255 +       rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
 256 +       rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
 257 +       spin_unlock_irqrestore(&rg->lock, flags);
 258 +}
 259 +
 260 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
 261 +{
 262 +       struct ralink_gpio_chip *rg;
 263 +       u32 mask = BIT(d->hwirq);
 264 +
 265 +       rg = (struct ralink_gpio_chip *) d->domain->host_data;
 266 +
 267 +       if (type == IRQ_TYPE_PROBE) {
 268 +               if ((rg->rising | rg->falling) & mask)
 269 +                       return 0;
 270 +
 271 +               type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 272 +       }
 273 +
 274 +       if (type & IRQ_TYPE_EDGE_RISING)
 275 +               rg->rising |= mask;
 276 +       else
 277 +               rg->rising &= ~mask;
 278 +
 279 +       if (type & IRQ_TYPE_EDGE_FALLING)
 280 +               rg->falling |= mask;
 281 +       else
 282 +               rg->falling &= ~mask;
 283 +
 284 +       return 0;
 285 +}
 286 +
 287 +static struct irq_chip ralink_gpio_irq_chip = {
 288 +       .name           = "GPIO",
 289 +       .irq_unmask     = ralink_gpio_irq_unmask,
 290 +       .irq_mask       = ralink_gpio_irq_mask,
 291 +       .irq_mask_ack   = ralink_gpio_irq_mask,
 292 +       .irq_set_type   = ralink_gpio_irq_type,
 293 +};
 294 +
 295 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 296 +{
 297 +       irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
 298 +       irq_set_handler_data(irq, d);
 299 +
 300 +       return 0;
 301 +}
 302 +
 303 +static const struct irq_domain_ops irq_domain_ops = {
 304 +       .xlate = irq_domain_xlate_onecell,
 305 +       .map = gpio_map,
 306 +};
 307 +
 308 +static void ralink_gpio_irq_init(struct device_node *np,
 309 +                                struct ralink_gpio_chip *rg)
 310 +{
 311 +       if (irq_map_count >= MAP_MAX)
 312 +               return;
 313 +
 314 +       rg->irq = irq_of_parse_and_map(np, 0);
 315 +       if (!rg->irq)
 316 +               return;
 317 +
 318 +       rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
 319 +                                          &irq_domain_ops, rg);
 320 +       if (!rg->domain) {
 321 +               dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
 322 +               return;
 323 +       }
 324 +
 325 +       irq_map[irq_map_count++] = rg->domain;
 326 +
 327 +       rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
 328 +       rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
 329 +
 330 +       if (!atomic_read(&irq_refcount))
 331 +               irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
 332 +       atomic_inc(&irq_refcount);
 333 +
 334 +       dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
 335 +}
 336 +
 337 +static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
 338 +{
 339 +       int gpio = chip->base + offset;
 340 +
 341 +       return pinctrl_request_gpio(gpio);
 342 +}
 343 +
 344 +static void ralink_gpio_free(struct gpio_chip *chip, unsigned offset)
 345 +{
 346 +       int gpio = chip->base + offset;
 347 +
 348 +       pinctrl_free_gpio(gpio);
 349 +}
 350 +
 351 +static int ralink_gpio_probe(struct platform_device *pdev)
 352 +{
 353 +       struct device_node *np = pdev->dev.of_node;
 354 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 355 +       struct ralink_gpio_chip *rg;
 356 +       const __be32 *ngpio, *gpiobase;
 357 +
 358 +       if (!res) {
 359 +               dev_err(&pdev->dev, "failed to find resource\n");
 360 +               return -ENOMEM;
 361 +       }
 362 +
 363 +       rg = devm_kzalloc(&pdev->dev,
 364 +                       sizeof(struct ralink_gpio_chip), GFP_KERNEL);
 365 +       if (!rg)
 366 +               return -ENOMEM;
 367 +
 368 +       rg->membase = devm_request_and_ioremap(&pdev->dev, res);
 369 +       if (!rg->membase) {
 370 +               dev_err(&pdev->dev, "cannot remap I/O memory region\n");
 371 +               return -ENOMEM;
 372 +       }
 373 +
 374 +       if (of_property_read_u8_array(np, "ralink,register-map",
 375 +                       rg->regs, GPIO_REG_MAX)) {
 376 +               dev_err(&pdev->dev, "failed to read register definition\n");
 377 +               return -EINVAL;
 378 +       }
 379 +
 380 +       ngpio = of_get_property(np, "ralink,num-gpios", NULL);
 381 +       if (!ngpio) {
 382 +               dev_err(&pdev->dev, "failed to read number of pins\n");
 383 +               return -EINVAL;
 384 +       }
 385 +
 386 +       gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
 387 +       if (gpiobase)
 388 +               rg->chip.base = be32_to_cpu(*gpiobase);
 389 +       else
 390 +               rg->chip.base = -1;
 391 +
 392 +       spin_lock_init(&rg->lock);
 393 +
 394 +       rg->chip.dev = &pdev->dev;
 395 +       rg->chip.label = dev_name(&pdev->dev);
 396 +       rg->chip.of_node = np;
 397 +       rg->chip.ngpio = be32_to_cpu(*ngpio);
 398 +       rg->chip.direction_input = ralink_gpio_direction_input;
 399 +       rg->chip.direction_output = ralink_gpio_direction_output;
 400 +       rg->chip.get = ralink_gpio_get;
 401 +       rg->chip.set = ralink_gpio_set;
 402 +       rg->chip.request = ralink_gpio_request;
 403 +       rg->chip.to_irq = ralink_gpio_to_irq;
 404 +       rg->chip.free = ralink_gpio_free;
 405 +
 406 +       /* set polarity to low for all lines */
 407 +       rt_gpio_w32(rg, GPIO_REG_POL, 0);
 408 +
 409 +       dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
 410 +
 411 +       ralink_gpio_irq_init(np, rg);
 412 +
 413 +       return gpiochip_add(&rg->chip);
 414 +}
 415 +
 416 +static const struct of_device_id ralink_gpio_match[] = {
 417 +       { .compatible = "ralink,rt2880-gpio" },
 418 +       {},
 419 +};
 420 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
 421 +
 422 +static struct platform_driver ralink_gpio_driver = {
 423 +       .probe = ralink_gpio_probe,
 424 +       .driver = {
 425 +               .name = "rt2880_gpio",
 426 +               .owner = THIS_MODULE,
 427 +               .of_match_table = ralink_gpio_match,
 428 +       },
 429 +};
 430 +
 431 +static int __init ralink_gpio_init(void)
 432 +{
 433 +       return platform_driver_register(&ralink_gpio_driver);
 434 +}
 435 +
 436 +subsys_initcall(ralink_gpio_init);