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c50384cfcca9967a4258974abd04a5e6a9706f91
[openwrt/openwrt.git] / target / linux / ramips / patches-3.18 / 0030-pinctrl-ralink-add-pinctrl-driver.patch
1 From 675c6ddd9432c39f508f9d6bdda17d9c675788cf Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:34:05 +0100
4 Subject: [PATCH 30/57] pinctrl: ralink: add pinctrl driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/Kconfig | 2 +
9 arch/mips/include/asm/mach-ralink/mt7620.h | 41 ++-
10 arch/mips/include/asm/mach-ralink/pinmux.h | 53 ++++
11 arch/mips/include/asm/mach-ralink/rt305x.h | 35 ++-
12 arch/mips/include/asm/mach-ralink/rt3883.h | 16 +-
13 arch/mips/ralink/common.h | 19 --
14 arch/mips/ralink/mt7620.c | 159 +++-------
15 arch/mips/ralink/rt288x.c | 62 ++--
16 arch/mips/ralink/rt305x.c | 151 ++++-----
17 arch/mips/ralink/rt3883.c | 173 +++--------
18 drivers/pinctrl/Kconfig | 5 +
19 drivers/pinctrl/Makefile | 1 +
20 drivers/pinctrl/pinctrl-rt2880.c | 467 ++++++++++++++++++++++++++++
21 13 files changed, 764 insertions(+), 420 deletions(-)
22 create mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h
23 create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
24
25 --- a/arch/mips/Kconfig
26 +++ b/arch/mips/Kconfig
27 @@ -453,6 +453,8 @@
28 select CLKDEV_LOOKUP
29 select ARCH_HAS_RESET_CONTROLLER
30 select RESET_CONTROLLER
31 + select PINCTRL
32 + select PINCTRL_RT2880
33
34 config SGI_IP22
35 bool "SGI IP22 (Indy/Indigo2)"
36 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
37 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
38 @@ -90,7 +90,6 @@
39 #define MT7620_DDR2_SIZE_MIN 32
40 #define MT7620_DDR2_SIZE_MAX 256
41
42 -#define MT7620_GPIO_MODE_I2C BIT(0)
43 #define MT7620_GPIO_MODE_UART0_SHIFT 2
44 #define MT7620_GPIO_MODE_UART0_MASK 0x7
45 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
46 @@ -102,16 +101,36 @@
47 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
48 #define MT7620_GPIO_MODE_GPIO_I2S 0x6
49 #define MT7620_GPIO_MODE_GPIO 0x7
50 -#define MT7620_GPIO_MODE_UART1 BIT(5)
51 -#define MT7620_GPIO_MODE_MDIO BIT(8)
52 -#define MT7620_GPIO_MODE_RGMII1 BIT(9)
53 -#define MT7620_GPIO_MODE_RGMII2 BIT(10)
54 -#define MT7620_GPIO_MODE_SPI BIT(11)
55 -#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
56 -#define MT7620_GPIO_MODE_WLED BIT(13)
57 -#define MT7620_GPIO_MODE_JTAG BIT(15)
58 -#define MT7620_GPIO_MODE_EPHY BIT(15)
59 -#define MT7620_GPIO_MODE_WDT BIT(22)
60 +
61 +#define MT7620_GPIO_MODE_NAND 0
62 +#define MT7620_GPIO_MODE_SD 1
63 +#define MT7620_GPIO_MODE_ND_SD_GPIO 2
64 +#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
65 +#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
66 +
67 +#define MT7620_GPIO_MODE_PCIE_RST 0
68 +#define MT7620_GPIO_MODE_PCIE_REF 1
69 +#define MT7620_GPIO_MODE_PCIE_GPIO 2
70 +#define MT7620_GPIO_MODE_PCIE_MASK 0x3
71 +#define MT7620_GPIO_MODE_PCIE_SHIFT 16
72 +
73 +#define MT7620_GPIO_MODE_WDT_RST 0
74 +#define MT7620_GPIO_MODE_WDT_REF 1
75 +#define MT7620_GPIO_MODE_WDT_GPIO 2
76 +#define MT7620_GPIO_MODE_WDT_MASK 0x3
77 +#define MT7620_GPIO_MODE_WDT_SHIFT 21
78 +
79 +#define MT7620_GPIO_MODE_I2C 0
80 +#define MT7620_GPIO_MODE_UART1 5
81 +#define MT7620_GPIO_MODE_MDIO 8
82 +#define MT7620_GPIO_MODE_RGMII1 9
83 +#define MT7620_GPIO_MODE_RGMII2 10
84 +#define MT7620_GPIO_MODE_SPI 11
85 +#define MT7620_GPIO_MODE_SPI_REF_CLK 12
86 +#define MT7620_GPIO_MODE_WLED 13
87 +#define MT7620_GPIO_MODE_JTAG 15
88 +#define MT7620_GPIO_MODE_EPHY 15
89 +#define MT7620_GPIO_MODE_PA 20
90
91 static inline int mt7620_get_eco(void)
92 {
93 --- /dev/null
94 +++ b/arch/mips/include/asm/mach-ralink/pinmux.h
95 @@ -0,0 +1,53 @@
96 +/*
97 + * This program is free software; you can redistribute it and/or modify
98 + * it under the terms of the GNU General Public License version 2 as
99 + * publishhed by the Free Software Foundation.
100 + *
101 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
102 + */
103 +
104 +#ifndef _RT288X_PINMUX_H__
105 +#define _RT288X_PINMUX_H__
106 +
107 +#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
108 +#define GRP(_name, _func, _mask, _shift) \
109 + { .name = _name, .mask = _mask, .shift = _shift, \
110 + .func = _func, .gpio = _mask, \
111 + .func_count = ARRAY_SIZE(_func) }
112 +
113 +#define GRP_G(_name, _func, _mask, _gpio, _shift) \
114 + { .name = _name, .mask = _mask, .shift = _shift, \
115 + .func = _func, .gpio = _gpio, \
116 + .func_count = ARRAY_SIZE(_func) }
117 +
118 +struct rt2880_pmx_group;
119 +
120 +struct rt2880_pmx_func {
121 + const char *name;
122 + const char value;
123 +
124 + int pin_first;
125 + int pin_count;
126 + int *pins;
127 +
128 + int *groups;
129 + int group_count;
130 +
131 + int enabled;
132 +};
133 +
134 +struct rt2880_pmx_group {
135 + const char *name;
136 + int enabled;
137 +
138 + const u32 shift;
139 + const char mask;
140 + const char gpio;
141 +
142 + struct rt2880_pmx_func *func;
143 + int func_count;
144 +};
145 +
146 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
147 +
148 +#endif
149 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
150 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
151 @@ -125,24 +125,29 @@
152 #define RT305X_GPIO_GE0_TXD0 40
153 #define RT305X_GPIO_GE0_RXCLK 51
154
155 -#define RT305X_GPIO_MODE_I2C BIT(0)
156 -#define RT305X_GPIO_MODE_SPI BIT(1)
157 #define RT305X_GPIO_MODE_UART0_SHIFT 2
158 #define RT305X_GPIO_MODE_UART0_MASK 0x7
159 #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
160 -#define RT305X_GPIO_MODE_UARTF 0x0
161 -#define RT305X_GPIO_MODE_PCM_UARTF 0x1
162 -#define RT305X_GPIO_MODE_PCM_I2S 0x2
163 -#define RT305X_GPIO_MODE_I2S_UARTF 0x3
164 -#define RT305X_GPIO_MODE_PCM_GPIO 0x4
165 -#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
166 -#define RT305X_GPIO_MODE_GPIO_I2S 0x6
167 -#define RT305X_GPIO_MODE_GPIO 0x7
168 -#define RT305X_GPIO_MODE_UART1 BIT(5)
169 -#define RT305X_GPIO_MODE_JTAG BIT(6)
170 -#define RT305X_GPIO_MODE_MDIO BIT(7)
171 -#define RT305X_GPIO_MODE_SDRAM BIT(8)
172 -#define RT305X_GPIO_MODE_RGMII BIT(9)
173 +#define RT305X_GPIO_MODE_UARTF 0
174 +#define RT305X_GPIO_MODE_PCM_UARTF 1
175 +#define RT305X_GPIO_MODE_PCM_I2S 2
176 +#define RT305X_GPIO_MODE_I2S_UARTF 3
177 +#define RT305X_GPIO_MODE_PCM_GPIO 4
178 +#define RT305X_GPIO_MODE_GPIO_UARTF 5
179 +#define RT305X_GPIO_MODE_GPIO_I2S 6
180 +#define RT305X_GPIO_MODE_GPIO 7
181 +
182 +#define RT305X_GPIO_MODE_I2C 0
183 +#define RT305X_GPIO_MODE_SPI 1
184 +#define RT305X_GPIO_MODE_UART1 5
185 +#define RT305X_GPIO_MODE_JTAG 6
186 +#define RT305X_GPIO_MODE_MDIO 7
187 +#define RT305X_GPIO_MODE_SDRAM 8
188 +#define RT305X_GPIO_MODE_RGMII 9
189 +#define RT5350_GPIO_MODE_PHY_LED 14
190 +#define RT5350_GPIO_MODE_SPI_CS1 21
191 +#define RT3352_GPIO_MODE_LNA 18
192 +#define RT3352_GPIO_MODE_PA 20
193
194 #define RT3352_SYSC_REG_SYSCFG0 0x010
195 #define RT3352_SYSC_REG_SYSCFG1 0x014
196 --- a/arch/mips/include/asm/mach-ralink/rt3883.h
197 +++ b/arch/mips/include/asm/mach-ralink/rt3883.h
198 @@ -112,8 +112,6 @@
199 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
200 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
201
202 -#define RT3883_GPIO_MODE_I2C BIT(0)
203 -#define RT3883_GPIO_MODE_SPI BIT(1)
204 #define RT3883_GPIO_MODE_UART0_SHIFT 2
205 #define RT3883_GPIO_MODE_UART0_MASK 0x7
206 #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
207 @@ -125,11 +123,15 @@
208 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
209 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
210 #define RT3883_GPIO_MODE_GPIO 0x7
211 -#define RT3883_GPIO_MODE_UART1 BIT(5)
212 -#define RT3883_GPIO_MODE_JTAG BIT(6)
213 -#define RT3883_GPIO_MODE_MDIO BIT(7)
214 -#define RT3883_GPIO_MODE_GE1 BIT(9)
215 -#define RT3883_GPIO_MODE_GE2 BIT(10)
216 +
217 +#define RT3883_GPIO_MODE_I2C 0
218 +#define RT3883_GPIO_MODE_SPI 1
219 +#define RT3883_GPIO_MODE_UART1 5
220 +#define RT3883_GPIO_MODE_JTAG 6
221 +#define RT3883_GPIO_MODE_MDIO 7
222 +#define RT3883_GPIO_MODE_GE1 9
223 +#define RT3883_GPIO_MODE_GE2 10
224 +
225 #define RT3883_GPIO_MODE_PCI_SHIFT 11
226 #define RT3883_GPIO_MODE_PCI_MASK 0x7
227 #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
228 --- a/arch/mips/ralink/common.h
229 +++ b/arch/mips/ralink/common.h
230 @@ -11,25 +11,6 @@
231
232 #define RAMIPS_SYS_TYPE_LEN 32
233
234 -struct ralink_pinmux_grp {
235 - const char *name;
236 - u32 mask;
237 - int gpio_first;
238 - int gpio_last;
239 -};
240 -
241 -struct ralink_pinmux {
242 - struct ralink_pinmux_grp *mode;
243 - struct ralink_pinmux_grp *uart;
244 - int uart_shift;
245 - u32 uart_mask;
246 - void (*wdt_reset)(void);
247 - struct ralink_pinmux_grp *pci;
248 - int pci_shift;
249 - u32 pci_mask;
250 -};
251 -extern struct ralink_pinmux rt_gpio_pinmux;
252 -
253 struct ralink_soc_info {
254 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
255 unsigned char *compatible;
256 --- a/arch/mips/ralink/mt7620.c
257 +++ b/arch/mips/ralink/mt7620.c
258 @@ -17,6 +17,7 @@
259 #include <asm/mipsregs.h>
260 #include <asm/mach-ralink/ralink_regs.h>
261 #include <asm/mach-ralink/mt7620.h>
262 +#include <asm/mach-ralink/pinmux.h>
263
264 #include "common.h"
265
266 @@ -47,118 +48,58 @@
267 /* does the board have sdram or ddram */
268 static int dram_type;
269
270 -static struct ralink_pinmux_grp mode_mux[] = {
271 - {
272 - .name = "i2c",
273 - .mask = MT7620_GPIO_MODE_I2C,
274 - .gpio_first = 1,
275 - .gpio_last = 2,
276 - }, {
277 - .name = "spi",
278 - .mask = MT7620_GPIO_MODE_SPI,
279 - .gpio_first = 3,
280 - .gpio_last = 6,
281 - }, {
282 - .name = "uartlite",
283 - .mask = MT7620_GPIO_MODE_UART1,
284 - .gpio_first = 15,
285 - .gpio_last = 16,
286 - }, {
287 - .name = "wdt",
288 - .mask = MT7620_GPIO_MODE_WDT,
289 - .gpio_first = 17,
290 - .gpio_last = 17,
291 - }, {
292 - .name = "mdio",
293 - .mask = MT7620_GPIO_MODE_MDIO,
294 - .gpio_first = 22,
295 - .gpio_last = 23,
296 - }, {
297 - .name = "rgmii1",
298 - .mask = MT7620_GPIO_MODE_RGMII1,
299 - .gpio_first = 24,
300 - .gpio_last = 35,
301 - }, {
302 - .name = "spi refclk",
303 - .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
304 - .gpio_first = 37,
305 - .gpio_last = 39,
306 - }, {
307 - .name = "jtag",
308 - .mask = MT7620_GPIO_MODE_JTAG,
309 - .gpio_first = 40,
310 - .gpio_last = 44,
311 - }, {
312 - /* shared lines with jtag */
313 - .name = "ephy",
314 - .mask = MT7620_GPIO_MODE_EPHY,
315 - .gpio_first = 40,
316 - .gpio_last = 44,
317 - }, {
318 - .name = "nand",
319 - .mask = MT7620_GPIO_MODE_JTAG,
320 - .gpio_first = 45,
321 - .gpio_last = 59,
322 - }, {
323 - .name = "rgmii2",
324 - .mask = MT7620_GPIO_MODE_RGMII2,
325 - .gpio_first = 60,
326 - .gpio_last = 71,
327 - }, {
328 - .name = "wled",
329 - .mask = MT7620_GPIO_MODE_WLED,
330 - .gpio_first = 72,
331 - .gpio_last = 72,
332 - }, {0}
333 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
334 +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
335 +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
336 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
337 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
338 +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
339 +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
340 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
341 +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
342 +static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
343 +static struct rt2880_pmx_func uartf_grp[] = {
344 + FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
345 + FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
346 + FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
347 + FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
348 + FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
349 + FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
350 + FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
351 };
352 -
353 -static struct ralink_pinmux_grp uart_mux[] = {
354 - {
355 - .name = "uartf",
356 - .mask = MT7620_GPIO_MODE_UARTF,
357 - .gpio_first = 7,
358 - .gpio_last = 14,
359 - }, {
360 - .name = "pcm uartf",
361 - .mask = MT7620_GPIO_MODE_PCM_UARTF,
362 - .gpio_first = 7,
363 - .gpio_last = 14,
364 - }, {
365 - .name = "pcm i2s",
366 - .mask = MT7620_GPIO_MODE_PCM_I2S,
367 - .gpio_first = 7,
368 - .gpio_last = 14,
369 - }, {
370 - .name = "i2s uartf",
371 - .mask = MT7620_GPIO_MODE_I2S_UARTF,
372 - .gpio_first = 7,
373 - .gpio_last = 14,
374 - }, {
375 - .name = "pcm gpio",
376 - .mask = MT7620_GPIO_MODE_PCM_GPIO,
377 - .gpio_first = 11,
378 - .gpio_last = 14,
379 - }, {
380 - .name = "gpio uartf",
381 - .mask = MT7620_GPIO_MODE_GPIO_UARTF,
382 - .gpio_first = 7,
383 - .gpio_last = 10,
384 - }, {
385 - .name = "gpio i2s",
386 - .mask = MT7620_GPIO_MODE_GPIO_I2S,
387 - .gpio_first = 7,
388 - .gpio_last = 10,
389 - }, {
390 - .name = "gpio",
391 - .mask = MT7620_GPIO_MODE_GPIO,
392 - }, {0}
393 +static struct rt2880_pmx_func wdt_grp[] = {
394 + FUNC("wdt rst", 0, 17, 1),
395 + FUNC("wdt refclk", 0, 17, 1),
396 + };
397 +static struct rt2880_pmx_func pcie_rst_grp[] = {
398 + FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
399 + FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
400 +};
401 +static struct rt2880_pmx_func nd_sd_grp[] = {
402 + FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
403 + FUNC("sd", MT7620_GPIO_MODE_SD, 45, 15)
404 };
405
406 -struct ralink_pinmux rt_gpio_pinmux = {
407 - .mode = mode_mux,
408 - .uart = uart_mux,
409 - .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
410 - .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
411 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
412 + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
413 + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
414 + MT7620_GPIO_MODE_UART0_SHIFT),
415 + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
416 + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
417 + GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
418 + MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
419 + GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
420 + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
421 + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
422 + GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
423 + MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
424 + GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
425 + MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
426 + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
427 + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
428 + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
429 + GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
430 + { 0 }
431 };
432
433 static struct rt2880_pmx_func pwm1_grp_mt7628[] = {
434 --- a/arch/mips/ralink/rt288x.c
435 +++ b/arch/mips/ralink/rt288x.c
436 @@ -17,46 +17,27 @@
437 #include <asm/mipsregs.h>
438 #include <asm/mach-ralink/ralink_regs.h>
439 #include <asm/mach-ralink/rt288x.h>
440 +#include <asm/mach-ralink/pinmux.h>
441
442 #include "common.h"
443
444 -static struct ralink_pinmux_grp mode_mux[] = {
445 - {
446 - .name = "i2c",
447 - .mask = RT2880_GPIO_MODE_I2C,
448 - .gpio_first = 1,
449 - .gpio_last = 2,
450 - }, {
451 - .name = "spi",
452 - .mask = RT2880_GPIO_MODE_SPI,
453 - .gpio_first = 3,
454 - .gpio_last = 6,
455 - }, {
456 - .name = "uartlite",
457 - .mask = RT2880_GPIO_MODE_UART0,
458 - .gpio_first = 7,
459 - .gpio_last = 14,
460 - }, {
461 - .name = "jtag",
462 - .mask = RT2880_GPIO_MODE_JTAG,
463 - .gpio_first = 17,
464 - .gpio_last = 21,
465 - }, {
466 - .name = "mdio",
467 - .mask = RT2880_GPIO_MODE_MDIO,
468 - .gpio_first = 22,
469 - .gpio_last = 23,
470 - }, {
471 - .name = "sdram",
472 - .mask = RT2880_GPIO_MODE_SDRAM,
473 - .gpio_first = 24,
474 - .gpio_last = 39,
475 - }, {
476 - .name = "pci",
477 - .mask = RT2880_GPIO_MODE_PCI,
478 - .gpio_first = 40,
479 - .gpio_last = 71,
480 - }, {0}
481 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
482 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
483 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) };
484 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
485 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
486 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
487 +static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) };
488 +
489 +static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
490 + GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
491 + GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
492 + GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
493 + GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
494 + GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
495 + GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
496 + GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
497 + { 0 }
498 };
499
500 static void rt288x_wdt_reset(void)
501 @@ -69,11 +50,6 @@
502 rt_sysc_w32(t, SYSC_REG_CLKCFG);
503 }
504
505 -struct ralink_pinmux rt_gpio_pinmux = {
506 - .mode = mode_mux,
507 - .wdt_reset = rt288x_wdt_reset,
508 -};
509 -
510 void __init ralink_clk_init(void)
511 {
512 unsigned long cpu_rate, wmac_rate = 40000000;
513 @@ -141,4 +117,6 @@
514 soc_info->mem_base = RT2880_SDRAM_BASE;
515 soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
516 soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
517 +
518 + rt2880_pinmux_data = rt2880_pinmux_data_act;
519 }
520 --- a/arch/mips/ralink/rt305x.c
521 +++ b/arch/mips/ralink/rt305x.c
522 @@ -17,90 +17,76 @@
523 #include <asm/mipsregs.h>
524 #include <asm/mach-ralink/ralink_regs.h>
525 #include <asm/mach-ralink/rt305x.h>
526 +#include <asm/mach-ralink/pinmux.h>
527
528 #include "common.h"
529
530 enum rt305x_soc_type rt305x_soc;
531
532 -static struct ralink_pinmux_grp mode_mux[] = {
533 - {
534 - .name = "i2c",
535 - .mask = RT305X_GPIO_MODE_I2C,
536 - .gpio_first = RT305X_GPIO_I2C_SD,
537 - .gpio_last = RT305X_GPIO_I2C_SCLK,
538 - }, {
539 - .name = "spi",
540 - .mask = RT305X_GPIO_MODE_SPI,
541 - .gpio_first = RT305X_GPIO_SPI_EN,
542 - .gpio_last = RT305X_GPIO_SPI_CLK,
543 - }, {
544 - .name = "uartlite",
545 - .mask = RT305X_GPIO_MODE_UART1,
546 - .gpio_first = RT305X_GPIO_UART1_TXD,
547 - .gpio_last = RT305X_GPIO_UART1_RXD,
548 - }, {
549 - .name = "jtag",
550 - .mask = RT305X_GPIO_MODE_JTAG,
551 - .gpio_first = RT305X_GPIO_JTAG_TDO,
552 - .gpio_last = RT305X_GPIO_JTAG_TDI,
553 - }, {
554 - .name = "mdio",
555 - .mask = RT305X_GPIO_MODE_MDIO,
556 - .gpio_first = RT305X_GPIO_MDIO_MDC,
557 - .gpio_last = RT305X_GPIO_MDIO_MDIO,
558 - }, {
559 - .name = "sdram",
560 - .mask = RT305X_GPIO_MODE_SDRAM,
561 - .gpio_first = RT305X_GPIO_SDRAM_MD16,
562 - .gpio_last = RT305X_GPIO_SDRAM_MD31,
563 - }, {
564 - .name = "rgmii",
565 - .mask = RT305X_GPIO_MODE_RGMII,
566 - .gpio_first = RT305X_GPIO_GE0_TXD0,
567 - .gpio_last = RT305X_GPIO_GE0_RXCLK,
568 - }, {0}
569 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
570 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
571 +static struct rt2880_pmx_func uartf_func[] = {
572 + FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
573 + FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
574 + FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
575 + FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
576 + FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
577 + FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
578 + FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
579 +};
580 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
581 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
582 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
583 +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
584 +static struct rt2880_pmx_func rt5350_cs1_func[] = {
585 + FUNC("spi_cs1", 0, 27, 1),
586 + FUNC("wdg_cs1", 1, 27, 1),
587 +};
588 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
589 +static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
590 +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
591 +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
592 +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
593 +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
594 +
595 +static struct rt2880_pmx_group rt3050_pinmux_data[] = {
596 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
597 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
598 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
599 + RT305X_GPIO_MODE_UART0_SHIFT),
600 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
601 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
602 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
603 + GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
604 + GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
605 + { 0 }
606 +};
607 +
608 +static struct rt2880_pmx_group rt3352_pinmux_data[] = {
609 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
610 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
611 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
612 + RT305X_GPIO_MODE_UART0_SHIFT),
613 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
614 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
615 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
616 + GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
617 + GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
618 + GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
619 + GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
620 + { 0 }
621 };
622
623 -static struct ralink_pinmux_grp uart_mux[] = {
624 - {
625 - .name = "uartf",
626 - .mask = RT305X_GPIO_MODE_UARTF,
627 - .gpio_first = RT305X_GPIO_7,
628 - .gpio_last = RT305X_GPIO_14,
629 - }, {
630 - .name = "pcm uartf",
631 - .mask = RT305X_GPIO_MODE_PCM_UARTF,
632 - .gpio_first = RT305X_GPIO_7,
633 - .gpio_last = RT305X_GPIO_14,
634 - }, {
635 - .name = "pcm i2s",
636 - .mask = RT305X_GPIO_MODE_PCM_I2S,
637 - .gpio_first = RT305X_GPIO_7,
638 - .gpio_last = RT305X_GPIO_14,
639 - }, {
640 - .name = "i2s uartf",
641 - .mask = RT305X_GPIO_MODE_I2S_UARTF,
642 - .gpio_first = RT305X_GPIO_7,
643 - .gpio_last = RT305X_GPIO_14,
644 - }, {
645 - .name = "pcm gpio",
646 - .mask = RT305X_GPIO_MODE_PCM_GPIO,
647 - .gpio_first = RT305X_GPIO_10,
648 - .gpio_last = RT305X_GPIO_14,
649 - }, {
650 - .name = "gpio uartf",
651 - .mask = RT305X_GPIO_MODE_GPIO_UARTF,
652 - .gpio_first = RT305X_GPIO_7,
653 - .gpio_last = RT305X_GPIO_10,
654 - }, {
655 - .name = "gpio i2s",
656 - .mask = RT305X_GPIO_MODE_GPIO_I2S,
657 - .gpio_first = RT305X_GPIO_7,
658 - .gpio_last = RT305X_GPIO_10,
659 - }, {
660 - .name = "gpio",
661 - .mask = RT305X_GPIO_MODE_GPIO,
662 - }, {0}
663 +static struct rt2880_pmx_group rt5350_pinmux_data[] = {
664 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
665 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
666 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
667 + RT305X_GPIO_MODE_UART0_SHIFT),
668 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
669 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
670 + GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
671 + GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
672 + { 0 }
673 };
674
675 static void rt305x_wdt_reset(void)
676 @@ -114,14 +100,6 @@
677 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
678 }
679
680 -struct ralink_pinmux rt_gpio_pinmux = {
681 - .mode = mode_mux,
682 - .uart = uart_mux,
683 - .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
684 - .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
685 - .wdt_reset = rt305x_wdt_reset,
686 -};
687 -
688 static unsigned long rt5350_get_mem_size(void)
689 {
690 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
691 @@ -290,11 +268,14 @@
692 soc_info->mem_base = RT305X_SDRAM_BASE;
693 if (soc_is_rt5350()) {
694 soc_info->mem_size = rt5350_get_mem_size();
695 + rt2880_pinmux_data = rt5350_pinmux_data;
696 } else if (soc_is_rt305x() || soc_is_rt3350()) {
697 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
698 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
699 + rt2880_pinmux_data = rt3050_pinmux_data;
700 } else if (soc_is_rt3352()) {
701 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
702 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
703 + rt2880_pinmux_data = rt3352_pinmux_data;
704 }
705 }
706 --- a/arch/mips/ralink/rt3883.c
707 +++ b/arch/mips/ralink/rt3883.c
708 @@ -17,132 +17,50 @@
709 #include <asm/mipsregs.h>
710 #include <asm/mach-ralink/ralink_regs.h>
711 #include <asm/mach-ralink/rt3883.h>
712 +#include <asm/mach-ralink/pinmux.h>
713
714 #include "common.h"
715
716 -static struct ralink_pinmux_grp mode_mux[] = {
717 - {
718 - .name = "i2c",
719 - .mask = RT3883_GPIO_MODE_I2C,
720 - .gpio_first = RT3883_GPIO_I2C_SD,
721 - .gpio_last = RT3883_GPIO_I2C_SCLK,
722 - }, {
723 - .name = "spi",
724 - .mask = RT3883_GPIO_MODE_SPI,
725 - .gpio_first = RT3883_GPIO_SPI_CS0,
726 - .gpio_last = RT3883_GPIO_SPI_MISO,
727 - }, {
728 - .name = "uartlite",
729 - .mask = RT3883_GPIO_MODE_UART1,
730 - .gpio_first = RT3883_GPIO_UART1_TXD,
731 - .gpio_last = RT3883_GPIO_UART1_RXD,
732 - }, {
733 - .name = "jtag",
734 - .mask = RT3883_GPIO_MODE_JTAG,
735 - .gpio_first = RT3883_GPIO_JTAG_TDO,
736 - .gpio_last = RT3883_GPIO_JTAG_TCLK,
737 - }, {
738 - .name = "mdio",
739 - .mask = RT3883_GPIO_MODE_MDIO,
740 - .gpio_first = RT3883_GPIO_MDIO_MDC,
741 - .gpio_last = RT3883_GPIO_MDIO_MDIO,
742 - }, {
743 - .name = "ge1",
744 - .mask = RT3883_GPIO_MODE_GE1,
745 - .gpio_first = RT3883_GPIO_GE1_TXD0,
746 - .gpio_last = RT3883_GPIO_GE1_RXCLK,
747 - }, {
748 - .name = "ge2",
749 - .mask = RT3883_GPIO_MODE_GE2,
750 - .gpio_first = RT3883_GPIO_GE2_TXD0,
751 - .gpio_last = RT3883_GPIO_GE2_RXCLK,
752 - }, {
753 - .name = "pci",
754 - .mask = RT3883_GPIO_MODE_PCI,
755 - .gpio_first = RT3883_GPIO_PCI_AD0,
756 - .gpio_last = RT3883_GPIO_PCI_AD31,
757 - }, {
758 - .name = "lna a",
759 - .mask = RT3883_GPIO_MODE_LNA_A,
760 - .gpio_first = RT3883_GPIO_LNA_PE_A0,
761 - .gpio_last = RT3883_GPIO_LNA_PE_A2,
762 - }, {
763 - .name = "lna g",
764 - .mask = RT3883_GPIO_MODE_LNA_G,
765 - .gpio_first = RT3883_GPIO_LNA_PE_G0,
766 - .gpio_last = RT3883_GPIO_LNA_PE_G2,
767 - }, {0}
768 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
769 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
770 +static struct rt2880_pmx_func uartf_func[] = {
771 + FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
772 + FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
773 + FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
774 + FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
775 + FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
776 + FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
777 + FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
778 };
779 -
780 -static struct ralink_pinmux_grp uart_mux[] = {
781 - {
782 - .name = "uartf",
783 - .mask = RT3883_GPIO_MODE_UARTF,
784 - .gpio_first = RT3883_GPIO_7,
785 - .gpio_last = RT3883_GPIO_14,
786 - }, {
787 - .name = "pcm uartf",
788 - .mask = RT3883_GPIO_MODE_PCM_UARTF,
789 - .gpio_first = RT3883_GPIO_7,
790 - .gpio_last = RT3883_GPIO_14,
791 - }, {
792 - .name = "pcm i2s",
793 - .mask = RT3883_GPIO_MODE_PCM_I2S,
794 - .gpio_first = RT3883_GPIO_7,
795 - .gpio_last = RT3883_GPIO_14,
796 - }, {
797 - .name = "i2s uartf",
798 - .mask = RT3883_GPIO_MODE_I2S_UARTF,
799 - .gpio_first = RT3883_GPIO_7,
800 - .gpio_last = RT3883_GPIO_14,
801 - }, {
802 - .name = "pcm gpio",
803 - .mask = RT3883_GPIO_MODE_PCM_GPIO,
804 - .gpio_first = RT3883_GPIO_11,
805 - .gpio_last = RT3883_GPIO_14,
806 - }, {
807 - .name = "gpio uartf",
808 - .mask = RT3883_GPIO_MODE_GPIO_UARTF,
809 - .gpio_first = RT3883_GPIO_7,
810 - .gpio_last = RT3883_GPIO_10,
811 - }, {
812 - .name = "gpio i2s",
813 - .mask = RT3883_GPIO_MODE_GPIO_I2S,
814 - .gpio_first = RT3883_GPIO_7,
815 - .gpio_last = RT3883_GPIO_10,
816 - }, {
817 - .name = "gpio",
818 - .mask = RT3883_GPIO_MODE_GPIO,
819 - }, {0}
820 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
821 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
822 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
823 +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
824 +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
825 +static struct rt2880_pmx_func pci_func[] = {
826 + FUNC("pci-dev", 0, 40, 32),
827 + FUNC("pci-host2", 1, 40, 32),
828 + FUNC("pci-host1", 2, 40, 32),
829 + FUNC("pci-fnc", 3, 40, 32)
830 };
831 +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
832 +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
833
834 -static struct ralink_pinmux_grp pci_mux[] = {
835 - {
836 - .name = "pci-dev",
837 - .mask = 0,
838 - .gpio_first = RT3883_GPIO_PCI_AD0,
839 - .gpio_last = RT3883_GPIO_PCI_AD31,
840 - }, {
841 - .name = "pci-host2",
842 - .mask = 1,
843 - .gpio_first = RT3883_GPIO_PCI_AD0,
844 - .gpio_last = RT3883_GPIO_PCI_AD31,
845 - }, {
846 - .name = "pci-host1",
847 - .mask = 2,
848 - .gpio_first = RT3883_GPIO_PCI_AD0,
849 - .gpio_last = RT3883_GPIO_PCI_AD31,
850 - }, {
851 - .name = "pci-fnc",
852 - .mask = 3,
853 - .gpio_first = RT3883_GPIO_PCI_AD0,
854 - .gpio_last = RT3883_GPIO_PCI_AD31,
855 - }, {
856 - .name = "pci-gpio",
857 - .mask = 7,
858 - .gpio_first = RT3883_GPIO_PCI_AD0,
859 - .gpio_last = RT3883_GPIO_PCI_AD31,
860 - }, {0}
861 +static struct rt2880_pmx_group rt3883_pinmux_data[] = {
862 + GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
863 + GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
864 + GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
865 + RT3883_GPIO_MODE_UART0_SHIFT),
866 + GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
867 + GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
868 + GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
869 + GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
870 + GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
871 + GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
872 + RT3883_GPIO_MODE_PCI_SHIFT),
873 + GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
874 + GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
875 + { 0 }
876 };
877
878 static void rt3883_wdt_reset(void)
879 @@ -155,17 +73,6 @@
880 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
881 }
882
883 -struct ralink_pinmux rt_gpio_pinmux = {
884 - .mode = mode_mux,
885 - .uart = uart_mux,
886 - .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
887 - .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
888 - .wdt_reset = rt3883_wdt_reset,
889 - .pci = pci_mux,
890 - .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
891 - .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
892 -};
893 -
894 void __init ralink_clk_init(void)
895 {
896 unsigned long cpu_rate, sys_rate;
897 @@ -244,4 +151,6 @@
898 soc_info->mem_base = RT3883_SDRAM_BASE;
899 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
900 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
901 +
902 + rt2880_pinmux_data = rt3883_pinmux_data;
903 }
904 --- a/drivers/pinctrl/Kconfig
905 +++ b/drivers/pinctrl/Kconfig
906 @@ -103,6 +103,11 @@
907 select PINMUX
908 select PINCONF
909
910 +config PINCTRL_RT2880
911 + bool
912 + depends on RALINK
913 + select PINMUX
914 +
915 config PINCTRL_FALCON
916 bool
917 depends on SOC_FALCON
918 --- a/drivers/pinctrl/Makefile
919 +++ b/drivers/pinctrl/Makefile
920 @@ -20,6 +20,7 @@
921 obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
922 obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
923 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
924 +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
925 obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
926 obj-$(CONFIG_PINCTRL_SIRF) += sirf/
927 obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
928 --- /dev/null
929 +++ b/drivers/pinctrl/pinctrl-rt2880.c
930 @@ -0,0 +1,474 @@
931 +/*
932 + * linux/drivers/pinctrl/pinctrl-rt2880.c
933 + *
934 + * This program is free software; you can redistribute it and/or modify
935 + * it under the terms of the GNU General Public License version 2 as
936 + * publishhed by the Free Software Foundation.
937 + *
938 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
939 + */
940 +
941 +#include <linux/module.h>
942 +#include <linux/device.h>
943 +#include <linux/io.h>
944 +#include <linux/platform_device.h>
945 +#include <linux/slab.h>
946 +#include <linux/of.h>
947 +#include <linux/pinctrl/pinctrl.h>
948 +#include <linux/pinctrl/pinconf.h>
949 +#include <linux/pinctrl/pinmux.h>
950 +#include <linux/pinctrl/consumer.h>
951 +#include <linux/pinctrl/machine.h>
952 +
953 +#include <asm/mach-ralink/ralink_regs.h>
954 +#include <asm/mach-ralink/pinmux.h>
955 +#include <asm/mach-ralink/mt7620.h>
956 +
957 +#include "core.h"
958 +
959 +#define SYSC_REG_GPIO_MODE 0x60
960 +#define SYSC_REG_GPIO_MODE2 0x64
961 +
962 +struct rt2880_priv {
963 + struct device *dev;
964 +
965 + struct pinctrl_pin_desc *pads;
966 + struct pinctrl_desc *desc;
967 +
968 + struct rt2880_pmx_func **func;
969 + int func_count;
970 +
971 + struct rt2880_pmx_group *groups;
972 + const char **group_names;
973 + int group_count;
974 +
975 + uint8_t *gpio;
976 + int max_pins;
977 +};
978 +
979 +struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
980 +
981 +static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
982 +{
983 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
984 +
985 + return p->group_count;
986 +}
987 +
988 +static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
989 + unsigned group)
990 +{
991 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
992 +
993 + if (group >= p->group_count)
994 + return NULL;
995 +
996 + return p->group_names[group];
997 +}
998 +
999 +static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
1000 + unsigned group,
1001 + const unsigned **pins,
1002 + unsigned *num_pins)
1003 +{
1004 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1005 +
1006 + if (group >= p->group_count)
1007 + return -EINVAL;
1008 +
1009 + *pins = p->groups[group].func[0].pins;
1010 + *num_pins = p->groups[group].func[0].pin_count;
1011 +
1012 + return 0;
1013 +}
1014 +
1015 +static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
1016 + struct pinctrl_map *map, unsigned num_maps)
1017 +{
1018 + int i;
1019 +
1020 + for (i = 0; i < num_maps; i++)
1021 + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
1022 + map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
1023 + kfree(map[i].data.configs.configs);
1024 + kfree(map);
1025 +}
1026 +
1027 +static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
1028 + struct seq_file *s,
1029 + unsigned offset)
1030 +{
1031 + seq_printf(s, "ralink pio");
1032 +}
1033 +
1034 +static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
1035 + struct device_node *np,
1036 + struct pinctrl_map **map)
1037 +{
1038 + const char *function;
1039 + int func = of_property_read_string(np, "ralink,function", &function);
1040 + int grps = of_property_count_strings(np, "ralink,group");
1041 + int i;
1042 +
1043 + if (func || !grps)
1044 + return;
1045 +
1046 + for (i = 0; i < grps; i++) {
1047 + const char *group;
1048 +
1049 + of_property_read_string_index(np, "ralink,group", i, &group);
1050 +
1051 + (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1052 + (*map)->name = function;
1053 + (*map)->data.mux.group = group;
1054 + (*map)->data.mux.function = function;
1055 + (*map)++;
1056 + }
1057 +}
1058 +
1059 +static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
1060 + struct device_node *np_config,
1061 + struct pinctrl_map **map,
1062 + unsigned *num_maps)
1063 +{
1064 + int max_maps = 0;
1065 + struct pinctrl_map *tmp;
1066 + struct device_node *np;
1067 +
1068 + for_each_child_of_node(np_config, np) {
1069 + int ret = of_property_count_strings(np, "ralink,group");
1070 +
1071 + if (ret >= 0)
1072 + max_maps += ret;
1073 + }
1074 +
1075 + if (!max_maps)
1076 + return max_maps;
1077 +
1078 + *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
1079 + if (!*map)
1080 + return -ENOMEM;
1081 +
1082 + tmp = *map;
1083 +
1084 + for_each_child_of_node(np_config, np)
1085 + rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
1086 + *num_maps = max_maps;
1087 +
1088 + return 0;
1089 +}
1090 +
1091 +static const struct pinctrl_ops rt2880_pctrl_ops = {
1092 + .get_groups_count = rt2880_get_group_count,
1093 + .get_group_name = rt2880_get_group_name,
1094 + .get_group_pins = rt2880_get_group_pins,
1095 + .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
1096 + .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
1097 + .dt_free_map = rt2880_pinctrl_dt_free_map,
1098 +};
1099 +
1100 +static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
1101 +{
1102 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1103 +
1104 + return p->func_count;
1105 +}
1106 +
1107 +static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
1108 + unsigned func)
1109 +{
1110 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1111 +
1112 + return p->func[func]->name;
1113 +}
1114 +
1115 +static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
1116 + unsigned func,
1117 + const char * const **groups,
1118 + unsigned * const num_groups)
1119 +{
1120 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1121 +
1122 + if (p->func[func]->group_count == 1)
1123 + *groups = &p->group_names[p->func[func]->groups[0]];
1124 + else
1125 + *groups = p->group_names;
1126 +
1127 + *num_groups = p->func[func]->group_count;
1128 +
1129 + return 0;
1130 +}
1131 +
1132 +static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
1133 + unsigned func,
1134 + unsigned group)
1135 +{
1136 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1137 + u32 mode = 0;
1138 + u32 reg = SYSC_REG_GPIO_MODE;
1139 + int i;
1140 + int shift;
1141 +
1142 + /* dont allow double use */
1143 + if (p->groups[group].enabled) {
1144 + dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
1145 + return -EBUSY;
1146 + }
1147 +
1148 + p->groups[group].enabled = 1;
1149 + p->func[func]->enabled = 1;
1150 +
1151 + shift = p->groups[group].shift;
1152 + if (shift >= 32) {
1153 + shift -= 32;
1154 + reg = SYSC_REG_GPIO_MODE2;
1155 + }
1156 + mode = rt_sysc_r32(reg);
1157 + mode &= ~(p->groups[group].mask << shift);
1158 +
1159 + /* mark the pins as gpio */
1160 + for (i = 0; i < p->groups[group].func[0].pin_count; i++)
1161 + p->gpio[p->groups[group].func[0].pins[i]] = 1;
1162 +
1163 + /* function 0 is gpio and needs special handling */
1164 + if (func == 0) {
1165 + mode |= p->groups[group].gpio << shift;
1166 + } else {
1167 + for (i = 0; i < p->func[func]->pin_count; i++)
1168 + p->gpio[p->func[func]->pins[i]] = 0;
1169 + mode |= p->func[func]->value << shift;
1170 + }
1171 + rt_sysc_w32(mode, reg);
1172 +
1173 + return 0;
1174 +}
1175 +
1176 +static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
1177 + struct pinctrl_gpio_range *range,
1178 + unsigned pin)
1179 +{
1180 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
1181 +
1182 + if (!p->gpio[pin]) {
1183 + dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
1184 + return -EINVAL;
1185 + }
1186 +
1187 + return 0;
1188 +}
1189 +
1190 +static const struct pinmux_ops rt2880_pmx_group_ops = {
1191 + .get_functions_count = rt2880_pmx_func_count,
1192 + .get_function_name = rt2880_pmx_func_name,
1193 + .get_function_groups = rt2880_pmx_group_get_groups,
1194 + .set_mux = rt2880_pmx_group_enable,
1195 + .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
1196 +};
1197 +
1198 +static struct pinctrl_desc rt2880_pctrl_desc = {
1199 + .owner = THIS_MODULE,
1200 + .name = "rt2880-pinmux",
1201 + .pctlops = &rt2880_pctrl_ops,
1202 + .pmxops = &rt2880_pmx_group_ops,
1203 +};
1204 +
1205 +static struct rt2880_pmx_func gpio_func = {
1206 + .name = "gpio",
1207 +};
1208 +
1209 +static int rt2880_pinmux_index(struct rt2880_priv *p)
1210 +{
1211 + struct rt2880_pmx_func **f;
1212 + struct rt2880_pmx_group *mux = p->groups;
1213 + int i, j, c = 0;
1214 +
1215 + /* count the mux functions */
1216 + while (mux->name) {
1217 + p->group_count++;
1218 + mux++;
1219 + }
1220 +
1221 + /* allocate the group names array needed by the gpio function */
1222 + p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
1223 + if (!p->group_names)
1224 + return -1;
1225 +
1226 + for (i = 0; i < p->group_count; i++) {
1227 + p->group_names[i] = p->groups[i].name;
1228 + p->func_count += p->groups[i].func_count;
1229 + }
1230 +
1231 + /* we have a dummy function[0] for gpio */
1232 + p->func_count++;
1233 +
1234 + /* allocate our function and group mapping index buffers */
1235 + f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
1236 + gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
1237 + if (!f || !gpio_func.groups)
1238 + return -1;
1239 +
1240 + /* add a backpointer to the function so it knows its group */
1241 + gpio_func.group_count = p->group_count;
1242 + for (i = 0; i < gpio_func.group_count; i++)
1243 + gpio_func.groups[i] = i;
1244 +
1245 + f[c] = &gpio_func;
1246 + c++;
1247 +
1248 + /* add remaining functions */
1249 + for (i = 0; i < p->group_count; i++) {
1250 + for (j = 0; j < p->groups[i].func_count; j++) {
1251 + f[c] = &p->groups[i].func[j];
1252 + f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
1253 + f[c]->groups[0] = i;
1254 + f[c]->group_count = 1;
1255 + c++;
1256 + }
1257 + }
1258 + return 0;
1259 +}
1260 +
1261 +static int rt2880_pinmux_pins(struct rt2880_priv *p)
1262 +{
1263 + int i, j;
1264 +
1265 + /* loop over the functions and initialize the pins array. also work out the highest pin used */
1266 + for (i = 0; i < p->func_count; i++) {
1267 + int pin;
1268 +
1269 + if (!p->func[i]->pin_count)
1270 + continue;
1271 +
1272 + p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
1273 + for (j = 0; j < p->func[i]->pin_count; j++)
1274 + p->func[i]->pins[j] = p->func[i]->pin_first + j;
1275 +
1276 + pin = p->func[i]->pin_first + p->func[i]->pin_count;
1277 + if (pin > p->max_pins)
1278 + p->max_pins = pin;
1279 + }
1280 +
1281 + /* the buffer that tells us which pins are gpio */
1282 + p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
1283 + GFP_KERNEL);
1284 + /* the pads needed to tell pinctrl about our pins */
1285 + p->pads = devm_kzalloc(p->dev,
1286 + sizeof(struct pinctrl_pin_desc) * p->max_pins,
1287 + GFP_KERNEL);
1288 + if (!p->pads || !p->gpio ) {
1289 + dev_err(p->dev, "Failed to allocate gpio data\n");
1290 + return -ENOMEM;
1291 + }
1292 +
1293 + memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
1294 + for (i = 0; i < p->func_count; i++) {
1295 + if (!p->func[i]->pin_count)
1296 + continue;
1297 +
1298 + for (j = 0; j < p->func[i]->pin_count; j++)
1299 + p->gpio[p->func[i]->pins[j]] = 0;
1300 + }
1301 +
1302 + /* pin 0 is always a gpio */
1303 + p->gpio[0] = 1;
1304 +
1305 + /* set the pads */
1306 + for (i = 0; i < p->max_pins; i++) {
1307 + /* strlen("ioXY") + 1 = 5 */
1308 + char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
1309 +
1310 + if (!name) {
1311 + dev_err(p->dev, "Failed to allocate pad name\n");
1312 + return -ENOMEM;
1313 + }
1314 + snprintf(name, 5, "io%d", i);
1315 + p->pads[i].number = i;
1316 + p->pads[i].name = name;
1317 + }
1318 + p->desc->pins = p->pads;
1319 + p->desc->npins = p->max_pins;
1320 +
1321 + return 0;
1322 +}
1323 +
1324 +static int rt2880_pinmux_probe(struct platform_device *pdev)
1325 +{
1326 + struct rt2880_priv *p;
1327 + struct pinctrl_dev *dev;
1328 + struct device_node *np;
1329 +
1330 + if (!rt2880_pinmux_data)
1331 + return -ENOSYS;
1332 +
1333 + /* setup the private data */
1334 + p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
1335 + if (!p)
1336 + return -ENOMEM;
1337 +
1338 + p->dev = &pdev->dev;
1339 + p->desc = &rt2880_pctrl_desc;
1340 + p->groups = rt2880_pinmux_data;
1341 + platform_set_drvdata(pdev, p);
1342 +
1343 + /* init the device */
1344 + if (rt2880_pinmux_index(p)) {
1345 + dev_err(&pdev->dev, "failed to load index\n");
1346 + return -EINVAL;
1347 + }
1348 + if (rt2880_pinmux_pins(p)) {
1349 + dev_err(&pdev->dev, "failed to load pins\n");
1350 + return -EINVAL;
1351 + }
1352 + dev = pinctrl_register(p->desc, &pdev->dev, p);
1353 + if (IS_ERR(dev))
1354 + return PTR_ERR(dev);
1355 +
1356 + /* finalize by adding gpio ranges for enables gpio controllers */
1357 + for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
1358 + const __be32 *ngpio, *gpiobase;
1359 + struct pinctrl_gpio_range *range;
1360 + char *name;
1361 +
1362 + if (!of_device_is_available(np))
1363 + continue;
1364 +
1365 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
1366 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
1367 + if (!ngpio || !gpiobase) {
1368 + dev_err(&pdev->dev, "failed to load chip info\n");
1369 + return -EINVAL;
1370 + }
1371 +
1372 + range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
1373 + range->name = name = (char *) &range[1];
1374 + sprintf(name, "pio");
1375 + range->npins = __be32_to_cpu(*ngpio);
1376 + range->base = __be32_to_cpu(*gpiobase);
1377 + range->pin_base = range->base;
1378 + pinctrl_add_gpio_range(dev, range);
1379 + }
1380 +
1381 + return 0;
1382 +}
1383 +
1384 +static const struct of_device_id rt2880_pinmux_match[] = {
1385 + { .compatible = "ralink,rt2880-pinmux" },
1386 + {},
1387 +};
1388 +MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
1389 +
1390 +static struct platform_driver rt2880_pinmux_driver = {
1391 + .probe = rt2880_pinmux_probe,
1392 + .driver = {
1393 + .name = "rt2880-pinmux",
1394 + .owner = THIS_MODULE,
1395 + .of_match_table = rt2880_pinmux_match,
1396 + },
1397 +};
1398 +
1399 +int __init rt2880_pinmux_init(void)
1400 +{
1401 + return platform_driver_register(&rt2880_pinmux_driver);
1402 +}
1403 +
1404 +core_initcall_sync(rt2880_pinmux_init);
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