target/linux/ramips/patches-3.18/0050-SPI-ralink-add-Ralink-SoC-spi-driver.patch

   1 From fc006d0622ab8c43086b2c9018c03012db332033 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 11:15:12 +0100
   4 Subject: [PATCH 50/57] SPI: ralink: add Ralink SoC spi driver
   5
   6 Add the driver needed to make SPI work on Ralink SoC.
   7
   8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   9 Acked-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  drivers/spi/Kconfig      |    6 +
  12  drivers/spi/Makefile     |    1 +
  13  drivers/spi/spi-rt2880.c |  432 ++++++++++++++++++++++++++++++++++++++++++++++
  14  3 files changed, 439 insertions(+)
  15  create mode 100644 drivers/spi/spi-rt2880.c
  16
  17 --- a/drivers/spi/Kconfig
  18 +++ b/drivers/spi/Kconfig
  19 @@ -433,6 +433,12 @@ config SPI_QUP
  20           This driver can also be built as a module.  If so, the module
  21           will be called spi_qup.
  22
  23 +config SPI_RT2880
  24 +       tristate "Ralink RT288x SPI Controller"
  25 +       depends on RALINK
  26 +       help
  27 +         This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  28 +
  29  config SPI_S3C24XX
  30         tristate "Samsung S3C24XX series SPI"
  31         depends on ARCH_S3C24XX
  32 --- a/drivers/spi/Makefile
  33 +++ b/drivers/spi/Makefile
  34 @@ -65,6 +65,7 @@ obj-$(CONFIG_SPI_PXA2XX_PCI)          += spi-pxa
  35  obj-$(CONFIG_SPI_QUP)                  += spi-qup.o
  36  obj-$(CONFIG_SPI_ROCKCHIP)             += spi-rockchip.o
  37  obj-$(CONFIG_SPI_RSPI)                 += spi-rspi.o
  38 +obj-$(CONFIG_SPI_RT2880)               += spi-rt2880.o
  39  obj-$(CONFIG_SPI_S3C24XX)              += spi-s3c24xx-hw.o
  40  spi-s3c24xx-hw-y                       := spi-s3c24xx.o
  41  spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
  42 --- /dev/null
  43 +++ b/drivers/spi/spi-rt2880.c
  44 @@ -0,0 +1,432 @@
  45 +/*
  46 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
  47 + *
  48 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  49 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  50 + *
  51 + * Some parts are based on spi-orion.c:
  52 + *   Author: Shadi Ammouri <shadi@marvell.com>
  53 + *   Copyright (C) 2007-2008 Marvell Ltd.
  54 + *
  55 + * This program is free software; you can redistribute it and/or modify
  56 + * it under the terms of the GNU General Public License version 2 as
  57 + * published by the Free Software Foundation.
  58 + */
  59 +
  60 +#include <linux/init.h>
  61 +#include <linux/module.h>
  62 +#include <linux/clk.h>
  63 +#include <linux/err.h>
  64 +#include <linux/delay.h>
  65 +#include <linux/io.h>
  66 +#include <linux/reset.h>
  67 +#include <linux/spi/spi.h>
  68 +#include <linux/platform_device.h>
  69 +
  70 +#define DRIVER_NAME                    "spi-rt2880"
  71 +/* only one slave is supported*/
  72 +#define RALINK_NUM_CHIPSELECTS         1
  73 +/* in usec */
  74 +#define RALINK_SPI_WAIT_MAX_LOOP       2000
  75 +
  76 +#define RAMIPS_SPI_STAT                        0x00
  77 +#define RAMIPS_SPI_CFG                 0x10
  78 +#define RAMIPS_SPI_CTL                 0x14
  79 +#define RAMIPS_SPI_DATA                        0x20
  80 +#define RAMIPS_SPI_FIFO_STAT           0x38
  81 +
  82 +/* SPISTAT register bit field */
  83 +#define SPISTAT_BUSY                   BIT(0)
  84 +
  85 +/* SPICFG register bit field */
  86 +#define SPICFG_LSBFIRST                        0
  87 +#define SPICFG_MSBFIRST                        BIT(8)
  88 +#define SPICFG_SPICLKPOL               BIT(6)
  89 +#define SPICFG_RXCLKEDGE_FALLING       BIT(5)
  90 +#define SPICFG_TXCLKEDGE_FALLING       BIT(4)
  91 +#define SPICFG_SPICLK_PRESCALE_MASK    0x7
  92 +#define SPICFG_SPICLK_DIV2             0
  93 +#define SPICFG_SPICLK_DIV4             1
  94 +#define SPICFG_SPICLK_DIV8             2
  95 +#define SPICFG_SPICLK_DIV16            3
  96 +#define SPICFG_SPICLK_DIV32            4
  97 +#define SPICFG_SPICLK_DIV64            5
  98 +#define SPICFG_SPICLK_DIV128           6
  99 +#define SPICFG_SPICLK_DISABLE          7
 100 +
 101 +/* SPICTL register bit field */
 102 +#define SPICTL_HIZSDO                  BIT(3)
 103 +#define SPICTL_STARTWR                 BIT(2)
 104 +#define SPICTL_STARTRD                 BIT(1)
 105 +#define SPICTL_SPIENA                  BIT(0)
 106 +
 107 +/* SPIFIFOSTAT register bit field */
 108 +#define SPIFIFOSTAT_TXFULL             BIT(17)
 109 +
 110 +struct rt2880_spi {
 111 +       struct spi_master       *master;
 112 +       void __iomem            *base;
 113 +       unsigned int            sys_freq;
 114 +       unsigned int            speed;
 115 +       struct clk              *clk;
 116 +       spinlock_t              lock;
 117 +};
 118 +
 119 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
 120 +{
 121 +       return spi_master_get_devdata(spi->master);
 122 +}
 123 +
 124 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
 125 +{
 126 +       return ioread32(rs->base + reg);
 127 +}
 128 +
 129 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, u32 val)
 130 +{
 131 +       iowrite32(val, rs->base + reg);
 132 +}
 133 +
 134 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 135 +{
 136 +       void __iomem *addr = rs->base + reg;
 137 +       unsigned long flags;
 138 +       u32 val;
 139 +
 140 +       spin_lock_irqsave(&rs->lock, flags);
 141 +       val = ioread32(addr);
 142 +       val |= mask;
 143 +       iowrite32(val, addr);
 144 +       spin_unlock_irqrestore(&rs->lock, flags);
 145 +}
 146 +
 147 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 148 +{
 149 +       void __iomem *addr = rs->base + reg;
 150 +       unsigned long flags;
 151 +       u32 val;
 152 +
 153 +       spin_lock_irqsave(&rs->lock, flags);
 154 +       val = ioread32(addr);
 155 +       val &= ~mask;
 156 +       iowrite32(val, addr);
 157 +       spin_unlock_irqrestore(&rs->lock, flags);
 158 +}
 159 +
 160 +static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 161 +{
 162 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 163 +       u32 rate;
 164 +       u32 prescale;
 165 +       u32 reg;
 166 +
 167 +       dev_dbg(&spi->dev, "speed:%u\n", speed);
 168 +
 169 +       /*
 170 +        * the supported rates are: 2, 4, 8, ... 128
 171 +        * round up as we look for equal or less speed
 172 +        */
 173 +       rate = DIV_ROUND_UP(rs->sys_freq, speed);
 174 +       dev_dbg(&spi->dev, "rate-1:%u\n", rate);
 175 +       rate = roundup_pow_of_two(rate);
 176 +       dev_dbg(&spi->dev, "rate-2:%u\n", rate);
 177 +
 178 +       /* check if requested speed is too small */
 179 +       if (rate > 128)
 180 +               return -EINVAL;
 181 +
 182 +       if (rate < 2)
 183 +               rate = 2;
 184 +
 185 +       /* Convert the rate to SPI clock divisor value. */
 186 +       prescale = ilog2(rate / 2);
 187 +       dev_dbg(&spi->dev, "prescale:%u\n", prescale);
 188 +
 189 +       reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
 190 +       reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
 191 +       rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
 192 +       rs->speed = speed;
 193 +       return 0;
 194 +}
 195 +
 196 +/*
 197 + * called only when no transfer is active on the bus
 198 + */
 199 +static int
 200 +rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 201 +{
 202 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 203 +       unsigned int speed = spi->max_speed_hz;
 204 +       int rc;
 205 +
 206 +       if ((t != NULL) && t->speed_hz)
 207 +               speed = t->speed_hz;
 208 +
 209 +       if (rs->speed != speed) {
 210 +               dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
 211 +               rc = rt2880_spi_baudrate_set(spi, speed);
 212 +               if (rc)
 213 +                       return rc;
 214 +       }
 215 +
 216 +       return 0;
 217 +}
 218 +
 219 +static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
 220 +{
 221 +       if (enable)
 222 +               rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 223 +       else
 224 +               rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 225 +}
 226 +
 227 +static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
 228 +{
 229 +       int i;
 230 +
 231 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 232 +               u32 status;
 233 +
 234 +               status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
 235 +               if ((status & SPISTAT_BUSY) == 0)
 236 +                       return 0;
 237 +
 238 +               cpu_relax();
 239 +               udelay(1);
 240 +       }
 241 +
 242 +       return -ETIMEDOUT;
 243 +}
 244 +
 245 +static unsigned int
 246 +rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 247 +{
 248 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 249 +       unsigned count = 0;
 250 +       u8 *rx = xfer->rx_buf;
 251 +       const u8 *tx = xfer->tx_buf;
 252 +       int err;
 253 +
 254 +       dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
 255 +                 (tx != NULL) ? "tx" : "  ",
 256 +                 (rx != NULL) ? "rx" : "  ");
 257 +
 258 +       if (tx) {
 259 +               for (count = 0; count < xfer->len; count++) {
 260 +                       rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
 261 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
 262 +                       err = rt2880_spi_wait_till_ready(rs);
 263 +                       if (err) {
 264 +                               dev_err(&spi->dev, "TX failed, err=%d\n", err);
 265 +                               goto out;
 266 +                       }
 267 +               }
 268 +       }
 269 +
 270 +       if (rx) {
 271 +               for (count = 0; count < xfer->len; count++) {
 272 +                       rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
 273 +                       err = rt2880_spi_wait_till_ready(rs);
 274 +                       if (err) {
 275 +                               dev_err(&spi->dev, "RX failed, err=%d\n", err);
 276 +                               goto out;
 277 +                       }
 278 +                       rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
 279 +               }
 280 +       }
 281 +
 282 +out:
 283 +       return count;
 284 +}
 285 +
 286 +static int rt2880_spi_transfer_one_message(struct spi_master *master,
 287 +                                          struct spi_message *m)
 288 +{
 289 +       struct rt2880_spi *rs = spi_master_get_devdata(master);
 290 +       struct spi_device *spi = m->spi;
 291 +       struct spi_transfer *t = NULL;
 292 +       int par_override = 0;
 293 +       int status = 0;
 294 +       int cs_active = 0;
 295 +
 296 +       /* Load defaults */
 297 +       status = rt2880_spi_setup_transfer(spi, NULL);
 298 +       if (status < 0)
 299 +               goto msg_done;
 300 +
 301 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 302 +               if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 303 +                       dev_err(&spi->dev,
 304 +                               "message rejected: invalid transfer data buffers\n");
 305 +                       status = -EIO;
 306 +                       goto msg_done;
 307 +               }
 308 +
 309 +               if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
 310 +                       dev_err(&spi->dev,
 311 +                               "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
 312 +                               (rs->sys_freq / 128), t->speed_hz);
 313 +                       status = -EIO;
 314 +                       goto msg_done;
 315 +               }
 316 +
 317 +               if (par_override || t->speed_hz || t->bits_per_word) {
 318 +                       par_override = 1;
 319 +                       status = rt2880_spi_setup_transfer(spi, t);
 320 +                       if (status < 0)
 321 +                               goto msg_done;
 322 +                       if (!t->speed_hz && !t->bits_per_word)
 323 +                               par_override = 0;
 324 +               }
 325 +
 326 +               if (!cs_active) {
 327 +                       rt2880_spi_set_cs(rs, 1);
 328 +                       cs_active = 1;
 329 +               }
 330 +
 331 +               if (t->len)
 332 +                       m->actual_length += rt2880_spi_write_read(spi, t);
 333 +
 334 +               if (t->delay_usecs)
 335 +                       udelay(t->delay_usecs);
 336 +
 337 +               if (t->cs_change) {
 338 +                       rt2880_spi_set_cs(rs, 0);
 339 +                       cs_active = 0;
 340 +               }
 341 +       }
 342 +
 343 +msg_done:
 344 +       if (cs_active)
 345 +               rt2880_spi_set_cs(rs, 0);
 346 +
 347 +       m->status = status;
 348 +       spi_finalize_current_message(master);
 349 +
 350 +       return 0;
 351 +}
 352 +
 353 +static int rt2880_spi_setup(struct spi_device *spi)
 354 +{
 355 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 356 +
 357 +       if ((spi->max_speed_hz == 0) ||
 358 +           (spi->max_speed_hz > (rs->sys_freq / 2)))
 359 +               spi->max_speed_hz = (rs->sys_freq / 2);
 360 +
 361 +       if (spi->max_speed_hz < (rs->sys_freq / 128)) {
 362 +               dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
 363 +                       spi->max_speed_hz);
 364 +               return -EINVAL;
 365 +       }
 366 +
 367 +       /*
 368 +        * baudrate & width will be set rt2880_spi_setup_transfer
 369 +        */
 370 +       return 0;
 371 +}
 372 +
 373 +static void rt2880_spi_reset(struct rt2880_spi *rs)
 374 +{
 375 +       rt2880_spi_write(rs, RAMIPS_SPI_CFG,
 376 +                        SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
 377 +                        SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
 378 +       rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 379 +}
 380 +
 381 +static int rt2880_spi_probe(struct platform_device *pdev)
 382 +{
 383 +       struct spi_master *master;
 384 +       struct rt2880_spi *rs;
 385 +       unsigned long flags;
 386 +       void __iomem *base;
 387 +       struct resource *r;
 388 +       int status = 0;
 389 +       struct clk *clk;
 390 +
 391 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 392 +       base = devm_ioremap_resource(&pdev->dev, r);
 393 +       if (IS_ERR(base))
 394 +               return PTR_ERR(base);
 395 +
 396 +       clk = devm_clk_get(&pdev->dev, NULL);
 397 +       if (IS_ERR(clk)) {
 398 +               dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
 399 +                       status);
 400 +               return PTR_ERR(clk);
 401 +       }
 402 +
 403 +       status = clk_prepare_enable(clk);
 404 +       if (status)
 405 +               return status;
 406 +
 407 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 408 +       if (master == NULL) {
 409 +               dev_dbg(&pdev->dev, "master allocation failed\n");
 410 +               return -ENOMEM;
 411 +       }
 412 +
 413 +       /* we support only mode 0, and no options */
 414 +       master->mode_bits = 0;
 415 +
 416 +       master->setup = rt2880_spi_setup;
 417 +       master->transfer_one_message = rt2880_spi_transfer_one_message;
 418 +       master->num_chipselect = RALINK_NUM_CHIPSELECTS;
 419 +       master->bits_per_word_mask = SPI_BPW_MASK(8);
 420 +       master->dev.of_node = pdev->dev.of_node;
 421 +
 422 +       dev_set_drvdata(&pdev->dev, master);
 423 +
 424 +       rs = spi_master_get_devdata(master);
 425 +       rs->base = base;
 426 +       rs->clk = clk;
 427 +       rs->master = master;
 428 +       rs->sys_freq = clk_get_rate(rs->clk);
 429 +       dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 430 +       spin_lock_irqsave(&rs->lock, flags);
 431 +
 432 +       device_reset(&pdev->dev);
 433 +
 434 +       rt2880_spi_reset(rs);
 435 +
 436 +       return spi_register_master(master);
 437 +}
 438 +
 439 +static int rt2880_spi_remove(struct platform_device *pdev)
 440 +{
 441 +       struct spi_master *master;
 442 +       struct rt2880_spi *rs;
 443 +
 444 +       master = dev_get_drvdata(&pdev->dev);
 445 +       rs = spi_master_get_devdata(master);
 446 +
 447 +       clk_disable(rs->clk);
 448 +       spi_unregister_master(master);
 449 +
 450 +       return 0;
 451 +}
 452 +
 453 +MODULE_ALIAS("platform:" DRIVER_NAME);
 454 +
 455 +static const struct of_device_id rt2880_spi_match[] = {
 456 +       { .compatible = "ralink,rt2880-spi" },
 457 +       {},
 458 +};
 459 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 460 +
 461 +static struct platform_driver rt2880_spi_driver = {
 462 +       .driver = {
 463 +               .name = DRIVER_NAME,
 464 +               .owner = THIS_MODULE,
 465 +               .of_match_table = rt2880_spi_match,
 466 +       },
 467 +       .probe = rt2880_spi_probe,
 468 +       .remove = rt2880_spi_remove,
 469 +};
 470 +
 471 +module_platform_driver(rt2880_spi_driver);
 472 +
 473 +MODULE_DESCRIPTION("Ralink SPI driver");
 474 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
 475 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 476 +MODULE_LICENSE("GPL");