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[openwrt/openwrt.git] / target / linux / ramips / patches-3.18 / 0053-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
1 From f954801c6f48fc291c39ca8a888dbdfda1021415 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 13 Nov 2014 19:08:40 +0100
4 Subject: [PATCH] mmc: MIPS: ralink: add sdhci for mt7620a SoC
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/mmc/host/Kconfig | 2 +
9 drivers/mmc/host/Makefile | 1 +
10 drivers/mmc/host/mtk-mmc/Kconfig | 16 +
11 drivers/mmc/host/mtk-mmc/Makefile | 42 +
12 drivers/mmc/host/mtk-mmc/board.h | 137 ++
13 drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++
14 drivers/mmc/host/mtk-mmc/dbg.h | 153 ++
15 drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
16 drivers/mmc/host/mtk-mmc/sd.c | 3041 ++++++++++++++++++++++++++++++++++
17 9 files changed, 4740 insertions(+)
18 create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
19 create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
20 create mode 100644 drivers/mmc/host/mtk-mmc/board.h
21 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
22 create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
23 create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
24 create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
25
26 --- a/drivers/mmc/host/Kconfig
27 +++ b/drivers/mmc/host/Kconfig
28 @@ -773,3 +773,5 @@ config MMC_SUNXI
29 help
30 This selects support for the SD/MMC Host Controller on
31 Allwinner sunxi SoCs.
32 +
33 +source "drivers/mmc/host/mtk-mmc/Kconfig"
34 --- a/drivers/mmc/host/Makefile
35 +++ b/drivers/mmc/host/Makefile
36 @@ -2,6 +2,7 @@
37 # Makefile for MMC/SD host controller drivers
38 #
39
40 +obj-$(CONFIG_MTK_MMC) += mtk-mmc/
41 obj-$(CONFIG_MMC_ARMMMCI) += mmci.o
42 obj-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
43 obj-$(CONFIG_MMC_PXA) += pxamci.o
44 --- /dev/null
45 +++ b/drivers/mmc/host/mtk-mmc/Kconfig
46 @@ -0,0 +1,16 @@
47 +config MTK_MMC
48 + tristate "MTK SD/MMC"
49 + depends on !MTD_NAND_RALINK
50 +
51 +config MTK_AEE_KDUMP
52 + bool "MTK AEE KDUMP"
53 + depends on MTK_MMC
54 +
55 +config MTK_MMC_CD_POLL
56 + bool "Card Detect with Polling"
57 + depends on MTK_MMC
58 +
59 +config MTK_MMC_EMMC_8BIT
60 + bool "eMMC 8-bit support"
61 + depends on MTK_MMC && RALINK_MT7628
62 +
63 --- /dev/null
64 +++ b/drivers/mmc/host/mtk-mmc/Makefile
65 @@ -0,0 +1,42 @@
66 +# Copyright Statement:
67 +#
68 +# This software/firmware and related documentation ("MediaTek Software") are
69 +# protected under relevant copyright laws. The information contained herein
70 +# is confidential and proprietary to MediaTek Inc. and/or its licensors.
71 +# Without the prior written permission of MediaTek inc. and/or its licensors,
72 +# any reproduction, modification, use or disclosure of MediaTek Software,
73 +# and information contained herein, in whole or in part, shall be strictly prohibited.
74 +#
75 +# MediaTek Inc. (C) 2010. All rights reserved.
76 +#
77 +# BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
78 +# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
79 +# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
80 +# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
81 +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
82 +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
83 +# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
84 +# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
85 +# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
86 +# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
87 +# THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
88 +# CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
89 +# SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
90 +# STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
91 +# CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
92 +# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
93 +# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
94 +# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
95 +#
96 +# The following software/firmware and/or related documentation ("MediaTek Software")
97 +# have been modified by MediaTek Inc. All revisions are subject to any receiver's
98 +# applicable license agreements with MediaTek Inc.
99 +
100 +obj-$(CONFIG_MTK_MMC) += mtk_sd.o
101 +mtk_sd-objs := sd.o dbg.o
102 +ifeq ($(CONFIG_MTK_AEE_KDUMP),y)
103 +EXTRA_CFLAGS += -DMT6575_SD_DEBUG
104 +endif
105 +
106 +clean:
107 + @rm -f *.o modules.order .*.cmd
108 --- /dev/null
109 +++ b/drivers/mmc/host/mtk-mmc/board.h
110 @@ -0,0 +1,137 @@
111 +/* Copyright Statement:
112 + *
113 + * This software/firmware and related documentation ("MediaTek Software") are
114 + * protected under relevant copyright laws. The information contained herein
115 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
116 + * Without the prior written permission of MediaTek inc. and/or its licensors,
117 + * any reproduction, modification, use or disclosure of MediaTek Software,
118 + * and information contained herein, in whole or in part, shall be strictly prohibited.
119 + */
120 +/* MediaTek Inc. (C) 2010. All rights reserved.
121 + *
122 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
123 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
124 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
125 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
126 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
127 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
128 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
129 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
130 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
131 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
132 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
133 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
134 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
135 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
136 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
137 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
138 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
139 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
140 + *
141 + * The following software/firmware and/or related documentation ("MediaTek Software")
142 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
143 + * applicable license agreements with MediaTek Inc.
144 + */
145 +
146 +#ifndef __ARCH_ARM_MACH_BOARD_H
147 +#define __ARCH_ARM_MACH_BOARD_H
148 +
149 +#include <generated/autoconf.h>
150 +#include <linux/pm.h>
151 +/* --- chhung */
152 +// #include <mach/mt6575.h>
153 +// #include <board-custom.h>
154 +/* end of chhung */
155 +
156 +typedef void (*sdio_irq_handler_t)(void*); /* external irq handler */
157 +typedef void (*pm_callback_t)(pm_message_t state, void *data);
158 +
159 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
160 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
161 +#define MSDC_RST_PIN_EN (1 << 2) /* emmc reset pin is wired */
162 +#define MSDC_SDIO_IRQ (1 << 3) /* use internal sdio irq (bus) */
163 +#define MSDC_EXT_SDIO_IRQ (1 << 4) /* use external sdio irq */
164 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
165 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
166 +#define MSDC_HIGHSPEED (1 << 7) /* high-speed mode support */
167 +#define MSDC_UHS1 (1 << 8) /* uhs-1 mode support */
168 +#define MSDC_DDR (1 << 9) /* ddr mode support */
169 +
170 +
171 +#define MSDC_SMPL_RISING (0)
172 +#define MSDC_SMPL_FALLING (1)
173 +
174 +#define MSDC_CMD_PIN (0)
175 +#define MSDC_DAT_PIN (1)
176 +#define MSDC_CD_PIN (2)
177 +#define MSDC_WP_PIN (3)
178 +#define MSDC_RST_PIN (4)
179 +
180 +enum {
181 + MSDC_CLKSRC_48MHZ = 0,
182 +// MSDC_CLKSRC_26MHZ = 0,
183 +// MSDC_CLKSRC_197MHZ = 1,
184 +// MSDC_CLKSRC_208MHZ = 2
185 +};
186 +
187 +struct msdc_hw {
188 + unsigned char clk_src; /* host clock source */
189 + unsigned char cmd_edge; /* command latch edge */
190 + unsigned char data_edge; /* data latch edge */
191 + unsigned char clk_drv; /* clock pad driving */
192 + unsigned char cmd_drv; /* command pad driving */
193 + unsigned char dat_drv; /* data pad driving */
194 + unsigned long flags; /* hardware capability flags */
195 + unsigned long data_pins; /* data pins */
196 + unsigned long data_offset; /* data address offset */
197 +
198 + /* config gpio pull mode */
199 + void (*config_gpio_pin)(int type, int pull);
200 +
201 + /* external power control for card */
202 + void (*ext_power_on)(void);
203 + void (*ext_power_off)(void);
204 +
205 + /* external sdio irq operations */
206 + void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
207 + void (*enable_sdio_eirq)(void);
208 + void (*disable_sdio_eirq)(void);
209 +
210 + /* external cd irq operations */
211 + void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
212 + void (*enable_cd_eirq)(void);
213 + void (*disable_cd_eirq)(void);
214 + int (*get_cd_status)(void);
215 +
216 + /* power management callback for external module */
217 + void (*register_pm)(pm_callback_t pm_cb, void *data);
218 +};
219 +
220 +extern struct msdc_hw msdc0_hw;
221 +extern struct msdc_hw msdc1_hw;
222 +extern struct msdc_hw msdc2_hw;
223 +extern struct msdc_hw msdc3_hw;
224 +
225 +/*GPS driver*/
226 +#define GPS_FLAG_FORCE_OFF 0x0001
227 +struct mt3326_gps_hardware {
228 + int (*ext_power_on)(int);
229 + int (*ext_power_off)(int);
230 +};
231 +extern struct mt3326_gps_hardware mt3326_gps_hw;
232 +
233 +/* NAND driver */
234 +struct mt6575_nand_host_hw {
235 + unsigned int nfi_bus_width; /* NFI_BUS_WIDTH */
236 + unsigned int nfi_access_timing; /* NFI_ACCESS_TIMING */
237 + unsigned int nfi_cs_num; /* NFI_CS_NUM */
238 + unsigned int nand_sec_size; /* NAND_SECTOR_SIZE */
239 + unsigned int nand_sec_shift; /* NAND_SECTOR_SHIFT */
240 + unsigned int nand_ecc_size;
241 + unsigned int nand_ecc_bytes;
242 + unsigned int nand_ecc_mode;
243 +};
244 +extern struct mt6575_nand_host_hw mt6575_nand_hw;
245 +
246 +#endif /* __ARCH_ARM_MACH_BOARD_H */
247 +
248 --- /dev/null
249 +++ b/drivers/mmc/host/mtk-mmc/dbg.c
250 @@ -0,0 +1,347 @@
251 +/* Copyright Statement:
252 + *
253 + * This software/firmware and related documentation ("MediaTek Software") are
254 + * protected under relevant copyright laws. The information contained herein
255 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
256 + * Without the prior written permission of MediaTek inc. and/or its licensors,
257 + * any reproduction, modification, use or disclosure of MediaTek Software,
258 + * and information contained herein, in whole or in part, shall be strictly prohibited.
259 + *
260 + * MediaTek Inc. (C) 2010. All rights reserved.
261 + *
262 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
263 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
264 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
265 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
266 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
267 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
268 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
269 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
270 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
271 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
272 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
273 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
274 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
275 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
276 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
277 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
278 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
279 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
280 + *
281 + * The following software/firmware and/or related documentation ("MediaTek Software")
282 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
283 + * applicable license agreements with MediaTek Inc.
284 + */
285 +
286 +#include <linux/version.h>
287 +#include <linux/kernel.h>
288 +#include <linux/sched.h>
289 +#include <linux/kthread.h>
290 +#include <linux/delay.h>
291 +#include <linux/module.h>
292 +#include <linux/init.h>
293 +#include <linux/proc_fs.h>
294 +#include <linux/string.h>
295 +#include <linux/uaccess.h>
296 +// #include <mach/mt6575_gpt.h> /* --- by chhung */
297 +#include "dbg.h"
298 +#include "mt6575_sd.h"
299 +#include <linux/seq_file.h>
300 +
301 +static char cmd_buf[256];
302 +
303 +/* for debug zone */
304 +unsigned int sd_debug_zone[4]={
305 + 0,
306 + 0,
307 + 0,
308 + 0
309 +};
310 +
311 +/* mode select */
312 +u32 dma_size[4]={
313 + 512,
314 + 512,
315 + 512,
316 + 512
317 +};
318 +msdc_mode drv_mode[4]={
319 + MODE_SIZE_DEP, /* using DMA or not depend on the size */
320 + MODE_SIZE_DEP,
321 + MODE_SIZE_DEP,
322 + MODE_SIZE_DEP
323 +};
324 +
325 +#if defined (MT6575_SD_DEBUG)
326 +/* for driver profile */
327 +#define TICKS_ONE_MS (13000)
328 +u32 gpt_enable = 0;
329 +u32 sdio_pro_enable = 0; /* make sure gpt is enabled */
330 +u32 sdio_pro_time = 0; /* no more than 30s */
331 +struct sdio_profile sdio_perfomance = {0};
332 +
333 +#if 0 /* --- chhung */
334 +void msdc_init_gpt(void)
335 +{
336 + GPT_CONFIG config;
337 +
338 + config.num = GPT6;
339 + config.mode = GPT_FREE_RUN;
340 + config.clkSrc = GPT_CLK_SRC_SYS;
341 + config.clkDiv = GPT_CLK_DIV_1; /* 13MHz GPT6 */
342 +
343 + if (GPT_Config(config) == FALSE )
344 + return;
345 +
346 + GPT_Start(GPT6);
347 +}
348 +#endif /* end of --- */
349 +
350 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32)
351 +{
352 + u32 ret = 0;
353 +
354 + if (new_H32 == old_H32) {
355 + ret = new_L32 - old_L32;
356 + } else if(new_H32 == (old_H32 + 1)) {
357 + if (new_L32 > old_L32) {
358 + printk("msdc old_L<0x%x> new_L<0x%x>\n", old_L32, new_L32);
359 + }
360 + ret = (0xffffffff - old_L32);
361 + ret += new_L32;
362 + } else {
363 + printk("msdc old_H<0x%x> new_H<0x%x>\n", old_H32, new_H32);
364 + }
365 +
366 + return ret;
367 +}
368 +
369 +void msdc_sdio_profile(struct sdio_profile* result)
370 +{
371 + struct cmd_profile* cmd;
372 + u32 i;
373 +
374 + printk("sdio === performance dump ===\n");
375 + printk("sdio === total execute tick<%d> time<%dms> Tx<%dB> Rx<%dB>\n",
376 + result->total_tc, result->total_tc / TICKS_ONE_MS,
377 + result->total_tx_bytes, result->total_rx_bytes);
378 +
379 + /* CMD52 Dump */
380 + cmd = &result->cmd52_rx;
381 + printk("sdio === CMD52 Rx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
382 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
383 + cmd = &result->cmd52_tx;
384 + printk("sdio === CMD52 Tx <%d>times tick<%d> Max<%d> Min<%d> Aver<%d>\n", cmd->count, cmd->tot_tc,
385 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count);
386 +
387 + /* CMD53 Rx bytes + block mode */
388 + for (i=0; i<512; i++) {
389 + cmd = &result->cmd53_rx_byte[i];
390 + if (cmd->count) {
391 + printk("sdio<%6d><%3dB>_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
392 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
393 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
394 + }
395 + }
396 + for (i=0; i<100; i++) {
397 + cmd = &result->cmd53_rx_blk[i];
398 + if (cmd->count) {
399 + printk("sdio<%6d><%3d>B_Rx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
400 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
401 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
402 + }
403 + }
404 +
405 + /* CMD53 Tx bytes + block mode */
406 + for (i=0; i<512; i++) {
407 + cmd = &result->cmd53_tx_byte[i];
408 + if (cmd->count) {
409 + printk("sdio<%6d><%3dB>_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
410 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
411 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
412 + }
413 + }
414 + for (i=0; i<100; i++) {
415 + cmd = &result->cmd53_tx_blk[i];
416 + if (cmd->count) {
417 + printk("sdio<%6d><%3d>B_Tx_<%9d><%9d><%6d><%6d>_<%9dB><%2dM>\n", cmd->count, i, cmd->tot_tc,
418 + cmd->max_tc, cmd->min_tc, cmd->tot_tc/cmd->count,
419 + cmd->tot_bytes, (cmd->tot_bytes/10)*13 / (cmd->tot_tc/10));
420 + }
421 + }
422 +
423 + printk("sdio === performance dump done ===\n");
424 +}
425 +
426 +//========= sdio command table ===========
427 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks)
428 +{
429 + struct sdio_profile* result = &sdio_perfomance;
430 + struct cmd_profile* cmd;
431 + u32 block;
432 +
433 + if (sdio_pro_enable == 0) {
434 + return;
435 + }
436 +
437 + if (opcode == 52) {
438 + cmd = bRx ? &result->cmd52_rx : &result->cmd52_tx;
439 + } else if (opcode == 53) {
440 + if (sizes < 512) {
441 + cmd = bRx ? &result->cmd53_rx_byte[sizes] : &result->cmd53_tx_byte[sizes];
442 + } else {
443 + block = sizes / 512;
444 + if (block >= 99) {
445 + printk("cmd53 error blocks\n");
446 + while(1);
447 + }
448 + cmd = bRx ? &result->cmd53_rx_blk[block] : &result->cmd53_tx_blk[block];
449 + }
450 + } else {
451 + return;
452 + }
453 +
454 + /* update the members */
455 + if (ticks > cmd->max_tc){
456 + cmd->max_tc = ticks;
457 + }
458 + if (cmd->min_tc == 0 || ticks < cmd->min_tc) {
459 + cmd->min_tc = ticks;
460 + }
461 + cmd->tot_tc += ticks;
462 + cmd->tot_bytes += sizes;
463 + cmd->count ++;
464 +
465 + if (bRx) {
466 + result->total_rx_bytes += sizes;
467 + } else {
468 + result->total_tx_bytes += sizes;
469 + }
470 + result->total_tc += ticks;
471 +
472 + /* dump when total_tc > 30s */
473 + if (result->total_tc >= sdio_pro_time * TICKS_ONE_MS * 1000) {
474 + msdc_sdio_profile(result);
475 + memset(result, 0 , sizeof(struct sdio_profile));
476 + }
477 +}
478 +
479 +//========== driver proc interface ===========
480 +static int msdc_debug_proc_read(struct seq_file *s, void *p)
481 +{
482 + seq_printf(s, "\n=========================================\n");
483 + seq_printf(s, "Index<0> + Id + Zone\n");
484 + seq_printf(s, "-> PWR<9> WRN<8> | FIO<7> OPS<6> FUN<5> CFG<4> | INT<3> RSP<2> CMD<1> DMA<0>\n");
485 + seq_printf(s, "-> echo 0 3 0x3ff >msdc_bebug -> host[3] debug zone set to 0x3ff\n");
486 + seq_printf(s, "-> MSDC[0] Zone: 0x%.8x\n", sd_debug_zone[0]);
487 + seq_printf(s, "-> MSDC[1] Zone: 0x%.8x\n", sd_debug_zone[1]);
488 + seq_printf(s, "-> MSDC[2] Zone: 0x%.8x\n", sd_debug_zone[2]);
489 + seq_printf(s, "-> MSDC[3] Zone: 0x%.8x\n", sd_debug_zone[3]);
490 +
491 + seq_printf(s, "Index<1> + ID:4|Mode:4 + DMA_SIZE\n");
492 + seq_printf(s, "-> 0)PIO 1)DMA 2)SIZE\n");
493 + seq_printf(s, "-> echo 1 22 0x200 >msdc_bebug -> host[2] size mode, dma when >= 512\n");
494 + seq_printf(s, "-> MSDC[0] mode<%d> size<%d>\n", drv_mode[0], dma_size[0]);
495 + seq_printf(s, "-> MSDC[1] mode<%d> size<%d>\n", drv_mode[1], dma_size[1]);
496 + seq_printf(s, "-> MSDC[2] mode<%d> size<%d>\n", drv_mode[2], dma_size[2]);
497 + seq_printf(s, "-> MSDC[3] mode<%d> size<%d>\n", drv_mode[3], dma_size[3]);
498 +
499 + seq_printf(s, "Index<3> + SDIO_PROFILE + TIME\n");
500 + seq_printf(s, "-> echo 3 1 0x1E >msdc_bebug -> enable sdio_profile, 30s\n");
501 + seq_printf(s, "-> SDIO_PROFILE<%d> TIME<%ds>\n", sdio_pro_enable, sdio_pro_time);
502 + seq_printf(s, "=========================================\n\n");
503 +
504 + return 0;
505 +}
506 +
507 +static ssize_t msdc_debug_proc_write(struct file *file,
508 + const char __user *buf, size_t count, loff_t *data)
509 +{
510 + int ret;
511 +
512 + int cmd, p1, p2;
513 + int id, zone;
514 + int mode, size;
515 +
516 + if (count == 0)return -1;
517 + if(count > 255)count = 255;
518 +
519 + ret = copy_from_user(cmd_buf, buf, count);
520 + if (ret < 0)return -1;
521 +
522 + cmd_buf[count] = '\0';
523 + printk("msdc Write %s\n", cmd_buf);
524 +
525 + sscanf(cmd_buf, "%x %x %x", &cmd, &p1, &p2);
526 +
527 + if(cmd == SD_TOOL_ZONE) {
528 + id = p1; zone = p2; zone &= 0x3ff;
529 + printk("msdc host_id<%d> zone<0x%.8x>\n", id, zone);
530 + if(id >=0 && id<=3){
531 + sd_debug_zone[id] = zone;
532 + }
533 + else if(id == 4){
534 + sd_debug_zone[0] = sd_debug_zone[1] = zone;
535 + sd_debug_zone[2] = sd_debug_zone[3] = zone;
536 + }
537 + else{
538 + printk("msdc host_id error when set debug zone\n");
539 + }
540 + } else if (cmd == SD_TOOL_DMA_SIZE) {
541 + id = p1>>4; mode = (p1&0xf); size = p2;
542 + if(id >=0 && id<=3){
543 + drv_mode[id] = mode;
544 + dma_size[id] = p2;
545 + }
546 + else if(id == 4){
547 + drv_mode[0] = drv_mode[1] = mode;
548 + drv_mode[2] = drv_mode[3] = mode;
549 + dma_size[0] = dma_size[1] = p2;
550 + dma_size[2] = dma_size[3] = p2;
551 + }
552 + else{
553 + printk("msdc host_id error when select mode\n");
554 + }
555 + } else if (cmd == SD_TOOL_SDIO_PROFILE) {
556 + if (p1 == 1) { /* enable profile */
557 + if (gpt_enable == 0) {
558 + // msdc_init_gpt(); /* --- by chhung */
559 + gpt_enable = 1;
560 + }
561 + sdio_pro_enable = 1;
562 + if (p2 == 0) p2 = 1; if (p2 >= 30) p2 = 30;
563 + sdio_pro_time = p2 ;
564 + } else if (p1 == 0) {
565 + /* todo */
566 + sdio_pro_enable = 0;
567 + }
568 + }
569 +
570 + return count;
571 +}
572 +
573 +static int msdc_debug_show(struct inode *inode, struct file *file)
574 +{
575 + return single_open(file, msdc_debug_proc_read, NULL);
576 +}
577 +
578 +static const struct file_operations msdc_debug_fops = {
579 + .owner = THIS_MODULE,
580 + .open = msdc_debug_show,
581 + .read = seq_read,
582 + .write = msdc_debug_proc_write,
583 + .llseek = seq_lseek,
584 + .release = single_release,
585 +};
586 +
587 +int msdc_debug_proc_init(void)
588 +{
589 + struct proc_dir_entry *de = proc_create("msdc_debug", 0667, NULL, &msdc_debug_fops);
590 +
591 + if (!de || IS_ERR(de))
592 + printk("!! Create MSDC debug PROC fail !!\n");
593 +
594 + return 0 ;
595 +}
596 +EXPORT_SYMBOL_GPL(msdc_debug_proc_init);
597 +#endif
598 --- /dev/null
599 +++ b/drivers/mmc/host/mtk-mmc/dbg.h
600 @@ -0,0 +1,156 @@
601 +/* Copyright Statement:
602 + *
603 + * This software/firmware and related documentation ("MediaTek Software") are
604 + * protected under relevant copyright laws. The information contained herein
605 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
606 + * Without the prior written permission of MediaTek inc. and/or its licensors,
607 + * any reproduction, modification, use or disclosure of MediaTek Software,
608 + * and information contained herein, in whole or in part, shall be strictly prohibited.
609 + *
610 + * MediaTek Inc. (C) 2010. All rights reserved.
611 + *
612 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
613 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
614 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
615 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
616 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
617 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
618 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
619 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
620 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
621 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
622 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
623 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
624 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
625 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
626 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
627 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
628 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
629 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
630 + *
631 + * The following software/firmware and/or related documentation ("MediaTek Software")
632 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
633 + * applicable license agreements with MediaTek Inc.
634 + */
635 +#ifndef __MT_MSDC_DEUBG__
636 +#define __MT_MSDC_DEUBG__
637 +
638 +//==========================
639 +extern u32 sdio_pro_enable;
640 +/* for a type command, e.g. CMD53, 2 blocks */
641 +struct cmd_profile {
642 + u32 max_tc; /* Max tick count */
643 + u32 min_tc;
644 + u32 tot_tc; /* total tick count */
645 + u32 tot_bytes;
646 + u32 count; /* the counts of the command */
647 +};
648 +
649 +/* dump when total_tc and total_bytes */
650 +struct sdio_profile {
651 + u32 total_tc; /* total tick count of CMD52 and CMD53 */
652 + u32 total_tx_bytes; /* total bytes of CMD53 Tx */
653 + u32 total_rx_bytes; /* total bytes of CMD53 Rx */
654 +
655 + /*CMD52*/
656 + struct cmd_profile cmd52_tx;
657 + struct cmd_profile cmd52_rx;
658 +
659 + /*CMD53 in byte unit */
660 + struct cmd_profile cmd53_tx_byte[512];
661 + struct cmd_profile cmd53_rx_byte[512];
662 +
663 + /*CMD53 in block unit */
664 + struct cmd_profile cmd53_tx_blk[100];
665 + struct cmd_profile cmd53_rx_blk[100];
666 +};
667 +
668 +//==========================
669 +typedef enum {
670 + SD_TOOL_ZONE = 0,
671 + SD_TOOL_DMA_SIZE = 1,
672 + SD_TOOL_PM_ENABLE = 2,
673 + SD_TOOL_SDIO_PROFILE = 3,
674 +} msdc_dbg;
675 +
676 +typedef enum {
677 + MODE_PIO = 0,
678 + MODE_DMA = 1,
679 + MODE_SIZE_DEP = 2,
680 +} msdc_mode;
681 +extern msdc_mode drv_mode[4];
682 +extern u32 dma_size[4];
683 +
684 +/* Debug message event */
685 +#define DBG_EVT_NONE (0) /* No event */
686 +#define DBG_EVT_DMA (1 << 0) /* DMA related event */
687 +#define DBG_EVT_CMD (1 << 1) /* MSDC CMD related event */
688 +#define DBG_EVT_RSP (1 << 2) /* MSDC CMD RSP related event */
689 +#define DBG_EVT_INT (1 << 3) /* MSDC INT event */
690 +#define DBG_EVT_CFG (1 << 4) /* MSDC CFG event */
691 +#define DBG_EVT_FUC (1 << 5) /* Function event */
692 +#define DBG_EVT_OPS (1 << 6) /* Read/Write operation event */
693 +#define DBG_EVT_FIO (1 << 7) /* FIFO operation event */
694 +#define DBG_EVT_WRN (1 << 8) /* Warning event */
695 +#define DBG_EVT_PWR (1 << 9) /* Power event */
696 +#define DBG_EVT_ALL (0xffffffff)
697 +
698 +#define DBG_EVT_MASK (DBG_EVT_ALL)
699 +
700 +extern unsigned int sd_debug_zone[4];
701 +#define TAG "msdc"
702 +#if 0 /* +++ chhung */
703 +#define BUG_ON(x) \
704 +do { \
705 + if (x) { \
706 + printk("[BUG] %s LINE:%d FILE:%s\n", #x, __LINE__, __FILE__); \
707 + while(1); \
708 + } \
709 +}while(0)
710 +#endif /* end of +++ */
711 +
712 +#define N_MSG(evt, fmt, args...)
713 +/*
714 +do { \
715 + if ((DBG_EVT_##evt) & sd_debug_zone[host->id]) { \
716 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
717 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
718 + } \
719 +} while(0)
720 +*/
721 +
722 +#define ERR_MSG(fmt, args...) \
723 +do { \
724 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
725 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
726 +} while(0);
727 +
728 +#if 1
729 +//defined CONFIG_MTK_MMC_CD_POLL
730 +#define INIT_MSG(fmt, args...)
731 +#define IRQ_MSG(fmt, args...)
732 +#else
733 +#define INIT_MSG(fmt, args...) \
734 +do { \
735 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d> PID<%s><0x%x>\n", \
736 + host->id, ##args , __FUNCTION__, __LINE__, current->comm, current->pid); \
737 +} while(0);
738 +
739 +/* PID in ISR in not corrent */
740 +#define IRQ_MSG(fmt, args...) \
741 +do { \
742 + printk(KERN_ERR TAG"%d -> "fmt" <- %s() : L<%d>\n", \
743 + host->id, ##args , __FUNCTION__, __LINE__); \
744 +} while(0);
745 +#endif
746 +
747 +int msdc_debug_proc_init(void);
748 +
749 +#if 0 /* --- chhung */
750 +void msdc_init_gpt(void);
751 +extern void GPT_GetCounter64(UINT32 *cntL32, UINT32 *cntH32);
752 +#endif /* end of --- */
753 +u32 msdc_time_calc(u32 old_L32, u32 old_H32, u32 new_L32, u32 new_H32);
754 +void msdc_performance(u32 opcode, u32 sizes, u32 bRx, u32 ticks);
755 +
756 +#endif
757 --- /dev/null
758 +++ b/drivers/mmc/host/mtk-mmc/mt6575_sd.h
759 @@ -0,0 +1,1001 @@
760 +/* Copyright Statement:
761 + *
762 + * This software/firmware and related documentation ("MediaTek Software") are
763 + * protected under relevant copyright laws. The information contained herein
764 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
765 + * Without the prior written permission of MediaTek inc. and/or its licensors,
766 + * any reproduction, modification, use or disclosure of MediaTek Software,
767 + * and information contained herein, in whole or in part, shall be strictly prohibited.
768 + */
769 +/* MediaTek Inc. (C) 2010. All rights reserved.
770 + *
771 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
772 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
773 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
774 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
775 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
776 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
777 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
778 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
779 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
780 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
781 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
782 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
783 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
784 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
785 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
786 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
787 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
788 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
789 + *
790 + * The following software/firmware and/or related documentation ("MediaTek Software")
791 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
792 + * applicable license agreements with MediaTek Inc.
793 + */
794 +
795 +#ifndef MT6575_SD_H
796 +#define MT6575_SD_H
797 +
798 +#include <linux/bitops.h>
799 +#include <linux/mmc/host.h>
800 +
801 +// #include <mach/mt6575_reg_base.h> /* --- by chhung */
802 +
803 +/*--------------------------------------------------------------------------*/
804 +/* Common Macro */
805 +/*--------------------------------------------------------------------------*/
806 +#define REG_ADDR(x) ((volatile u32*)(base + OFFSET_##x))
807 +
808 +/*--------------------------------------------------------------------------*/
809 +/* Common Definition */
810 +/*--------------------------------------------------------------------------*/
811 +#define MSDC_FIFO_SZ (128)
812 +#define MSDC_FIFO_THD (64) // (128)
813 +#define MSDC_NUM (4)
814 +
815 +#define MSDC_MS (0)
816 +#define MSDC_SDMMC (1)
817 +
818 +#define MSDC_MODE_UNKNOWN (0)
819 +#define MSDC_MODE_PIO (1)
820 +#define MSDC_MODE_DMA_BASIC (2)
821 +#define MSDC_MODE_DMA_DESC (3)
822 +#define MSDC_MODE_DMA_ENHANCED (4)
823 +#define MSDC_MODE_MMC_STREAM (5)
824 +
825 +#define MSDC_BUS_1BITS (0)
826 +#define MSDC_BUS_4BITS (1)
827 +#define MSDC_BUS_8BITS (2)
828 +
829 +#define MSDC_BRUST_8B (3)
830 +#define MSDC_BRUST_16B (4)
831 +#define MSDC_BRUST_32B (5)
832 +#define MSDC_BRUST_64B (6)
833 +
834 +#define MSDC_PIN_PULL_NONE (0)
835 +#define MSDC_PIN_PULL_DOWN (1)
836 +#define MSDC_PIN_PULL_UP (2)
837 +#define MSDC_PIN_KEEP (3)
838 +
839 +#define MSDC_MAX_SCLK (48000000) /* +/- by chhung */
840 +#define MSDC_MIN_SCLK (260000)
841 +
842 +#define MSDC_AUTOCMD12 (0x0001)
843 +#define MSDC_AUTOCMD23 (0x0002)
844 +#define MSDC_AUTOCMD19 (0x0003)
845 +
846 +#define MSDC_EMMC_BOOTMODE0 (0) /* Pull low CMD mode */
847 +#define MSDC_EMMC_BOOTMODE1 (1) /* Reset CMD mode */
848 +
849 +enum {
850 + RESP_NONE = 0,
851 + RESP_R1,
852 + RESP_R2,
853 + RESP_R3,
854 + RESP_R4,
855 + RESP_R5,
856 + RESP_R6,
857 + RESP_R7,
858 + RESP_R1B
859 +};
860 +
861 +/*--------------------------------------------------------------------------*/
862 +/* Register Offset */
863 +/*--------------------------------------------------------------------------*/
864 +#define OFFSET_MSDC_CFG (0x0)
865 +#define OFFSET_MSDC_IOCON (0x04)
866 +#define OFFSET_MSDC_PS (0x08)
867 +#define OFFSET_MSDC_INT (0x0c)
868 +#define OFFSET_MSDC_INTEN (0x10)
869 +#define OFFSET_MSDC_FIFOCS (0x14)
870 +#define OFFSET_MSDC_TXDATA (0x18)
871 +#define OFFSET_MSDC_RXDATA (0x1c)
872 +#define OFFSET_SDC_CFG (0x30)
873 +#define OFFSET_SDC_CMD (0x34)
874 +#define OFFSET_SDC_ARG (0x38)
875 +#define OFFSET_SDC_STS (0x3c)
876 +#define OFFSET_SDC_RESP0 (0x40)
877 +#define OFFSET_SDC_RESP1 (0x44)
878 +#define OFFSET_SDC_RESP2 (0x48)
879 +#define OFFSET_SDC_RESP3 (0x4c)
880 +#define OFFSET_SDC_BLK_NUM (0x50)
881 +#define OFFSET_SDC_CSTS (0x58)
882 +#define OFFSET_SDC_CSTS_EN (0x5c)
883 +#define OFFSET_SDC_DCRC_STS (0x60)
884 +#define OFFSET_EMMC_CFG0 (0x70)
885 +#define OFFSET_EMMC_CFG1 (0x74)
886 +#define OFFSET_EMMC_STS (0x78)
887 +#define OFFSET_EMMC_IOCON (0x7c)
888 +#define OFFSET_SDC_ACMD_RESP (0x80)
889 +#define OFFSET_SDC_ACMD19_TRG (0x84)
890 +#define OFFSET_SDC_ACMD19_STS (0x88)
891 +#define OFFSET_MSDC_DMA_SA (0x90)
892 +#define OFFSET_MSDC_DMA_CA (0x94)
893 +#define OFFSET_MSDC_DMA_CTRL (0x98)
894 +#define OFFSET_MSDC_DMA_CFG (0x9c)
895 +#define OFFSET_MSDC_DBG_SEL (0xa0)
896 +#define OFFSET_MSDC_DBG_OUT (0xa4)
897 +#define OFFSET_MSDC_PATCH_BIT (0xb0)
898 +#define OFFSET_MSDC_PATCH_BIT1 (0xb4)
899 +#define OFFSET_MSDC_PAD_CTL0 (0xe0)
900 +#define OFFSET_MSDC_PAD_CTL1 (0xe4)
901 +#define OFFSET_MSDC_PAD_CTL2 (0xe8)
902 +#define OFFSET_MSDC_PAD_TUNE (0xec)
903 +#define OFFSET_MSDC_DAT_RDDLY0 (0xf0)
904 +#define OFFSET_MSDC_DAT_RDDLY1 (0xf4)
905 +#define OFFSET_MSDC_HW_DBG (0xf8)
906 +#define OFFSET_MSDC_VERSION (0x100)
907 +#define OFFSET_MSDC_ECO_VER (0x104)
908 +
909 +/*--------------------------------------------------------------------------*/
910 +/* Register Address */
911 +/*--------------------------------------------------------------------------*/
912 +
913 +/* common register */
914 +#define MSDC_CFG REG_ADDR(MSDC_CFG)
915 +#define MSDC_IOCON REG_ADDR(MSDC_IOCON)
916 +#define MSDC_PS REG_ADDR(MSDC_PS)
917 +#define MSDC_INT REG_ADDR(MSDC_INT)
918 +#define MSDC_INTEN REG_ADDR(MSDC_INTEN)
919 +#define MSDC_FIFOCS REG_ADDR(MSDC_FIFOCS)
920 +#define MSDC_TXDATA REG_ADDR(MSDC_TXDATA)
921 +#define MSDC_RXDATA REG_ADDR(MSDC_RXDATA)
922 +#define MSDC_PATCH_BIT0 REG_ADDR(MSDC_PATCH_BIT)
923 +
924 +/* sdmmc register */
925 +#define SDC_CFG REG_ADDR(SDC_CFG)
926 +#define SDC_CMD REG_ADDR(SDC_CMD)
927 +#define SDC_ARG REG_ADDR(SDC_ARG)
928 +#define SDC_STS REG_ADDR(SDC_STS)
929 +#define SDC_RESP0 REG_ADDR(SDC_RESP0)
930 +#define SDC_RESP1 REG_ADDR(SDC_RESP1)
931 +#define SDC_RESP2 REG_ADDR(SDC_RESP2)
932 +#define SDC_RESP3 REG_ADDR(SDC_RESP3)
933 +#define SDC_BLK_NUM REG_ADDR(SDC_BLK_NUM)
934 +#define SDC_CSTS REG_ADDR(SDC_CSTS)
935 +#define SDC_CSTS_EN REG_ADDR(SDC_CSTS_EN)
936 +#define SDC_DCRC_STS REG_ADDR(SDC_DCRC_STS)
937 +
938 +/* emmc register*/
939 +#define EMMC_CFG0 REG_ADDR(EMMC_CFG0)
940 +#define EMMC_CFG1 REG_ADDR(EMMC_CFG1)
941 +#define EMMC_STS REG_ADDR(EMMC_STS)
942 +#define EMMC_IOCON REG_ADDR(EMMC_IOCON)
943 +
944 +/* auto command register */
945 +#define SDC_ACMD_RESP REG_ADDR(SDC_ACMD_RESP)
946 +#define SDC_ACMD19_TRG REG_ADDR(SDC_ACMD19_TRG)
947 +#define SDC_ACMD19_STS REG_ADDR(SDC_ACMD19_STS)
948 +
949 +/* dma register */
950 +#define MSDC_DMA_SA REG_ADDR(MSDC_DMA_SA)
951 +#define MSDC_DMA_CA REG_ADDR(MSDC_DMA_CA)
952 +#define MSDC_DMA_CTRL REG_ADDR(MSDC_DMA_CTRL)
953 +#define MSDC_DMA_CFG REG_ADDR(MSDC_DMA_CFG)
954 +
955 +/* pad ctrl register */
956 +#define MSDC_PAD_CTL0 REG_ADDR(MSDC_PAD_CTL0)
957 +#define MSDC_PAD_CTL1 REG_ADDR(MSDC_PAD_CTL1)
958 +#define MSDC_PAD_CTL2 REG_ADDR(MSDC_PAD_CTL2)
959 +
960 +/* data read delay */
961 +#define MSDC_DAT_RDDLY0 REG_ADDR(MSDC_DAT_RDDLY0)
962 +#define MSDC_DAT_RDDLY1 REG_ADDR(MSDC_DAT_RDDLY1)
963 +
964 +/* debug register */
965 +#define MSDC_DBG_SEL REG_ADDR(MSDC_DBG_SEL)
966 +#define MSDC_DBG_OUT REG_ADDR(MSDC_DBG_OUT)
967 +
968 +/* misc register */
969 +#define MSDC_PATCH_BIT REG_ADDR(MSDC_PATCH_BIT)
970 +#define MSDC_PATCH_BIT1 REG_ADDR(MSDC_PATCH_BIT1)
971 +#define MSDC_PAD_TUNE REG_ADDR(MSDC_PAD_TUNE)
972 +#define MSDC_HW_DBG REG_ADDR(MSDC_HW_DBG)
973 +#define MSDC_VERSION REG_ADDR(MSDC_VERSION)
974 +#define MSDC_ECO_VER REG_ADDR(MSDC_ECO_VER) /* ECO Version */
975 +
976 +/*--------------------------------------------------------------------------*/
977 +/* Register Mask */
978 +/*--------------------------------------------------------------------------*/
979 +
980 +/* MSDC_CFG mask */
981 +#define MSDC_CFG_MODE (0x1 << 0) /* RW */
982 +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
983 +#define MSDC_CFG_RST (0x1 << 2) /* RW */
984 +#define MSDC_CFG_PIO (0x1 << 3) /* RW */
985 +#define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
986 +#define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
987 +#define MSDC_CFG_BV18PSS (0x1 << 6) /* R */
988 +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */
989 +#define MSDC_CFG_CKDIV (0xff << 8) /* RW */
990 +#define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
991 +
992 +/* MSDC_IOCON mask */
993 +#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
994 +#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
995 +#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
996 +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
997 +#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
998 +#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
999 +#define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */
1000 +#define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */
1001 +#define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */
1002 +#define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */
1003 +#define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */
1004 +#define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */
1005 +#define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */
1006 +#define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */
1007 +#define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */
1008 +
1009 +/* MSDC_PS mask */
1010 +#define MSDC_PS_CDEN (0x1 << 0) /* RW */
1011 +#define MSDC_PS_CDSTS (0x1 << 1) /* R */
1012 +#define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */
1013 +#define MSDC_PS_DAT (0xff << 16) /* R */
1014 +#define MSDC_PS_CMD (0x1 << 24) /* R */
1015 +#define MSDC_PS_WP (0x1UL<< 31) /* R */
1016 +
1017 +/* MSDC_INT mask */
1018 +#define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */
1019 +#define MSDC_INT_CDSC (0x1 << 1) /* W1C */
1020 +#define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */
1021 +#define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */
1022 +#define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */
1023 +#define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */
1024 +#define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */
1025 +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */
1026 +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */
1027 +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */
1028 +#define MSDC_INT_CSTA (0x1 << 11) /* R */
1029 +#define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */
1030 +#define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */
1031 +#define MSDC_INT_DATTMO (0x1 << 14) /* W1C */
1032 +#define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */
1033 +#define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */
1034 +
1035 +/* MSDC_INTEN mask */
1036 +#define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */
1037 +#define MSDC_INTEN_CDSC (0x1 << 1) /* RW */
1038 +#define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */
1039 +#define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */
1040 +#define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */
1041 +#define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */
1042 +#define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */
1043 +#define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */
1044 +#define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */
1045 +#define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */
1046 +#define MSDC_INTEN_CSTA (0x1 << 11) /* RW */
1047 +#define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */
1048 +#define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */
1049 +#define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */
1050 +#define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */
1051 +#define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */
1052 +
1053 +/* MSDC_FIFOCS mask */
1054 +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */
1055 +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */
1056 +#define MSDC_FIFOCS_CLR (0x1UL<< 31) /* RW */
1057 +
1058 +/* SDC_CFG mask */
1059 +#define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */
1060 +#define SDC_CFG_INSWKUP (0x1 << 1) /* RW */
1061 +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */
1062 +#define SDC_CFG_SDIO (0x1 << 19) /* RW */
1063 +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */
1064 +#define SDC_CFG_INTATGAP (0x1 << 21) /* RW */
1065 +#define SDC_CFG_DTOC (0xffUL << 24) /* RW */
1066 +
1067 +/* SDC_CMD mask */
1068 +#define SDC_CMD_OPC (0x3f << 0) /* RW */
1069 +#define SDC_CMD_BRK (0x1 << 6) /* RW */
1070 +#define SDC_CMD_RSPTYP (0x7 << 7) /* RW */
1071 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1072 +#define SDC_CMD_DTYP (0x3 << 11) /* RW */
1073 +#define SDC_CMD_RW (0x1 << 13) /* RW */
1074 +#define SDC_CMD_STOP (0x1 << 14) /* RW */
1075 +#define SDC_CMD_GOIRQ (0x1 << 15) /* RW */
1076 +#define SDC_CMD_BLKLEN (0xfff<< 16) /* RW */
1077 +#define SDC_CMD_AUTOCMD (0x3 << 28) /* RW */
1078 +#define SDC_CMD_VOLSWTH (0x1 << 30) /* RW */
1079 +
1080 +/* SDC_STS mask */
1081 +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */
1082 +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */
1083 +#define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */
1084 +
1085 +/* SDC_DCRC_STS mask */
1086 +#define SDC_DCRC_STS_NEG (0xf << 8) /* RO */
1087 +#define SDC_DCRC_STS_POS (0xff << 0) /* RO */
1088 +
1089 +/* EMMC_CFG0 mask */
1090 +#define EMMC_CFG0_BOOTSTART (0x1 << 0) /* W */
1091 +#define EMMC_CFG0_BOOTSTOP (0x1 << 1) /* W */
1092 +#define EMMC_CFG0_BOOTMODE (0x1 << 2) /* RW */
1093 +#define EMMC_CFG0_BOOTACKDIS (0x1 << 3) /* RW */
1094 +#define EMMC_CFG0_BOOTWDLY (0x7 << 12) /* RW */
1095 +#define EMMC_CFG0_BOOTSUPP (0x1 << 15) /* RW */
1096 +
1097 +/* EMMC_CFG1 mask */
1098 +#define EMMC_CFG1_BOOTDATTMC (0xfffff << 0) /* RW */
1099 +#define EMMC_CFG1_BOOTACKTMC (0xfffUL << 20) /* RW */
1100 +
1101 +/* EMMC_STS mask */
1102 +#define EMMC_STS_BOOTCRCERR (0x1 << 0) /* W1C */
1103 +#define EMMC_STS_BOOTACKERR (0x1 << 1) /* W1C */
1104 +#define EMMC_STS_BOOTDATTMO (0x1 << 2) /* W1C */
1105 +#define EMMC_STS_BOOTACKTMO (0x1 << 3) /* W1C */
1106 +#define EMMC_STS_BOOTUPSTATE (0x1 << 4) /* R */
1107 +#define EMMC_STS_BOOTACKRCV (0x1 << 5) /* W1C */
1108 +#define EMMC_STS_BOOTDATRCV (0x1 << 6) /* R */
1109 +
1110 +/* EMMC_IOCON mask */
1111 +#define EMMC_IOCON_BOOTRST (0x1 << 0) /* RW */
1112 +
1113 +/* SDC_ACMD19_TRG mask */
1114 +#define SDC_ACMD19_TRG_TUNESEL (0xf << 0) /* RW */
1115 +
1116 +/* MSDC_DMA_CTRL mask */
1117 +#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
1118 +#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
1119 +#define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */
1120 +#define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */
1121 +#define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */
1122 +#define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */
1123 +#define MSDC_DMA_CTRL_XFERSZ (0xffffUL << 16)/* RW */
1124 +
1125 +/* MSDC_DMA_CFG mask */
1126 +#define MSDC_DMA_CFG_STS (0x1 << 0) /* R */
1127 +#define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */
1128 +#define MSDC_DMA_CFG_BDCSERR (0x1 << 4) /* R */
1129 +#define MSDC_DMA_CFG_GPDCSERR (0x1 << 5) /* R */
1130 +
1131 +/* MSDC_PATCH_BIT mask */
1132 +#define MSDC_PATCH_BIT_WFLSMODE (0x1 << 0) /* RW */
1133 +#define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */
1134 +#define MSDC_PATCH_BIT_CKGEN_CK (0x1 << 6) /* E2: Fixed to 1 */
1135 +#define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */
1136 +#define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */
1137 +#define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */
1138 +#define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */
1139 +#define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */
1140 +#define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */
1141 +#define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */
1142 +#define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */
1143 +#define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */
1144 +
1145 +/* MSDC_PATCH_BIT1 mask */
1146 +#define MSDC_PATCH_BIT1_WRDAT_CRCS (0x7 << 3)
1147 +#define MSDC_PATCH_BIT1_CMD_RSP (0x7 << 0)
1148 +
1149 +/* MSDC_PAD_CTL0 mask */
1150 +#define MSDC_PAD_CTL0_CLKDRVN (0x7 << 0) /* RW */
1151 +#define MSDC_PAD_CTL0_CLKDRVP (0x7 << 4) /* RW */
1152 +#define MSDC_PAD_CTL0_CLKSR (0x1 << 8) /* RW */
1153 +#define MSDC_PAD_CTL0_CLKPD (0x1 << 16) /* RW */
1154 +#define MSDC_PAD_CTL0_CLKPU (0x1 << 17) /* RW */
1155 +#define MSDC_PAD_CTL0_CLKSMT (0x1 << 18) /* RW */
1156 +#define MSDC_PAD_CTL0_CLKIES (0x1 << 19) /* RW */
1157 +#define MSDC_PAD_CTL0_CLKTDSEL (0xf << 20) /* RW */
1158 +#define MSDC_PAD_CTL0_CLKRDSEL (0xffUL<< 24) /* RW */
1159 +
1160 +/* MSDC_PAD_CTL1 mask */
1161 +#define MSDC_PAD_CTL1_CMDDRVN (0x7 << 0) /* RW */
1162 +#define MSDC_PAD_CTL1_CMDDRVP (0x7 << 4) /* RW */
1163 +#define MSDC_PAD_CTL1_CMDSR (0x1 << 8) /* RW */
1164 +#define MSDC_PAD_CTL1_CMDPD (0x1 << 16) /* RW */
1165 +#define MSDC_PAD_CTL1_CMDPU (0x1 << 17) /* RW */
1166 +#define MSDC_PAD_CTL1_CMDSMT (0x1 << 18) /* RW */
1167 +#define MSDC_PAD_CTL1_CMDIES (0x1 << 19) /* RW */
1168 +#define MSDC_PAD_CTL1_CMDTDSEL (0xf << 20) /* RW */
1169 +#define MSDC_PAD_CTL1_CMDRDSEL (0xffUL<< 24) /* RW */
1170 +
1171 +/* MSDC_PAD_CTL2 mask */
1172 +#define MSDC_PAD_CTL2_DATDRVN (0x7 << 0) /* RW */
1173 +#define MSDC_PAD_CTL2_DATDRVP (0x7 << 4) /* RW */
1174 +#define MSDC_PAD_CTL2_DATSR (0x1 << 8) /* RW */
1175 +#define MSDC_PAD_CTL2_DATPD (0x1 << 16) /* RW */
1176 +#define MSDC_PAD_CTL2_DATPU (0x1 << 17) /* RW */
1177 +#define MSDC_PAD_CTL2_DATIES (0x1 << 19) /* RW */
1178 +#define MSDC_PAD_CTL2_DATSMT (0x1 << 18) /* RW */
1179 +#define MSDC_PAD_CTL2_DATTDSEL (0xf << 20) /* RW */
1180 +#define MSDC_PAD_CTL2_DATRDSEL (0xffUL<< 24) /* RW */
1181 +
1182 +/* MSDC_PAD_TUNE mask */
1183 +#define MSDC_PAD_TUNE_DATWRDLY (0x1F << 0) /* RW */
1184 +#define MSDC_PAD_TUNE_DATRRDLY (0x1F << 8) /* RW */
1185 +#define MSDC_PAD_TUNE_CMDRDLY (0x1F << 16) /* RW */
1186 +#define MSDC_PAD_TUNE_CMDRRDLY (0x1FUL << 22) /* RW */
1187 +#define MSDC_PAD_TUNE_CLKTXDLY (0x1FUL << 27) /* RW */
1188 +
1189 +/* MSDC_DAT_RDDLY0/1 mask */
1190 +#define MSDC_DAT_RDDLY0_D0 (0x1F << 0) /* RW */
1191 +#define MSDC_DAT_RDDLY0_D1 (0x1F << 8) /* RW */
1192 +#define MSDC_DAT_RDDLY0_D2 (0x1F << 16) /* RW */
1193 +#define MSDC_DAT_RDDLY0_D3 (0x1F << 24) /* RW */
1194 +
1195 +#define MSDC_DAT_RDDLY1_D4 (0x1F << 0) /* RW */
1196 +#define MSDC_DAT_RDDLY1_D5 (0x1F << 8) /* RW */
1197 +#define MSDC_DAT_RDDLY1_D6 (0x1F << 16) /* RW */
1198 +#define MSDC_DAT_RDDLY1_D7 (0x1F << 24) /* RW */
1199 +
1200 +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1F<<10)
1201 +#define MSDC_INT_DAT_LATCH_CK_SEL (0x7<<7)
1202 +#define MSDC_CKGEN_MSDC_CK_SEL (0x1<<6)
1203 +#define CARD_READY_FOR_DATA (1<<8)
1204 +#define CARD_CURRENT_STATE(x) ((x&0x00001E00)>>9)
1205 +
1206 +/*--------------------------------------------------------------------------*/
1207 +/* Descriptor Structure */
1208 +/*--------------------------------------------------------------------------*/
1209 +typedef struct {
1210 + u32 hwo:1; /* could be changed by hw */
1211 + u32 bdp:1;
1212 + u32 rsv0:6;
1213 + u32 chksum:8;
1214 + u32 intr:1;
1215 + u32 rsv1:15;
1216 + void *next;
1217 + void *ptr;
1218 + u32 buflen:16;
1219 + u32 extlen:8;
1220 + u32 rsv2:8;
1221 + u32 arg;
1222 + u32 blknum;
1223 + u32 cmd;
1224 +} gpd_t;
1225 +
1226 +typedef struct {
1227 + u32 eol:1;
1228 + u32 rsv0:7;
1229 + u32 chksum:8;
1230 + u32 rsv1:1;
1231 + u32 blkpad:1;
1232 + u32 dwpad:1;
1233 + u32 rsv2:13;
1234 + void *next;
1235 + void *ptr;
1236 + u32 buflen:16;
1237 + u32 rsv3:16;
1238 +} bd_t;
1239 +
1240 +/*--------------------------------------------------------------------------*/
1241 +/* Register Debugging Structure */
1242 +/*--------------------------------------------------------------------------*/
1243 +
1244 +typedef struct {
1245 + u32 msdc:1;
1246 + u32 ckpwn:1;
1247 + u32 rst:1;
1248 + u32 pio:1;
1249 + u32 ckdrven:1;
1250 + u32 start18v:1;
1251 + u32 pass18v:1;
1252 + u32 ckstb:1;
1253 + u32 ckdiv:8;
1254 + u32 ckmod:2;
1255 + u32 pad:14;
1256 +} msdc_cfg_reg;
1257 +typedef struct {
1258 + u32 sdr104cksel:1;
1259 + u32 rsmpl:1;
1260 + u32 dsmpl:1;
1261 + u32 ddlysel:1;
1262 + u32 ddr50ckd:1;
1263 + u32 dsplsel:1;
1264 + u32 pad1:10;
1265 + u32 d0spl:1;
1266 + u32 d1spl:1;
1267 + u32 d2spl:1;
1268 + u32 d3spl:1;
1269 + u32 d4spl:1;
1270 + u32 d5spl:1;
1271 + u32 d6spl:1;
1272 + u32 d7spl:1;
1273 + u32 riscsz:1;
1274 + u32 pad2:7;
1275 +} msdc_iocon_reg;
1276 +typedef struct {
1277 + u32 cden:1;
1278 + u32 cdsts:1;
1279 + u32 pad1:10;
1280 + u32 cddebounce:4;
1281 + u32 dat:8;
1282 + u32 cmd:1;
1283 + u32 pad2:6;
1284 + u32 wp:1;
1285 +} msdc_ps_reg;
1286 +typedef struct {
1287 + u32 mmcirq:1;
1288 + u32 cdsc:1;
1289 + u32 pad1:1;
1290 + u32 atocmdrdy:1;
1291 + u32 atocmdtmo:1;
1292 + u32 atocmdcrc:1;
1293 + u32 dmaqempty:1;
1294 + u32 sdioirq:1;
1295 + u32 cmdrdy:1;
1296 + u32 cmdtmo:1;
1297 + u32 rspcrc:1;
1298 + u32 csta:1;
1299 + u32 xfercomp:1;
1300 + u32 dxferdone:1;
1301 + u32 dattmo:1;
1302 + u32 datcrc:1;
1303 + u32 atocmd19done:1;
1304 + u32 pad2:15;
1305 +} msdc_int_reg;
1306 +typedef struct {
1307 + u32 mmcirq:1;
1308 + u32 cdsc:1;
1309 + u32 pad1:1;
1310 + u32 atocmdrdy:1;
1311 + u32 atocmdtmo:1;
1312 + u32 atocmdcrc:1;
1313 + u32 dmaqempty:1;
1314 + u32 sdioirq:1;
1315 + u32 cmdrdy:1;
1316 + u32 cmdtmo:1;
1317 + u32 rspcrc:1;
1318 + u32 csta:1;
1319 + u32 xfercomp:1;
1320 + u32 dxferdone:1;
1321 + u32 dattmo:1;
1322 + u32 datcrc:1;
1323 + u32 atocmd19done:1;
1324 + u32 pad2:15;
1325 +} msdc_inten_reg;
1326 +typedef struct {
1327 + u32 rxcnt:8;
1328 + u32 pad1:8;
1329 + u32 txcnt:8;
1330 + u32 pad2:7;
1331 + u32 clr:1;
1332 +} msdc_fifocs_reg;
1333 +typedef struct {
1334 + u32 val;
1335 +} msdc_txdat_reg;
1336 +typedef struct {
1337 + u32 val;
1338 +} msdc_rxdat_reg;
1339 +typedef struct {
1340 + u32 sdiowkup:1;
1341 + u32 inswkup:1;
1342 + u32 pad1:14;
1343 + u32 buswidth:2;
1344 + u32 pad2:1;
1345 + u32 sdio:1;
1346 + u32 sdioide:1;
1347 + u32 intblkgap:1;
1348 + u32 pad4:2;
1349 + u32 dtoc:8;
1350 +} sdc_cfg_reg;
1351 +typedef struct {
1352 + u32 cmd:6;
1353 + u32 brk:1;
1354 + u32 rsptyp:3;
1355 + u32 pad1:1;
1356 + u32 dtype:2;
1357 + u32 rw:1;
1358 + u32 stop:1;
1359 + u32 goirq:1;
1360 + u32 blklen:12;
1361 + u32 atocmd:2;
1362 + u32 volswth:1;
1363 + u32 pad2:1;
1364 +} sdc_cmd_reg;
1365 +typedef struct {
1366 + u32 arg;
1367 +} sdc_arg_reg;
1368 +typedef struct {
1369 + u32 sdcbusy:1;
1370 + u32 cmdbusy:1;
1371 + u32 pad:29;
1372 + u32 swrcmpl:1;
1373 +} sdc_sts_reg;
1374 +typedef struct {
1375 + u32 val;
1376 +} sdc_resp0_reg;
1377 +typedef struct {
1378 + u32 val;
1379 +} sdc_resp1_reg;
1380 +typedef struct {
1381 + u32 val;
1382 +} sdc_resp2_reg;
1383 +typedef struct {
1384 + u32 val;
1385 +} sdc_resp3_reg;
1386 +typedef struct {
1387 + u32 num;
1388 +} sdc_blknum_reg;
1389 +typedef struct {
1390 + u32 sts;
1391 +} sdc_csts_reg;
1392 +typedef struct {
1393 + u32 sts;
1394 +} sdc_cstsen_reg;
1395 +typedef struct {
1396 + u32 datcrcsts:8;
1397 + u32 ddrcrcsts:4;
1398 + u32 pad:20;
1399 +} sdc_datcrcsts_reg;
1400 +typedef struct {
1401 + u32 bootstart:1;
1402 + u32 bootstop:1;
1403 + u32 bootmode:1;
1404 + u32 pad1:9;
1405 + u32 bootwaidly:3;
1406 + u32 bootsupp:1;
1407 + u32 pad2:16;
1408 +} emmc_cfg0_reg;
1409 +typedef struct {
1410 + u32 bootcrctmc:16;
1411 + u32 pad:4;
1412 + u32 bootacktmc:12;
1413 +} emmc_cfg1_reg;
1414 +typedef struct {
1415 + u32 bootcrcerr:1;
1416 + u32 bootackerr:1;
1417 + u32 bootdattmo:1;
1418 + u32 bootacktmo:1;
1419 + u32 bootupstate:1;
1420 + u32 bootackrcv:1;
1421 + u32 bootdatrcv:1;
1422 + u32 pad:25;
1423 +} emmc_sts_reg;
1424 +typedef struct {
1425 + u32 bootrst:1;
1426 + u32 pad:31;
1427 +} emmc_iocon_reg;
1428 +typedef struct {
1429 + u32 val;
1430 +} msdc_acmd_resp_reg;
1431 +typedef struct {
1432 + u32 tunesel:4;
1433 + u32 pad:28;
1434 +} msdc_acmd19_trg_reg;
1435 +typedef struct {
1436 + u32 val;
1437 +} msdc_acmd19_sts_reg;
1438 +typedef struct {
1439 + u32 addr;
1440 +} msdc_dma_sa_reg;
1441 +typedef struct {
1442 + u32 addr;
1443 +} msdc_dma_ca_reg;
1444 +typedef struct {
1445 + u32 start:1;
1446 + u32 stop:1;
1447 + u32 resume:1;
1448 + u32 pad1:5;
1449 + u32 mode:1;
1450 + u32 pad2:1;
1451 + u32 lastbuf:1;
1452 + u32 pad3:1;
1453 + u32 brustsz:3;
1454 + u32 pad4:1;
1455 + u32 xfersz:16;
1456 +} msdc_dma_ctrl_reg;
1457 +typedef struct {
1458 + u32 status:1;
1459 + u32 decsen:1;
1460 + u32 pad1:2;
1461 + u32 bdcsen:1;
1462 + u32 gpdcsen:1;
1463 + u32 pad2:26;
1464 +} msdc_dma_cfg_reg;
1465 +typedef struct {
1466 + u32 sel:16;
1467 + u32 pad2:16;
1468 +} msdc_dbg_sel_reg;
1469 +typedef struct {
1470 + u32 val;
1471 +} msdc_dbg_out_reg;
1472 +typedef struct {
1473 + u32 clkdrvn:3;
1474 + u32 rsv0:1;
1475 + u32 clkdrvp:3;
1476 + u32 rsv1:1;
1477 + u32 clksr:1;
1478 + u32 rsv2:7;
1479 + u32 clkpd:1;
1480 + u32 clkpu:1;
1481 + u32 clksmt:1;
1482 + u32 clkies:1;
1483 + u32 clktdsel:4;
1484 + u32 clkrdsel:8;
1485 +} msdc_pad_ctl0_reg;
1486 +typedef struct {
1487 + u32 cmddrvn:3;
1488 + u32 rsv0:1;
1489 + u32 cmddrvp:3;
1490 + u32 rsv1:1;
1491 + u32 cmdsr:1;
1492 + u32 rsv2:7;
1493 + u32 cmdpd:1;
1494 + u32 cmdpu:1;
1495 + u32 cmdsmt:1;
1496 + u32 cmdies:1;
1497 + u32 cmdtdsel:4;
1498 + u32 cmdrdsel:8;
1499 +} msdc_pad_ctl1_reg;
1500 +typedef struct {
1501 + u32 datdrvn:3;
1502 + u32 rsv0:1;
1503 + u32 datdrvp:3;
1504 + u32 rsv1:1;
1505 + u32 datsr:1;
1506 + u32 rsv2:7;
1507 + u32 datpd:1;
1508 + u32 datpu:1;
1509 + u32 datsmt:1;
1510 + u32 daties:1;
1511 + u32 dattdsel:4;
1512 + u32 datrdsel:8;
1513 +} msdc_pad_ctl2_reg;
1514 +typedef struct {
1515 + u32 wrrxdly:3;
1516 + u32 pad1:5;
1517 + u32 rdrxdly:8;
1518 + u32 pad2:16;
1519 +} msdc_pad_tune_reg;
1520 +typedef struct {
1521 + u32 dat0:5;
1522 + u32 rsv0:3;
1523 + u32 dat1:5;
1524 + u32 rsv1:3;
1525 + u32 dat2:5;
1526 + u32 rsv2:3;
1527 + u32 dat3:5;
1528 + u32 rsv3:3;
1529 +} msdc_dat_rddly0;
1530 +typedef struct {
1531 + u32 dat4:5;
1532 + u32 rsv4:3;
1533 + u32 dat5:5;
1534 + u32 rsv5:3;
1535 + u32 dat6:5;
1536 + u32 rsv6:3;
1537 + u32 dat7:5;
1538 + u32 rsv7:3;
1539 +} msdc_dat_rddly1;
1540 +typedef struct {
1541 + u32 dbg0sel:8;
1542 + u32 dbg1sel:6;
1543 + u32 pad1:2;
1544 + u32 dbg2sel:6;
1545 + u32 pad2:2;
1546 + u32 dbg3sel:6;
1547 + u32 pad3:2;
1548 +} msdc_hw_dbg_reg;
1549 +typedef struct {
1550 + u32 val;
1551 +} msdc_version_reg;
1552 +typedef struct {
1553 + u32 val;
1554 +} msdc_eco_ver_reg;
1555 +
1556 +struct msdc_regs {
1557 + msdc_cfg_reg msdc_cfg; /* base+0x00h */
1558 + msdc_iocon_reg msdc_iocon; /* base+0x04h */
1559 + msdc_ps_reg msdc_ps; /* base+0x08h */
1560 + msdc_int_reg msdc_int; /* base+0x0ch */
1561 + msdc_inten_reg msdc_inten; /* base+0x10h */
1562 + msdc_fifocs_reg msdc_fifocs; /* base+0x14h */
1563 + msdc_txdat_reg msdc_txdat; /* base+0x18h */
1564 + msdc_rxdat_reg msdc_rxdat; /* base+0x1ch */
1565 + u32 rsv1[4];
1566 + sdc_cfg_reg sdc_cfg; /* base+0x30h */
1567 + sdc_cmd_reg sdc_cmd; /* base+0x34h */
1568 + sdc_arg_reg sdc_arg; /* base+0x38h */
1569 + sdc_sts_reg sdc_sts; /* base+0x3ch */
1570 + sdc_resp0_reg sdc_resp0; /* base+0x40h */
1571 + sdc_resp1_reg sdc_resp1; /* base+0x44h */
1572 + sdc_resp2_reg sdc_resp2; /* base+0x48h */
1573 + sdc_resp3_reg sdc_resp3; /* base+0x4ch */
1574 + sdc_blknum_reg sdc_blknum; /* base+0x50h */
1575 + u32 rsv2[1];
1576 + sdc_csts_reg sdc_csts; /* base+0x58h */
1577 + sdc_cstsen_reg sdc_cstsen; /* base+0x5ch */
1578 + sdc_datcrcsts_reg sdc_dcrcsta; /* base+0x60h */
1579 + u32 rsv3[3];
1580 + emmc_cfg0_reg emmc_cfg0; /* base+0x70h */
1581 + emmc_cfg1_reg emmc_cfg1; /* base+0x74h */
1582 + emmc_sts_reg emmc_sts; /* base+0x78h */
1583 + emmc_iocon_reg emmc_iocon; /* base+0x7ch */
1584 + msdc_acmd_resp_reg acmd_resp; /* base+0x80h */
1585 + msdc_acmd19_trg_reg acmd19_trg; /* base+0x84h */
1586 + msdc_acmd19_sts_reg acmd19_sts; /* base+0x88h */
1587 + u32 rsv4[1];
1588 + msdc_dma_sa_reg dma_sa; /* base+0x90h */
1589 + msdc_dma_ca_reg dma_ca; /* base+0x94h */
1590 + msdc_dma_ctrl_reg dma_ctrl; /* base+0x98h */
1591 + msdc_dma_cfg_reg dma_cfg; /* base+0x9ch */
1592 + msdc_dbg_sel_reg dbg_sel; /* base+0xa0h */
1593 + msdc_dbg_out_reg dbg_out; /* base+0xa4h */
1594 + u32 rsv5[2];
1595 + u32 patch0; /* base+0xb0h */
1596 + u32 patch1; /* base+0xb4h */
1597 + u32 rsv6[10];
1598 + msdc_pad_ctl0_reg pad_ctl0; /* base+0xe0h */
1599 + msdc_pad_ctl1_reg pad_ctl1; /* base+0xe4h */
1600 + msdc_pad_ctl2_reg pad_ctl2; /* base+0xe8h */
1601 + msdc_pad_tune_reg pad_tune; /* base+0xech */
1602 + msdc_dat_rddly0 dat_rddly0; /* base+0xf0h */
1603 + msdc_dat_rddly1 dat_rddly1; /* base+0xf4h */
1604 + msdc_hw_dbg_reg hw_dbg; /* base+0xf8h */
1605 + u32 rsv7[1];
1606 + msdc_version_reg version; /* base+0x100h */
1607 + msdc_eco_ver_reg eco_ver; /* base+0x104h */
1608 +};
1609 +
1610 +struct scatterlist_ex {
1611 + u32 cmd;
1612 + u32 arg;
1613 + u32 sglen;
1614 + struct scatterlist *sg;
1615 +};
1616 +
1617 +#define DMA_FLAG_NONE (0x00000000)
1618 +#define DMA_FLAG_EN_CHKSUM (0x00000001)
1619 +#define DMA_FLAG_PAD_BLOCK (0x00000002)
1620 +#define DMA_FLAG_PAD_DWORD (0x00000004)
1621 +
1622 +struct msdc_dma {
1623 + u32 flags; /* flags */
1624 + u32 xfersz; /* xfer size in bytes */
1625 + u32 sglen; /* size of scatter list */
1626 + u32 blklen; /* block size */
1627 + struct scatterlist *sg; /* I/O scatter list */
1628 + struct scatterlist_ex *esg; /* extended I/O scatter list */
1629 + u8 mode; /* dma mode */
1630 + u8 burstsz; /* burst size */
1631 + u8 intr; /* dma done interrupt */
1632 + u8 padding; /* padding */
1633 + u32 cmd; /* enhanced mode command */
1634 + u32 arg; /* enhanced mode arg */
1635 + u32 rsp; /* enhanced mode command response */
1636 + u32 autorsp; /* auto command response */
1637 +
1638 + gpd_t *gpd; /* pointer to gpd array */
1639 + bd_t *bd; /* pointer to bd array */
1640 + dma_addr_t gpd_addr; /* the physical address of gpd array */
1641 + dma_addr_t bd_addr; /* the physical address of bd array */
1642 + u32 used_gpd; /* the number of used gpd elements */
1643 + u32 used_bd; /* the number of used bd elements */
1644 +};
1645 +
1646 +struct msdc_host
1647 +{
1648 + struct msdc_hw *hw;
1649 +
1650 + struct mmc_host *mmc; /* mmc structure */
1651 + struct mmc_command *cmd;
1652 + struct mmc_data *data;
1653 + struct mmc_request *mrq;
1654 + int cmd_rsp;
1655 + int cmd_rsp_done;
1656 + int cmd_r1b_done;
1657 +
1658 + int error;
1659 + spinlock_t lock; /* mutex */
1660 + struct semaphore sem;
1661 +
1662 + u32 blksz; /* host block size */
1663 + u32 base; /* host base address */
1664 + int id; /* host id */
1665 + int pwr_ref; /* core power reference count */
1666 +
1667 + u32 xfer_size; /* total transferred size */
1668 +
1669 + struct msdc_dma dma; /* dma channel */
1670 + u32 dma_addr; /* dma transfer address */
1671 + u32 dma_left_size; /* dma transfer left size */
1672 + u32 dma_xfer_size; /* dma transfer size in bytes */
1673 + int dma_xfer; /* dma transfer mode */
1674 +
1675 + u32 timeout_ns; /* data timeout ns */
1676 + u32 timeout_clks; /* data timeout clks */
1677 +
1678 + atomic_t abort; /* abort transfer */
1679 +
1680 + int irq; /* host interrupt */
1681 +
1682 + struct tasklet_struct card_tasklet;
1683 +#if 0
1684 + struct work_struct card_workqueue;
1685 +#else
1686 + struct delayed_work card_delaywork;
1687 +#endif
1688 +
1689 + struct completion cmd_done;
1690 + struct completion xfer_done;
1691 + struct pm_message pm_state;
1692 +
1693 + u32 mclk; /* mmc subsystem clock */
1694 + u32 hclk; /* host clock speed */
1695 + u32 sclk; /* SD/MS clock speed */
1696 + u8 core_clkon; /* Host core clock on ? */
1697 + u8 card_clkon; /* Card clock on ? */
1698 + u8 core_power; /* core power */
1699 + u8 power_mode; /* host power mode */
1700 + u8 card_inserted; /* card inserted ? */
1701 + u8 suspend; /* host suspended ? */
1702 + u8 reserved;
1703 + u8 app_cmd; /* for app command */
1704 + u32 app_cmd_arg;
1705 + u64 starttime;
1706 +};
1707 +
1708 +static inline unsigned int uffs(unsigned int x)
1709 +{
1710 + unsigned int r = 1;
1711 +
1712 + if (!x)
1713 + return 0;
1714 + if (!(x & 0xffff)) {
1715 + x >>= 16;
1716 + r += 16;
1717 + }
1718 + if (!(x & 0xff)) {
1719 + x >>= 8;
1720 + r += 8;
1721 + }
1722 + if (!(x & 0xf)) {
1723 + x >>= 4;
1724 + r += 4;
1725 + }
1726 + if (!(x & 3)) {
1727 + x >>= 2;
1728 + r += 2;
1729 + }
1730 + if (!(x & 1)) {
1731 + x >>= 1;
1732 + r += 1;
1733 + }
1734 + return r;
1735 +}
1736 +#define sdr_read8(reg) __raw_readb(reg)
1737 +#define sdr_read16(reg) __raw_readw(reg)
1738 +#define sdr_read32(reg) __raw_readl(reg)
1739 +#define sdr_write8(reg,val) __raw_writeb(val,reg)
1740 +#define sdr_write16(reg,val) __raw_writew(val,reg)
1741 +#define sdr_write32(reg,val) __raw_writel(val,reg)
1742 +
1743 +#define sdr_set_bits(reg,bs) ((*(volatile u32*)(reg)) |= (u32)(bs))
1744 +#define sdr_clr_bits(reg,bs) ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
1745 +
1746 +#define sdr_set_field(reg,field,val) \
1747 + do { \
1748 + volatile unsigned int tv = sdr_read32(reg); \
1749 + tv &= ~(field); \
1750 + tv |= ((val) << (uffs((unsigned int)field) - 1)); \
1751 + sdr_write32(reg,tv); \
1752 + } while(0)
1753 +#define sdr_get_field(reg,field,val) \
1754 + do { \
1755 + volatile unsigned int tv = sdr_read32(reg); \
1756 + val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
1757 + } while(0)
1758 +
1759 +#endif
1760 +
1761 --- /dev/null
1762 +++ b/drivers/mmc/host/mtk-mmc/sd.c
1763 @@ -0,0 +1,3050 @@
1764 +/* Copyright Statement:
1765 + *
1766 + * This software/firmware and related documentation ("MediaTek Software") are
1767 + * protected under relevant copyright laws. The information contained herein
1768 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
1769 + * Without the prior written permission of MediaTek inc. and/or its licensors,
1770 + * any reproduction, modification, use or disclosure of MediaTek Software,
1771 + * and information contained herein, in whole or in part, shall be strictly prohibited.
1772 + *
1773 + * MediaTek Inc. (C) 2010. All rights reserved.
1774 + *
1775 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1776 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1777 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
1778 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1779 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1780 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1781 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1782 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1783 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
1784 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
1785 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
1786 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
1787 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
1788 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
1789 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1790 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1791 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
1792 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1793 + *
1794 + * The following software/firmware and/or related documentation ("MediaTek Software")
1795 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
1796 + * applicable license agreements with MediaTek Inc.
1797 + */
1798 +
1799 +#include <linux/module.h>
1800 +#include <linux/moduleparam.h>
1801 +#include <linux/init.h>
1802 +#include <linux/spinlock.h>
1803 +#include <linux/timer.h>
1804 +#include <linux/ioport.h>
1805 +#include <linux/device.h>
1806 +#include <linux/platform_device.h>
1807 +#include <linux/interrupt.h>
1808 +#include <linux/delay.h>
1809 +#include <linux/blkdev.h>
1810 +#include <linux/slab.h>
1811 +#include <linux/mmc/host.h>
1812 +#include <linux/mmc/card.h>
1813 +#include <linux/mmc/core.h>
1814 +#include <linux/mmc/mmc.h>
1815 +#include <linux/mmc/sd.h>
1816 +#include <linux/mmc/sdio.h>
1817 +#include <linux/dma-mapping.h>
1818 +
1819 +/* +++ by chhung */
1820 +#include <linux/types.h>
1821 +#include <linux/kernel.h>
1822 +#include <linux/version.h>
1823 +#include <linux/pm.h>
1824 +#include <linux/of.h>
1825 +
1826 +#define MSDC_SMPL_FALLING (1)
1827 +#define MSDC_CD_PIN_EN (1 << 0) /* card detection pin is wired */
1828 +#define MSDC_WP_PIN_EN (1 << 1) /* write protection pin is wired */
1829 +#define MSDC_REMOVABLE (1 << 5) /* removable slot */
1830 +#define MSDC_SYS_SUSPEND (1 << 6) /* suspended by system */
1831 +#define MSDC_HIGHSPEED (1 << 7)
1832 +
1833 +//#define IRQ_SDC 14 //MT7620 /*FIXME*/
1834 +#ifdef CONFIG_SOC_MT7621
1835 +#define RALINK_SYSCTL_BASE 0xbe000000
1836 +#define RALINK_MSDC_BASE 0xbe130000
1837 +#else
1838 +#define RALINK_SYSCTL_BASE 0xb0000000
1839 +#define RALINK_MSDC_BASE 0xb0130000
1840 +#endif
1841 +#define IRQ_SDC 22 /*FIXME*/
1842 +
1843 +#include <asm/dma.h>
1844 +/* end of +++ */
1845 +
1846 +
1847 +#include <asm/mach-ralink/ralink_regs.h>
1848 +
1849 +#if 0 /* --- by chhung */
1850 +#include <mach/board.h>
1851 +#include <mach/mt6575_devs.h>
1852 +#include <mach/mt6575_typedefs.h>
1853 +#include <mach/mt6575_clock_manager.h>
1854 +#include <mach/mt6575_pm_ldo.h>
1855 +//#include <mach/mt6575_pll.h>
1856 +//#include <mach/mt6575_gpio.h>
1857 +//#include <mach/mt6575_gpt_sw.h>
1858 +#include <asm/tcm.h>
1859 +// #include <mach/mt6575_gpt.h>
1860 +#endif /* end of --- */
1861 +
1862 +#include "mt6575_sd.h"
1863 +#include "dbg.h"
1864 +
1865 +/* +++ by chhung */
1866 +#include "board.h"
1867 +/* end of +++ */
1868 +
1869 +#if 0 /* --- by chhung */
1870 +#define isb() __asm__ __volatile__ ("" : : : "memory")
1871 +#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
1872 + : : "r" (0) : "memory")
1873 +#define dmb() __asm__ __volatile__ ("" : : : "memory")
1874 +#endif /* end of --- */
1875 +
1876 +#define DRV_NAME "mtk-sd"
1877 +
1878 +#define HOST_MAX_NUM (1) /* +/- by chhung */
1879 +
1880 +#if defined (CONFIG_SOC_MT7620)
1881 +#define HOST_MAX_MCLK (48000000) /* +/- by chhung */
1882 +#elif defined (CONFIG_SOC_MT7621)
1883 +#define HOST_MAX_MCLK (50000000) /* +/- by chhung */
1884 +#endif
1885 +#define HOST_MIN_MCLK (260000)
1886 +
1887 +#define HOST_MAX_BLKSZ (2048)
1888 +
1889 +#define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
1890 +
1891 +#define GPIO_PULL_DOWN (0)
1892 +#define GPIO_PULL_UP (1)
1893 +
1894 +#if 0 /* --- by chhung */
1895 +#define MSDC_CLKSRC_REG (0xf100000C)
1896 +#define PDN_REG (0xF1000010)
1897 +#endif /* end of --- */
1898 +
1899 +#define DEFAULT_DEBOUNCE (8) /* 8 cycles */
1900 +#define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
1901 +
1902 +#define CMD_TIMEOUT (HZ/10) /* 100ms */
1903 +#define DAT_TIMEOUT (HZ/2 * 5) /* 500ms x5 */
1904 +
1905 +#define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
1906 +
1907 +#define MAX_GPD_NUM (1 + 1) /* one null gpd */
1908 +#define MAX_BD_NUM (1024)
1909 +#define MAX_BD_PER_GPD (MAX_BD_NUM)
1910 +
1911 +#define MAX_HW_SGMTS (MAX_BD_NUM)
1912 +#define MAX_PHY_SGMTS (MAX_BD_NUM)
1913 +#define MAX_SGMT_SZ (MAX_DMA_CNT)
1914 +#define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
1915 +
1916 +#ifdef MT6575_SD_DEBUG
1917 +static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
1918 +#endif
1919 +
1920 +static int mtk_sw_poll;
1921 +
1922 +//=================================
1923 +#define PERI_MSDC0_PDN (15)
1924 +//#define PERI_MSDC1_PDN (16)
1925 +//#define PERI_MSDC2_PDN (17)
1926 +//#define PERI_MSDC3_PDN (18)
1927 +
1928 +struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
1929 +#if 0 /* --- by chhung */
1930 +/* gate means clock power down */
1931 +static int g_clk_gate = 0;
1932 +#define msdc_gate_clock(id) \
1933 + do { \
1934 + g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
1935 + } while(0)
1936 +/* not like power down register. 1 means clock on. */
1937 +#define msdc_ungate_clock(id) \
1938 + do { \
1939 + g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
1940 + } while(0)
1941 +
1942 +// do we need sync object or not
1943 +void msdc_clk_status(int * status)
1944 +{
1945 + *status = g_clk_gate;
1946 +}
1947 +#endif /* end of --- */
1948 +
1949 +/* +++ by chhung */
1950 +struct msdc_hw msdc0_hw = {
1951 + .clk_src = 0,
1952 + .cmd_edge = MSDC_SMPL_FALLING,
1953 + .data_edge = MSDC_SMPL_FALLING,
1954 + .clk_drv = 4,
1955 + .cmd_drv = 4,
1956 + .dat_drv = 4,
1957 + .data_pins = 4,
1958 + .data_offset = 0,
1959 + .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
1960 +// .flags = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
1961 +};
1962 +
1963 +static struct resource mtk_sd_resources[] = {
1964 + [0] = {
1965 + .start = RALINK_MSDC_BASE,
1966 + .end = RALINK_MSDC_BASE+0x3fff,
1967 + .flags = IORESOURCE_MEM,
1968 + },
1969 + [1] = {
1970 + .start = IRQ_SDC, /*FIXME*/
1971 + .end = IRQ_SDC, /*FIXME*/
1972 + .flags = IORESOURCE_IRQ,
1973 + },
1974 +};
1975 +
1976 +static struct platform_device mtk_sd_device = {
1977 + .name = "mtk-sd",
1978 + .id = 0,
1979 + .num_resources = ARRAY_SIZE(mtk_sd_resources),
1980 + .resource = mtk_sd_resources,
1981 +};
1982 +/* end of +++ */
1983 +
1984 +static int msdc_rsp[] = {
1985 + 0, /* RESP_NONE */
1986 + 1, /* RESP_R1 */
1987 + 2, /* RESP_R2 */
1988 + 3, /* RESP_R3 */
1989 + 4, /* RESP_R4 */
1990 + 1, /* RESP_R5 */
1991 + 1, /* RESP_R6 */
1992 + 1, /* RESP_R7 */
1993 + 7, /* RESP_R1b */
1994 +};
1995 +
1996 +/* For Inhanced DMA */
1997 +#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
1998 + do { \
1999 + ((gpd_t*)gpd)->extlen = extlen; \
2000 + ((gpd_t*)gpd)->cmd = cmd; \
2001 + ((gpd_t*)gpd)->arg = arg; \
2002 + ((gpd_t*)gpd)->blknum = blknum; \
2003 + }while(0)
2004 +
2005 +#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
2006 + do { \
2007 + BUG_ON(dlen > 0xFFFFUL); \
2008 + ((bd_t*)bd)->blkpad = blkpad; \
2009 + ((bd_t*)bd)->dwpad = dwpad; \
2010 + ((bd_t*)bd)->ptr = (void*)dptr; \
2011 + ((bd_t*)bd)->buflen = dlen; \
2012 + }while(0)
2013 +
2014 +#define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
2015 +#define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
2016 +#define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
2017 +#define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
2018 +#define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
2019 +#define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
2020 +
2021 +
2022 +#define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
2023 +#define msdc_dma_off() sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
2024 +
2025 +#define msdc_retry(expr,retry,cnt) \
2026 + do { \
2027 + int backup = cnt; \
2028 + while (retry) { \
2029 + if (!(expr)) break; \
2030 + if (cnt-- == 0) { \
2031 + retry--; mdelay(1); cnt = backup; \
2032 + } \
2033 + } \
2034 + WARN_ON(retry == 0); \
2035 + } while(0)
2036 +
2037 +#if 0 /* --- by chhung */
2038 +#define msdc_reset() \
2039 + do { \
2040 + int retry = 3, cnt = 1000; \
2041 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2042 + dsb(); \
2043 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2044 + } while(0)
2045 +#else
2046 +#define msdc_reset() \
2047 + do { \
2048 + int retry = 3, cnt = 1000; \
2049 + sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
2050 + msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
2051 + } while(0)
2052 +#endif /* end of +/- */
2053 +
2054 +#define msdc_clr_int() \
2055 + do { \
2056 + volatile u32 val = sdr_read32(MSDC_INT); \
2057 + sdr_write32(MSDC_INT, val); \
2058 + } while(0)
2059 +
2060 +#define msdc_clr_fifo() \
2061 + do { \
2062 + int retry = 3, cnt = 1000; \
2063 + sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
2064 + msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
2065 + } while(0)
2066 +
2067 +#define msdc_irq_save(val) \
2068 + do { \
2069 + val = sdr_read32(MSDC_INTEN); \
2070 + sdr_clr_bits(MSDC_INTEN, val); \
2071 + } while(0)
2072 +
2073 +#define msdc_irq_restore(val) \
2074 + do { \
2075 + sdr_set_bits(MSDC_INTEN, val); \
2076 + } while(0)
2077 +
2078 +/* clock source for host: global */
2079 +#if defined (CONFIG_SOC_MT7620)
2080 +static u32 hclks[] = {48000000}; /* +/- by chhung */
2081 +#elif defined (CONFIG_SOC_MT7621)
2082 +static u32 hclks[] = {50000000}; /* +/- by chhung */
2083 +#endif
2084 +
2085 +//============================================
2086 +// the power for msdc host controller: global
2087 +// always keep the VMC on.
2088 +//============================================
2089 +#define msdc_vcore_on(host) \
2090 + do { \
2091 + INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
2092 + (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
2093 + } while (0)
2094 +#define msdc_vcore_off(host) \
2095 + do { \
2096 + INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
2097 + (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
2098 + } while (0)
2099 +
2100 +//====================================
2101 +// the vdd output for card: global
2102 +// always keep the VMCH on.
2103 +//====================================
2104 +#define msdc_vdd_on(host) \
2105 + do { \
2106 + (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
2107 + } while (0)
2108 +#define msdc_vdd_off(host) \
2109 + do { \
2110 + (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
2111 + } while (0)
2112 +
2113 +#define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
2114 +#define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
2115 +
2116 +#define sdc_send_cmd(cmd,arg) \
2117 + do { \
2118 + sdr_write32(SDC_ARG, (arg)); \
2119 + sdr_write32(SDC_CMD, (cmd)); \
2120 + } while(0)
2121 +
2122 +// can modify to read h/w register.
2123 +//#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
2124 +#define is_card_present(h) (((struct msdc_host*)(h))->card_inserted)
2125 +
2126 +/* +++ by chhung */
2127 +#ifndef __ASSEMBLY__
2128 +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
2129 +#else
2130 +#define PHYSADDR(a) ((a) & 0x1fffffff)
2131 +#endif
2132 +/* end of +++ */
2133 +static unsigned int msdc_do_command(struct msdc_host *host,
2134 + struct mmc_command *cmd,
2135 + int tune,
2136 + unsigned long timeout);
2137 +
2138 +static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
2139 +
2140 +#ifdef MT6575_SD_DEBUG
2141 +static void msdc_dump_card_status(struct msdc_host *host, u32 status)
2142 +{
2143 + static char *state[] = {
2144 + "Idle", /* 0 */
2145 + "Ready", /* 1 */
2146 + "Ident", /* 2 */
2147 + "Stby", /* 3 */
2148 + "Tran", /* 4 */
2149 + "Data", /* 5 */
2150 + "Rcv", /* 6 */
2151 + "Prg", /* 7 */
2152 + "Dis", /* 8 */
2153 + "Reserved", /* 9 */
2154 + "Reserved", /* 10 */
2155 + "Reserved", /* 11 */
2156 + "Reserved", /* 12 */
2157 + "Reserved", /* 13 */
2158 + "Reserved", /* 14 */
2159 + "I/O mode", /* 15 */
2160 + };
2161 + if (status & R1_OUT_OF_RANGE)
2162 + N_MSG(RSP, "[CARD_STATUS] Out of Range");
2163 + if (status & R1_ADDRESS_ERROR)
2164 + N_MSG(RSP, "[CARD_STATUS] Address Error");
2165 + if (status & R1_BLOCK_LEN_ERROR)
2166 + N_MSG(RSP, "[CARD_STATUS] Block Len Error");
2167 + if (status & R1_ERASE_SEQ_ERROR)
2168 + N_MSG(RSP, "[CARD_STATUS] Erase Seq Error");
2169 + if (status & R1_ERASE_PARAM)
2170 + N_MSG(RSP, "[CARD_STATUS] Erase Param");
2171 + if (status & R1_WP_VIOLATION)
2172 + N_MSG(RSP, "[CARD_STATUS] WP Violation");
2173 + if (status & R1_CARD_IS_LOCKED)
2174 + N_MSG(RSP, "[CARD_STATUS] Card is Locked");
2175 + if (status & R1_LOCK_UNLOCK_FAILED)
2176 + N_MSG(RSP, "[CARD_STATUS] Lock/Unlock Failed");
2177 + if (status & R1_COM_CRC_ERROR)
2178 + N_MSG(RSP, "[CARD_STATUS] Command CRC Error");
2179 + if (status & R1_ILLEGAL_COMMAND)
2180 + N_MSG(RSP, "[CARD_STATUS] Illegal Command");
2181 + if (status & R1_CARD_ECC_FAILED)
2182 + N_MSG(RSP, "[CARD_STATUS] Card ECC Failed");
2183 + if (status & R1_CC_ERROR)
2184 + N_MSG(RSP, "[CARD_STATUS] CC Error");
2185 + if (status & R1_ERROR)
2186 + N_MSG(RSP, "[CARD_STATUS] Error");
2187 + if (status & R1_UNDERRUN)
2188 + N_MSG(RSP, "[CARD_STATUS] Underrun");
2189 + if (status & R1_OVERRUN)
2190 + N_MSG(RSP, "[CARD_STATUS] Overrun");
2191 + if (status & R1_CID_CSD_OVERWRITE)
2192 + N_MSG(RSP, "[CARD_STATUS] CID/CSD Overwrite");
2193 + if (status & R1_WP_ERASE_SKIP)
2194 + N_MSG(RSP, "[CARD_STATUS] WP Eraser Skip");
2195 + if (status & R1_CARD_ECC_DISABLED)
2196 + N_MSG(RSP, "[CARD_STATUS] Card ECC Disabled");
2197 + if (status & R1_ERASE_RESET)
2198 + N_MSG(RSP, "[CARD_STATUS] Erase Reset");
2199 + if (status & R1_READY_FOR_DATA)
2200 + N_MSG(RSP, "[CARD_STATUS] Ready for Data");
2201 + if (status & R1_SWITCH_ERROR)
2202 + N_MSG(RSP, "[CARD_STATUS] Switch error");
2203 + if (status & R1_APP_CMD)
2204 + N_MSG(RSP, "[CARD_STATUS] App Command");
2205 +
2206 + N_MSG(RSP, "[CARD_STATUS] '%s' State", state[R1_CURRENT_STATE(status)]);
2207 +}
2208 +
2209 +static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
2210 +{
2211 + if (resp & (1 << 7))
2212 + N_MSG(RSP, "[OCR] Low Voltage Range");
2213 + if (resp & (1 << 15))
2214 + N_MSG(RSP, "[OCR] 2.7-2.8 volt");
2215 + if (resp & (1 << 16))
2216 + N_MSG(RSP, "[OCR] 2.8-2.9 volt");
2217 + if (resp & (1 << 17))
2218 + N_MSG(RSP, "[OCR] 2.9-3.0 volt");
2219 + if (resp & (1 << 18))
2220 + N_MSG(RSP, "[OCR] 3.0-3.1 volt");
2221 + if (resp & (1 << 19))
2222 + N_MSG(RSP, "[OCR] 3.1-3.2 volt");
2223 + if (resp & (1 << 20))
2224 + N_MSG(RSP, "[OCR] 3.2-3.3 volt");
2225 + if (resp & (1 << 21))
2226 + N_MSG(RSP, "[OCR] 3.3-3.4 volt");
2227 + if (resp & (1 << 22))
2228 + N_MSG(RSP, "[OCR] 3.4-3.5 volt");
2229 + if (resp & (1 << 23))
2230 + N_MSG(RSP, "[OCR] 3.5-3.6 volt");
2231 + if (resp & (1 << 24))
2232 + N_MSG(RSP, "[OCR] Switching to 1.8V Accepted (S18A)");
2233 + if (resp & (1 << 30))
2234 + N_MSG(RSP, "[OCR] Card Capacity Status (CCS)");
2235 + if (resp & (1 << 31))
2236 + N_MSG(RSP, "[OCR] Card Power Up Status (Idle)");
2237 + else
2238 + N_MSG(RSP, "[OCR] Card Power Up Status (Busy)");
2239 +}
2240 +
2241 +static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
2242 +{
2243 + u32 status = (((resp >> 15) & 0x1) << 23) |
2244 + (((resp >> 14) & 0x1) << 22) |
2245 + (((resp >> 13) & 0x1) << 19) |
2246 + (resp & 0x1fff);
2247 +
2248 + N_MSG(RSP, "[RCA] 0x%.4x", resp >> 16);
2249 + msdc_dump_card_status(host, status);
2250 +}
2251 +
2252 +static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
2253 +{
2254 + u32 flags = (resp >> 8) & 0xFF;
2255 + char *state[] = {"DIS", "CMD", "TRN", "RFU"};
2256 +
2257 + if (flags & (1 << 7))
2258 + N_MSG(RSP, "[IO] COM_CRC_ERR");
2259 + if (flags & (1 << 6))
2260 + N_MSG(RSP, "[IO] Illgal command");
2261 + if (flags & (1 << 3))
2262 + N_MSG(RSP, "[IO] Error");
2263 + if (flags & (1 << 2))
2264 + N_MSG(RSP, "[IO] RFU");
2265 + if (flags & (1 << 1))
2266 + N_MSG(RSP, "[IO] Function number error");
2267 + if (flags & (1 << 0))
2268 + N_MSG(RSP, "[IO] Out of range");
2269 +
2270 + N_MSG(RSP, "[IO] State: %s, Data:0x%x", state[(resp >> 12) & 0x3], resp & 0xFF);
2271 +}
2272 +#endif
2273 +
2274 +static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
2275 +{
2276 + u32 base = host->base;
2277 + u32 timeout, clk_ns;
2278 +
2279 + host->timeout_ns = ns;
2280 + host->timeout_clks = clks;
2281 +
2282 + clk_ns = 1000000000UL / host->sclk;
2283 + timeout = ns / clk_ns + clks;
2284 + timeout = timeout >> 16; /* in 65536 sclk cycle unit */
2285 + timeout = timeout > 1 ? timeout - 1 : 0;
2286 + timeout = timeout > 255 ? 255 : timeout;
2287 +
2288 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
2289 +
2290 + N_MSG(OPS, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
2291 + ns, clks, timeout + 1);
2292 +}
2293 +
2294 +/* msdc_eirq_sdio() will be called when EIRQ(for WIFI) */
2295 +static void msdc_eirq_sdio(void *data)
2296 +{
2297 + struct msdc_host *host = (struct msdc_host *)data;
2298 +
2299 + N_MSG(INT, "SDIO EINT");
2300 +
2301 + mmc_signal_sdio_irq(host->mmc);
2302 +}
2303 +
2304 +/* msdc_eirq_cd will not be used! We not using EINT for card detection. */
2305 +static void msdc_eirq_cd(void *data)
2306 +{
2307 + struct msdc_host *host = (struct msdc_host *)data;
2308 +
2309 + N_MSG(INT, "CD EINT");
2310 +
2311 +#if 0
2312 + tasklet_hi_schedule(&host->card_tasklet);
2313 +#else
2314 + schedule_delayed_work(&host->card_delaywork, HZ);
2315 +#endif
2316 +}
2317 +
2318 +#if 0
2319 +static void msdc_tasklet_card(unsigned long arg)
2320 +{
2321 + struct msdc_host *host = (struct msdc_host *)arg;
2322 +#else
2323 +static void msdc_tasklet_card(struct work_struct *work)
2324 +{
2325 + struct msdc_host *host = (struct msdc_host *)container_of(work,
2326 + struct msdc_host, card_delaywork.work);
2327 +#endif
2328 + struct msdc_hw *hw = host->hw;
2329 + u32 base = host->base;
2330 + u32 inserted;
2331 + u32 status = 0;
2332 + //u32 change = 0;
2333 +
2334 + spin_lock(&host->lock);
2335 +
2336 + if (hw->get_cd_status) { // NULL
2337 + inserted = hw->get_cd_status();
2338 + } else {
2339 + status = sdr_read32(MSDC_PS);
2340 + inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
2341 + }
2342 +
2343 +#if 0
2344 + change = host->card_inserted ^ inserted;
2345 + host->card_inserted = inserted;
2346 +
2347 + if (change && !host->suspend) {
2348 + if (inserted) {
2349 + host->mmc->f_max = HOST_MAX_MCLK; // work around
2350 + }
2351 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2352 + }
2353 +#else /* Make sure: handle the last interrupt */
2354 + host->card_inserted = inserted;
2355 +
2356 + if (!host->suspend) {
2357 + host->mmc->f_max = HOST_MAX_MCLK;
2358 + mmc_detect_change(host->mmc, msecs_to_jiffies(20));
2359 + }
2360 +
2361 + IRQ_MSG("card found<%s>", inserted ? "inserted" : "removed");
2362 +#endif
2363 +
2364 + spin_unlock(&host->lock);
2365 +}
2366 +
2367 +#if 0 /* --- by chhung */
2368 +/* For E2 only */
2369 +static u8 clk_src_bit[4] = {
2370 + 0, 3, 5, 7
2371 +};
2372 +
2373 +static void msdc_select_clksrc(struct msdc_host* host, unsigned char clksrc)
2374 +{
2375 + u32 val;
2376 + u32 base = host->base;
2377 +
2378 + BUG_ON(clksrc > 3);
2379 + INIT_MSG("set clock source to <%d>", clksrc);
2380 +
2381 + val = sdr_read32(MSDC_CLKSRC_REG);
2382 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
2383 + val &= ~(0x3 << clk_src_bit[host->id]);
2384 + val |= clksrc << clk_src_bit[host->id];
2385 + } else {
2386 + val &= ~0x3; val |= clksrc;
2387 + }
2388 + sdr_write32(MSDC_CLKSRC_REG, val);
2389 +
2390 + host->hclk = hclks[clksrc];
2391 + host->hw->clk_src = clksrc;
2392 +}
2393 +#endif /* end of --- */
2394 +
2395 +static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
2396 +{
2397 + //struct msdc_hw *hw = host->hw;
2398 + u32 base = host->base;
2399 + u32 mode;
2400 + u32 flags;
2401 + u32 div;
2402 + u32 sclk;
2403 + u32 hclk = host->hclk;
2404 + //u8 clksrc = hw->clk_src;
2405 +
2406 + if (!hz) { // set mmc system clock to 0 ?
2407 + //ERR_MSG("set mclk to 0!!!");
2408 + msdc_reset();
2409 + return;
2410 + }
2411 +
2412 + msdc_irq_save(flags);
2413 +
2414 +#if defined (CONFIG_MT7621_FPGA) || defined (CONFIG_MT7628_FPGA)
2415 + mode = 0x0; /* use divisor */
2416 + if (hz >= (hclk >> 1)) {
2417 + div = 0; /* mean div = 1/2 */
2418 + sclk = hclk >> 1; /* sclk = clk / 2 */
2419 + } else {
2420 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2421 + sclk = (hclk >> 2) / div;
2422 + }
2423 +#else
2424 + if (ddr) {
2425 + mode = 0x2; /* ddr mode and use divisor */
2426 + if (hz >= (hclk >> 2)) {
2427 + div = 1; /* mean div = 1/4 */
2428 + sclk = hclk >> 2; /* sclk = clk / 4 */
2429 + } else {
2430 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2431 + sclk = (hclk >> 2) / div;
2432 + }
2433 + } else if (hz >= hclk) { /* bug fix */
2434 + mode = 0x1; /* no divisor and divisor is ignored */
2435 + div = 0;
2436 + sclk = hclk;
2437 + } else {
2438 + mode = 0x0; /* use divisor */
2439 + if (hz >= (hclk >> 1)) {
2440 + div = 0; /* mean div = 1/2 */
2441 + sclk = hclk >> 1; /* sclk = clk / 2 */
2442 + } else {
2443 + div = (hclk + ((hz << 2) - 1)) / (hz << 2);
2444 + sclk = (hclk >> 2) / div;
2445 + }
2446 + }
2447 +#endif
2448 + /* set clock mode and divisor */
2449 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
2450 + sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
2451 +
2452 + /* wait clock stable */
2453 + while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
2454 +
2455 + host->sclk = sclk;
2456 + host->mclk = hz;
2457 + msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); // need?
2458 +
2459 + INIT_MSG("================");
2460 + INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz/1000, hclk/1000, sclk/1000);
2461 + INIT_MSG("================");
2462 +
2463 + msdc_irq_restore(flags);
2464 +}
2465 +
2466 +/* Fix me. when need to abort */
2467 +static void msdc_abort_data(struct msdc_host *host)
2468 +{
2469 + u32 base = host->base;
2470 + struct mmc_command *stop = host->mrq->stop;
2471 +
2472 + ERR_MSG("Need to Abort. dma<%d>", host->dma_xfer);
2473 +
2474 + msdc_reset();
2475 + msdc_clr_fifo();
2476 + msdc_clr_int();
2477 +
2478 + // need to check FIFO count 0 ?
2479 +
2480 + if (stop) { /* try to stop, but may not success */
2481 + ERR_MSG("stop when abort CMD<%d>", stop->opcode);
2482 + (void)msdc_do_command(host, stop, 0, CMD_TIMEOUT);
2483 + }
2484 +
2485 + //if (host->mclk >= 25000000) {
2486 + // msdc_set_mclk(host, 0, host->mclk >> 1);
2487 + //}
2488 +}
2489 +
2490 +#if 0 /* --- by chhung */
2491 +static void msdc_pin_config(struct msdc_host *host, int mode)
2492 +{
2493 + struct msdc_hw *hw = host->hw;
2494 + u32 base = host->base;
2495 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2496 +
2497 + /* Config WP pin */
2498 + if (hw->flags & MSDC_WP_PIN_EN) {
2499 + if (hw->config_gpio_pin) /* NULL */
2500 + hw->config_gpio_pin(MSDC_WP_PIN, pull);
2501 + }
2502 +
2503 + switch (mode) {
2504 + case MSDC_PIN_PULL_UP:
2505 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
2506 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2507 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 1);
2508 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2509 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 1);
2510 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2511 + break;
2512 + case MSDC_PIN_PULL_DOWN:
2513 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2514 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
2515 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2516 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 1);
2517 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2518 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 1);
2519 + break;
2520 + case MSDC_PIN_PULL_NONE:
2521 + default:
2522 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
2523 + //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
2524 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPU, 0);
2525 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDPD, 0);
2526 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPU, 0);
2527 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATPD, 0);
2528 + break;
2529 + }
2530 +
2531 + N_MSG(CFG, "Pins mode(%d), down(%d), up(%d)",
2532 + mode, MSDC_PIN_PULL_DOWN, MSDC_PIN_PULL_UP);
2533 +}
2534 +
2535 +void msdc_pin_reset(struct msdc_host *host, int mode)
2536 +{
2537 + struct msdc_hw *hw = (struct msdc_hw *)host->hw;
2538 + u32 base = host->base;
2539 + int pull = (mode == MSDC_PIN_PULL_UP) ? GPIO_PULL_UP : GPIO_PULL_DOWN;
2540 +
2541 + /* Config reset pin */
2542 + if (hw->flags & MSDC_RST_PIN_EN) {
2543 + if (hw->config_gpio_pin) /* NULL */
2544 + hw->config_gpio_pin(MSDC_RST_PIN, pull);
2545 +
2546 + if (mode == MSDC_PIN_PULL_UP) {
2547 + sdr_clr_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2548 + } else {
2549 + sdr_set_bits(EMMC_IOCON, EMMC_IOCON_BOOTRST);
2550 + }
2551 + }
2552 +}
2553 +
2554 +static void msdc_core_power(struct msdc_host *host, int on)
2555 +{
2556 + N_MSG(CFG, "Turn %s %s power (copower: %d -> %d)",
2557 + on ? "on" : "off", "core", host->core_power, on);
2558 +
2559 + if (on && host->core_power == 0) {
2560 + msdc_vcore_on(host);
2561 + host->core_power = 1;
2562 + msleep(1);
2563 + } else if (!on && host->core_power == 1) {
2564 + msdc_vcore_off(host);
2565 + host->core_power = 0;
2566 + msleep(1);
2567 + }
2568 +}
2569 +
2570 +static void msdc_host_power(struct msdc_host *host, int on)
2571 +{
2572 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "host");
2573 +
2574 + if (on) {
2575 + //msdc_core_power(host, 1); // need do card detection.
2576 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
2577 + } else {
2578 + msdc_pin_reset(host, MSDC_PIN_PULL_DOWN);
2579 + //msdc_core_power(host, 0);
2580 + }
2581 +}
2582 +
2583 +static void msdc_card_power(struct msdc_host *host, int on)
2584 +{
2585 + N_MSG(CFG, "Turn %s %s power ", on ? "on" : "off", "card");
2586 +
2587 + if (on) {
2588 + msdc_pin_config(host, MSDC_PIN_PULL_UP);
2589 + if (host->hw->ext_power_on) {
2590 + host->hw->ext_power_on();
2591 + } else {
2592 + //msdc_vdd_on(host); // need todo card detection.
2593 + }
2594 + msleep(1);
2595 + } else {
2596 + if (host->hw->ext_power_off) {
2597 + host->hw->ext_power_off();
2598 + } else {
2599 + //msdc_vdd_off(host);
2600 + }
2601 + msdc_pin_config(host, MSDC_PIN_PULL_DOWN);
2602 + msleep(1);
2603 + }
2604 +}
2605 +
2606 +static void msdc_set_power_mode(struct msdc_host *host, u8 mode)
2607 +{
2608 + N_MSG(CFG, "Set power mode(%d)", mode);
2609 +
2610 + if (host->power_mode == MMC_POWER_OFF && mode != MMC_POWER_OFF) {
2611 + msdc_host_power(host, 1);
2612 + msdc_card_power(host, 1);
2613 + } else if (host->power_mode != MMC_POWER_OFF && mode == MMC_POWER_OFF) {
2614 + msdc_card_power(host, 0);
2615 + msdc_host_power(host, 0);
2616 + }
2617 + host->power_mode = mode;
2618 +}
2619 +#endif /* end of --- */
2620 +
2621 +#ifdef CONFIG_PM
2622 +/*
2623 + register as callback function of WIFI(combo_sdio_register_pm) .
2624 + can called by msdc_drv_suspend/resume too.
2625 +*/
2626 +static void msdc_pm(pm_message_t state, void *data)
2627 +{
2628 + struct msdc_host *host = (struct msdc_host *)data;
2629 + int evt = state.event;
2630 +
2631 + if (evt == PM_EVENT_USER_RESUME || evt == PM_EVENT_USER_SUSPEND) {
2632 + INIT_MSG("USR_%s: suspend<%d> power<%d>",
2633 + evt == PM_EVENT_USER_RESUME ? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
2634 + host->suspend, host->power_mode);
2635 + }
2636 +
2637 + if (evt == PM_EVENT_SUSPEND || evt == PM_EVENT_USER_SUSPEND) {
2638 + if (host->suspend) /* already suspend */ /* default 0*/
2639 + return;
2640 +
2641 + /* for memory card. already power off by mmc */
2642 + if (evt == PM_EVENT_SUSPEND && host->power_mode == MMC_POWER_OFF)
2643 + return;
2644 +
2645 + host->suspend = 1;
2646 + host->pm_state = state; /* default PMSG_RESUME */
2647 +
2648 + INIT_MSG("%s Suspend", evt == PM_EVENT_SUSPEND ? "PM" : "USR");
2649 + if(host->hw->flags & MSDC_SYS_SUSPEND) /* set for card */
2650 + (void)mmc_suspend_host(host->mmc);
2651 + else {
2652 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* just for double confirm */ /* --- by chhung */
2653 + mmc_remove_host(host->mmc);
2654 + }
2655 + } else if (evt == PM_EVENT_RESUME || evt == PM_EVENT_USER_RESUME) {
2656 + if (!host->suspend){
2657 + //ERR_MSG("warning: already resume");
2658 + return;
2659 + }
2660 +
2661 + /* No PM resume when USR suspend */
2662 + if (evt == PM_EVENT_RESUME && host->pm_state.event == PM_EVENT_USER_SUSPEND) {
2663 + ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
2664 + return;
2665 + }
2666 +
2667 + host->suspend = 0;
2668 + host->pm_state = state;
2669 +
2670 + INIT_MSG("%s Resume", evt == PM_EVENT_RESUME ? "PM" : "USR");
2671 + if(host->hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
2672 + (void)mmc_resume_host(host->mmc);
2673 + }
2674 + else {
2675 + // host->mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* --- by chhung */
2676 + mmc_add_host(host->mmc);
2677 + }
2678 + }
2679 +}
2680 +#endif
2681 +
2682 +/*--------------------------------------------------------------------------*/
2683 +/* mmc_host_ops members */
2684 +/*--------------------------------------------------------------------------*/
2685 +static unsigned int msdc_command_start(struct msdc_host *host,
2686 + struct mmc_command *cmd,
2687 + int tune, /* not used */
2688 + unsigned long timeout)
2689 +{
2690 + u32 base = host->base;
2691 + u32 opcode = cmd->opcode;
2692 + u32 rawcmd;
2693 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2694 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2695 + MSDC_INT_ACMD19_DONE;
2696 +
2697 + u32 resp;
2698 + unsigned long tmo;
2699 +
2700 + /* Protocol layer does not provide response type, but our hardware needs
2701 + * to know exact type, not just size!
2702 + */
2703 + if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
2704 + resp = RESP_R3;
2705 + else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
2706 + resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
2707 + else if (opcode == MMC_FAST_IO)
2708 + resp = RESP_R4;
2709 + else if (opcode == MMC_GO_IRQ_STATE)
2710 + resp = RESP_R5;
2711 + else if (opcode == MMC_SELECT_CARD)
2712 + resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
2713 + else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
2714 + resp = RESP_R1; /* SDIO workaround. */
2715 + else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
2716 + resp = RESP_R1;
2717 + else {
2718 + switch (mmc_resp_type(cmd)) {
2719 + case MMC_RSP_R1:
2720 + resp = RESP_R1;
2721 + break;
2722 + case MMC_RSP_R1B:
2723 + resp = RESP_R1B;
2724 + break;
2725 + case MMC_RSP_R2:
2726 + resp = RESP_R2;
2727 + break;
2728 + case MMC_RSP_R3:
2729 + resp = RESP_R3;
2730 + break;
2731 + case MMC_RSP_NONE:
2732 + default:
2733 + resp = RESP_NONE;
2734 + break;
2735 + }
2736 + }
2737 +
2738 + cmd->error = 0;
2739 + /* rawcmd :
2740 + * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
2741 + * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
2742 + */
2743 + rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
2744 +
2745 + if (opcode == MMC_READ_MULTIPLE_BLOCK) {
2746 + rawcmd |= (2 << 11);
2747 + } else if (opcode == MMC_READ_SINGLE_BLOCK) {
2748 + rawcmd |= (1 << 11);
2749 + } else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
2750 + rawcmd |= ((2 << 11) | (1 << 13));
2751 + } else if (opcode == MMC_WRITE_BLOCK) {
2752 + rawcmd |= ((1 << 11) | (1 << 13));
2753 + } else if (opcode == SD_IO_RW_EXTENDED) {
2754 + if (cmd->data->flags & MMC_DATA_WRITE)
2755 + rawcmd |= (1 << 13);
2756 + if (cmd->data->blocks > 1)
2757 + rawcmd |= (2 << 11);
2758 + else
2759 + rawcmd |= (1 << 11);
2760 + } else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
2761 + rawcmd |= (1 << 14);
2762 + } else if ((opcode == SD_APP_SEND_SCR) ||
2763 + (opcode == SD_APP_SEND_NUM_WR_BLKS) ||
2764 + (opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2765 + (opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
2766 + (opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
2767 + rawcmd |= (1 << 11);
2768 + } else if (opcode == MMC_STOP_TRANSMISSION) {
2769 + rawcmd |= (1 << 14);
2770 + rawcmd &= ~(0x0FFF << 16);
2771 + }
2772 +
2773 + N_MSG(CMD, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode , rawcmd, cmd->arg);
2774 +
2775 + tmo = jiffies + timeout;
2776 +
2777 + if (opcode == MMC_SEND_STATUS) {
2778 + for (;;) {
2779 + if (!sdc_is_cmd_busy())
2780 + break;
2781 +
2782 + if (time_after(jiffies, tmo)) {
2783 + ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode);
2784 + cmd->error = (unsigned int)-ETIMEDOUT;
2785 + msdc_reset();
2786 + goto end;
2787 + }
2788 + }
2789 + }else {
2790 + for (;;) {
2791 + if (!sdc_is_busy())
2792 + break;
2793 + if (time_after(jiffies, tmo)) {
2794 + ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode);
2795 + cmd->error = (unsigned int)-ETIMEDOUT;
2796 + msdc_reset();
2797 + goto end;
2798 + }
2799 + }
2800 + }
2801 +
2802 + //BUG_ON(in_interrupt());
2803 + host->cmd = cmd;
2804 + host->cmd_rsp = resp;
2805 +
2806 + init_completion(&host->cmd_done);
2807 +
2808 + sdr_set_bits(MSDC_INTEN, wints);
2809 + sdc_send_cmd(rawcmd, cmd->arg);
2810 +
2811 +end:
2812 + return cmd->error;
2813 +}
2814 +
2815 +static unsigned int msdc_command_resp(struct msdc_host *host,
2816 + struct mmc_command *cmd,
2817 + int tune,
2818 + unsigned long timeout)
2819 +{
2820 + u32 base = host->base;
2821 + u32 opcode = cmd->opcode;
2822 + //u32 rawcmd;
2823 + u32 resp;
2824 + u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
2825 + MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
2826 + MSDC_INT_ACMD19_DONE;
2827 +
2828 + resp = host->cmd_rsp;
2829 +
2830 + BUG_ON(in_interrupt());
2831 + //init_completion(&host->cmd_done);
2832 + //sdr_set_bits(MSDC_INTEN, wints);
2833 +
2834 + spin_unlock(&host->lock);
2835 + if(!wait_for_completion_timeout(&host->cmd_done, 10*timeout)){
2836 + ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode, cmd->arg);
2837 + cmd->error = (unsigned int)-ETIMEDOUT;
2838 + msdc_reset();
2839 + }
2840 + spin_lock(&host->lock);
2841 +
2842 + sdr_clr_bits(MSDC_INTEN, wints);
2843 + host->cmd = NULL;
2844 +
2845 +//end:
2846 +#ifdef MT6575_SD_DEBUG
2847 + switch (resp) {
2848 + case RESP_NONE:
2849 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)", opcode, cmd->error, resp);
2850 + break;
2851 + case RESP_R2:
2852 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
2853 + opcode, cmd->error, resp, cmd->resp[0], cmd->resp[1],
2854 + cmd->resp[2], cmd->resp[3]);
2855 + break;
2856 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
2857 + N_MSG(RSP, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
2858 + opcode, cmd->error, resp, cmd->resp[0]);
2859 + if (cmd->error == 0) {
2860 + switch (resp) {
2861 + case RESP_R1:
2862 + case RESP_R1B:
2863 + msdc_dump_card_status(host, cmd->resp[0]);
2864 + break;
2865 + case RESP_R3:
2866 + msdc_dump_ocr_reg(host, cmd->resp[0]);
2867 + break;
2868 + case RESP_R5:
2869 + msdc_dump_io_resp(host, cmd->resp[0]);
2870 + break;
2871 + case RESP_R6:
2872 + msdc_dump_rca_resp(host, cmd->resp[0]);
2873 + break;
2874 + }
2875 + }
2876 + break;
2877 + }
2878 +#endif
2879 +
2880 + /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
2881 +
2882 + if (!tune) {
2883 + return cmd->error;
2884 + }
2885 +
2886 + /* memory card CRC */
2887 + if(host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
2888 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
2889 + msdc_abort_data(host);
2890 + } else {
2891 + /* do basic: reset*/
2892 + msdc_reset();
2893 + msdc_clr_fifo();
2894 + msdc_clr_int();
2895 + }
2896 + cmd->error = msdc_tune_cmdrsp(host,cmd);
2897 + }
2898 +
2899 + // check DAT0
2900 + /* if (resp == RESP_R1B) {
2901 + while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
2902 + } */
2903 + /* CMD12 Error Handle */
2904 +
2905 + return cmd->error;
2906 +}
2907 +
2908 +static unsigned int msdc_do_command(struct msdc_host *host,
2909 + struct mmc_command *cmd,
2910 + int tune,
2911 + unsigned long timeout)
2912 +{
2913 + if (msdc_command_start(host, cmd, tune, timeout))
2914 + goto end;
2915 +
2916 + if (msdc_command_resp(host, cmd, tune, timeout))
2917 + goto end;
2918 +
2919 +end:
2920 +
2921 + N_MSG(CMD, " return<%d> resp<0x%.8x>", cmd->error, cmd->resp[0]);
2922 + return cmd->error;
2923 +}
2924 +
2925 +/* The abort condition when PIO read/write
2926 + tmo:
2927 +*/
2928 +static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
2929 +{
2930 + int ret = 0;
2931 + u32 base = host->base;
2932 +
2933 + if (atomic_read(&host->abort)) {
2934 + ret = 1;
2935 + }
2936 +
2937 + if (time_after(jiffies, tmo)) {
2938 + data->error = (unsigned int)-ETIMEDOUT;
2939 + ERR_MSG("XXX PIO Data Timeout: CMD<%d>", host->mrq->cmd->opcode);
2940 + ret = 1;
2941 + }
2942 +
2943 + if(ret) {
2944 + msdc_reset();
2945 + msdc_clr_fifo();
2946 + msdc_clr_int();
2947 + ERR_MSG("msdc pio find abort");
2948 + }
2949 + return ret;
2950 +}
2951 +
2952 +/*
2953 + Need to add a timeout, or WDT timeout, system reboot.
2954 +*/
2955 +// pio mode data read/write
2956 +static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
2957 +{
2958 + struct scatterlist *sg = data->sg;
2959 + u32 base = host->base;
2960 + u32 num = data->sg_len;
2961 + u32 *ptr;
2962 + u8 *u8ptr;
2963 + u32 left = 0;
2964 + u32 count, size = 0;
2965 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
2966 + unsigned long tmo = jiffies + DAT_TIMEOUT;
2967 +
2968 + sdr_set_bits(MSDC_INTEN, wints);
2969 + while (num) {
2970 + left = sg_dma_len(sg);
2971 + ptr = sg_virt(sg);
2972 + while (left) {
2973 + if ((left >= MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
2974 + count = MSDC_FIFO_THD >> 2;
2975 + do {
2976 + *ptr++ = msdc_fifo_read32();
2977 + } while (--count);
2978 + left -= MSDC_FIFO_THD;
2979 + } else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
2980 + while (left > 3) {
2981 + *ptr++ = msdc_fifo_read32();
2982 + left -= 4;
2983 + }
2984 +
2985 + u8ptr = (u8 *)ptr;
2986 + while(left) {
2987 + * u8ptr++ = msdc_fifo_read8();
2988 + left--;
2989 + }
2990 + }
2991 +
2992 + if (msdc_pio_abort(host, data, tmo)) {
2993 + goto end;
2994 + }
2995 + }
2996 + size += sg_dma_len(sg);
2997 + sg = sg_next(sg); num--;
2998 + }
2999 +end:
3000 + data->bytes_xfered += size;
3001 + N_MSG(FIO, " PIO Read<%d>bytes", size);
3002 +
3003 + sdr_clr_bits(MSDC_INTEN, wints);
3004 + if(data->error) ERR_MSG("read pio data->error<%d> left<%d> size<%d>", data->error, left, size);
3005 + return data->error;
3006 +}
3007 +
3008 +/* please make sure won't using PIO when size >= 512
3009 + which means, memory card block read/write won't using pio
3010 + then don't need to handle the CMD12 when data error.
3011 +*/
3012 +static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
3013 +{
3014 + u32 base = host->base;
3015 + struct scatterlist *sg = data->sg;
3016 + u32 num = data->sg_len;
3017 + u32 *ptr;
3018 + u8 *u8ptr;
3019 + u32 left;
3020 + u32 count, size = 0;
3021 + u32 wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3022 + unsigned long tmo = jiffies + DAT_TIMEOUT;
3023 +
3024 + sdr_set_bits(MSDC_INTEN, wints);
3025 + while (num) {
3026 + left = sg_dma_len(sg);
3027 + ptr = sg_virt(sg);
3028 +
3029 + while (left) {
3030 + if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3031 + count = MSDC_FIFO_SZ >> 2;
3032 + do {
3033 + msdc_fifo_write32(*ptr); ptr++;
3034 + } while (--count);
3035 + left -= MSDC_FIFO_SZ;
3036 + } else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
3037 + while (left > 3) {
3038 + msdc_fifo_write32(*ptr); ptr++;
3039 + left -= 4;
3040 + }
3041 +
3042 + u8ptr = (u8*)ptr;
3043 + while(left){
3044 + msdc_fifo_write8(*u8ptr); u8ptr++;
3045 + left--;
3046 + }
3047 + }
3048 +
3049 + if (msdc_pio_abort(host, data, tmo)) {
3050 + goto end;
3051 + }
3052 + }
3053 + size += sg_dma_len(sg);
3054 + sg = sg_next(sg); num--;
3055 + }
3056 +end:
3057 + data->bytes_xfered += size;
3058 + N_MSG(FIO, " PIO Write<%d>bytes", size);
3059 + if(data->error) ERR_MSG("write pio data->error<%d>", data->error);
3060 +
3061 + sdr_clr_bits(MSDC_INTEN, wints);
3062 + return data->error;
3063 +}
3064 +
3065 +#if 0 /* --- by chhung */
3066 +// DMA resume / start / stop
3067 +static void msdc_dma_resume(struct msdc_host *host)
3068 +{
3069 + u32 base = host->base;
3070 +
3071 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_RESUME, 1);
3072 +
3073 + N_MSG(DMA, "DMA resume");
3074 +}
3075 +#endif /* end of --- */
3076 +
3077 +static void msdc_dma_start(struct msdc_host *host)
3078 +{
3079 + u32 base = host->base;
3080 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3081 +
3082 + sdr_set_bits(MSDC_INTEN, wints);
3083 + //dsb(); /* --- by chhung */
3084 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
3085 +
3086 + N_MSG(DMA, "DMA start");
3087 +}
3088 +
3089 +static void msdc_dma_stop(struct msdc_host *host)
3090 +{
3091 + u32 base = host->base;
3092 + //u32 retries=500;
3093 + u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR ;
3094 +
3095 + N_MSG(DMA, "DMA status: 0x%.8x",sdr_read32(MSDC_DMA_CFG));
3096 + //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3097 +
3098 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
3099 + while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
3100 +
3101 + //dsb(); /* --- by chhung */
3102 + sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
3103 +
3104 + N_MSG(DMA, "DMA stop");
3105 +}
3106 +
3107 +#if 0 /* --- by chhung */
3108 +/* dump a gpd list */
3109 +static void msdc_dma_dump(struct msdc_host *host, struct msdc_dma *dma)
3110 +{
3111 + gpd_t *gpd = dma->gpd;
3112 + bd_t *bd = dma->bd;
3113 + bd_t *ptr;
3114 + int i = 0;
3115 + int p_to_v;
3116 +
3117 + if (dma->mode != MSDC_MODE_DMA_DESC) {
3118 + return;
3119 + }
3120 +
3121 + ERR_MSG("try to dump gpd and bd");
3122 +
3123 + /* dump gpd */
3124 + ERR_MSG(".gpd<0x%.8x> gpd_phy<0x%.8x>", (int)gpd, (int)dma->gpd_addr);
3125 + ERR_MSG("...hwo <%d>", gpd->hwo );
3126 + ERR_MSG("...bdp <%d>", gpd->bdp );
3127 + ERR_MSG("...chksum<0x%.8x>", gpd->chksum );
3128 + //ERR_MSG("...intr <0x%.8x>", gpd->intr );
3129 + ERR_MSG("...next <0x%.8x>", (int)gpd->next );
3130 + ERR_MSG("...ptr <0x%.8x>", (int)gpd->ptr );
3131 + ERR_MSG("...buflen<0x%.8x>", gpd->buflen );
3132 + //ERR_MSG("...extlen<0x%.8x>", gpd->extlen );
3133 + //ERR_MSG("...arg <0x%.8x>", gpd->arg );
3134 + //ERR_MSG("...blknum<0x%.8x>", gpd->blknum );
3135 + //ERR_MSG("...cmd <0x%.8x>", gpd->cmd );
3136 +
3137 + /* dump bd */
3138 + ERR_MSG(".bd<0x%.8x> bd_phy<0x%.8x> gpd_ptr<0x%.8x>", (int)bd, (int)dma->bd_addr, (int)gpd->ptr);
3139 + ptr = bd;
3140 + p_to_v = ((u32)bd - (u32)dma->bd_addr);
3141 + while (1) {
3142 + ERR_MSG(".bd[%d]", i); i++;
3143 + ERR_MSG("...eol <%d>", ptr->eol );
3144 + ERR_MSG("...chksum<0x%.8x>", ptr->chksum );
3145 + //ERR_MSG("...blkpad<0x%.8x>", ptr->blkpad );
3146 + //ERR_MSG("...dwpad <0x%.8x>", ptr->dwpad );
3147 + ERR_MSG("...next <0x%.8x>", (int)ptr->next );
3148 + ERR_MSG("...ptr <0x%.8x>", (int)ptr->ptr );
3149 + ERR_MSG("...buflen<0x%.8x>", (int)ptr->buflen );
3150 +
3151 + if (ptr->eol == 1) {
3152 + break;
3153 + }
3154 +
3155 + /* find the next bd, virtual address of ptr->next */
3156 + /* don't need to enable when use malloc */
3157 + //BUG_ON( (ptr->next + p_to_v)!=(ptr+1) );
3158 + //ERR_MSG(".next bd<0x%.8x><0x%.8x>", (ptr->next + p_to_v), (ptr+1));
3159 + ptr++;
3160 + }
3161 +
3162 + ERR_MSG("dump gpd and bd finished");
3163 +}
3164 +#endif /* end of --- */
3165 +
3166 +/* calc checksum */
3167 +static u8 msdc_dma_calcs(u8 *buf, u32 len)
3168 +{
3169 + u32 i, sum = 0;
3170 + for (i = 0; i < len; i++) {
3171 + sum += buf[i];
3172 + }
3173 + return 0xFF - (u8)sum;
3174 +}
3175 +
3176 +/* gpd bd setup + dma registers */
3177 +static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
3178 +{
3179 + u32 base = host->base;
3180 + u32 sglen = dma->sglen;
3181 + //u32 i, j, num, bdlen, arg, xfersz;
3182 + u32 j, num, bdlen;
3183 + u8 blkpad, dwpad, chksum;
3184 + struct scatterlist *sg = dma->sg;
3185 + gpd_t *gpd;
3186 + bd_t *bd;
3187 +
3188 + switch (dma->mode) {
3189 + case MSDC_MODE_DMA_BASIC:
3190 + BUG_ON(dma->xfersz > 65535);
3191 + BUG_ON(dma->sglen != 1);
3192 + sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
3193 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
3194 +//#if defined (CONFIG_RALINK_MT7620)
3195 + if (ralink_soc == MT762X_SOC_MT7620A)
3196 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
3197 +//#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3198 + else
3199 + sdr_write32((volatile u32*)(RALINK_MSDC_BASE+0xa8), sg_dma_len(sg));
3200 +//#endif
3201 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3202 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
3203 + break;
3204 + case MSDC_MODE_DMA_DESC:
3205 + blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
3206 + dwpad = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
3207 + chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
3208 +
3209 + /* calculate the required number of gpd */
3210 + num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
3211 + BUG_ON(num !=1 );
3212 +
3213 + gpd = dma->gpd;
3214 + bd = dma->bd;
3215 + bdlen = sglen;
3216 +
3217 + /* modify gpd*/
3218 + //gpd->intr = 0;
3219 + gpd->hwo = 1; /* hw will clear it */
3220 + gpd->bdp = 1;
3221 + gpd->chksum = 0; /* need to clear first. */
3222 + gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
3223 +
3224 + /* modify bd*/
3225 + for (j = 0; j < bdlen; j++) {
3226 + msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
3227 + if(j == bdlen - 1) {
3228 + bd[j].eol = 1; /* the last bd */
3229 + } else {
3230 + bd[j].eol = 0;
3231 + }
3232 + bd[j].chksum = 0; /* checksume need to clear first */
3233 + bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
3234 + sg++;
3235 + }
3236 +
3237 + dma->used_gpd += 2;
3238 + dma->used_bd += bdlen;
3239 +
3240 + sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
3241 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
3242 + sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
3243 +
3244 + sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
3245 + break;
3246 +
3247 + default:
3248 + break;
3249 + }
3250 +
3251 + N_MSG(DMA, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3252 + N_MSG(DMA, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3253 + N_MSG(DMA, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3254 +
3255 + return 0;
3256 +}
3257 +
3258 +static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
3259 + struct scatterlist *sg, unsigned int sglen)
3260 +{
3261 + BUG_ON(sglen > MAX_BD_NUM); /* not support currently */
3262 +
3263 + dma->sg = sg;
3264 + dma->flags = DMA_FLAG_EN_CHKSUM;
3265 + //dma->flags = DMA_FLAG_NONE; /* CHECKME */
3266 + dma->sglen = sglen;
3267 + dma->xfersz = host->xfer_size;
3268 + dma->burstsz = MSDC_BRUST_64B;
3269 +
3270 + if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
3271 + dma->mode = MSDC_MODE_DMA_BASIC;
3272 + else
3273 + dma->mode = MSDC_MODE_DMA_DESC;
3274 +
3275 + N_MSG(DMA, "DMA mode<%d> sglen<%d> xfersz<%d>", dma->mode, dma->sglen, dma->xfersz);
3276 +
3277 + msdc_dma_config(host, dma);
3278 +
3279 + /*if (dma->mode == MSDC_MODE_DMA_DESC) {
3280 + //msdc_dma_dump(host, dma);
3281 + } */
3282 +}
3283 +
3284 +/* set block number before send command */
3285 +static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
3286 +{
3287 + u32 base = host->base;
3288 +
3289 + sdr_write32(SDC_BLK_NUM, blknum);
3290 +}
3291 +
3292 +static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
3293 +{
3294 + struct msdc_host *host = mmc_priv(mmc);
3295 + struct mmc_command *cmd;
3296 + struct mmc_data *data;
3297 + u32 base = host->base;
3298 + //u32 intsts = 0;
3299 + unsigned int left=0;
3300 + int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
3301 +
3302 + #define SND_DAT 0
3303 + #define SND_CMD 1
3304 +
3305 + BUG_ON(mmc == NULL);
3306 + BUG_ON(mrq == NULL);
3307 +
3308 + host->error = 0;
3309 + atomic_set(&host->abort, 0);
3310 +
3311 + cmd = mrq->cmd;
3312 + data = mrq->cmd->data;
3313 +
3314 +#if 0 /* --- by chhung */
3315 + //if(host->id ==1){
3316 + N_MSG(OPS, "enable clock!");
3317 + msdc_ungate_clock(host->id);
3318 + //}
3319 +#endif /* end of --- */
3320 +
3321 + if (!data) {
3322 + send_type=SND_CMD;
3323 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3324 + goto done;
3325 + }
3326 + } else {
3327 + BUG_ON(data->blksz > HOST_MAX_BLKSZ);
3328 + send_type=SND_DAT;
3329 +
3330 + data->error = 0;
3331 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3332 + host->data = data;
3333 + host->xfer_size = data->blocks * data->blksz;
3334 + host->blksz = data->blksz;
3335 +
3336 + /* deside the transfer mode */
3337 + if (drv_mode[host->id] == MODE_PIO) {
3338 + host->dma_xfer = dma = 0;
3339 + } else if (drv_mode[host->id] == MODE_DMA) {
3340 + host->dma_xfer = dma = 1;
3341 + } else if (drv_mode[host->id] == MODE_SIZE_DEP) {
3342 + host->dma_xfer = dma = ((host->xfer_size >= dma_size[host->id]) ? 1 : 0);
3343 + }
3344 +
3345 + if (read) {
3346 + if ((host->timeout_ns != data->timeout_ns) ||
3347 + (host->timeout_clks != data->timeout_clks)) {
3348 + msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
3349 + }
3350 + }
3351 +
3352 + msdc_set_blknum(host, data->blocks);
3353 + //msdc_clr_fifo(); /* no need */
3354 +
3355 + if (dma) {
3356 + msdc_dma_on(); /* enable DMA mode first!! */
3357 + init_completion(&host->xfer_done);
3358 +
3359 + /* start the command first*/
3360 + if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
3361 + goto done;
3362 +
3363 + dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
3364 + (void)dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3365 + msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
3366 +
3367 + /* then wait command done */
3368 + if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
3369 + goto done;
3370 +
3371 + /* for read, the data coming too fast, then CRC error
3372 + start DMA no business with CRC. */
3373 + //init_completion(&host->xfer_done);
3374 + msdc_dma_start(host);
3375 +
3376 + spin_unlock(&host->lock);
3377 + if(!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)){
3378 + ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd->opcode, data->blocks * data->blksz);
3379 + ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA));
3380 + ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA));
3381 + ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL));
3382 + ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG));
3383 + data->error = (unsigned int)-ETIMEDOUT;
3384 +
3385 + msdc_reset();
3386 + msdc_clr_fifo();
3387 + msdc_clr_int();
3388 + }
3389 + spin_lock(&host->lock);
3390 + msdc_dma_stop(host);
3391 + } else {
3392 + /* Firstly: send command */
3393 + if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0) {
3394 + goto done;
3395 + }
3396 +
3397 + /* Secondly: pio data phase */
3398 + if (read) {
3399 + if (msdc_pio_read(host, data)){
3400 + goto done;
3401 + }
3402 + } else {
3403 + if (msdc_pio_write(host, data)) {
3404 + goto done;
3405 + }
3406 + }
3407 +
3408 + /* For write case: make sure contents in fifo flushed to device */
3409 + if (!read) {
3410 + while (1) {
3411 + left=msdc_txfifocnt();
3412 + if (left == 0) {
3413 + break;
3414 + }
3415 + if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
3416 + break;
3417 + /* Fix me: what about if data error, when stop ? how to? */
3418 + }
3419 + }
3420 + } else {
3421 + /* Fix me: read case: need to check CRC error */
3422 + }
3423 +
3424 + /* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy.
3425 + For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
3426 + */
3427 +
3428 + /* try not to wait xfer_comp interrupt.
3429 + the next command will check SDC_BUSY.
3430 + SDC_BUSY means xfer_comp assert
3431 + */
3432 +
3433 + } // PIO mode
3434 +
3435 + /* Last: stop transfer */
3436 + if (data->stop){
3437 + if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
3438 + goto done;
3439 + }
3440 + }
3441 + }
3442 +
3443 +done:
3444 + if (data != NULL) {
3445 + host->data = NULL;
3446 + host->dma_xfer = 0;
3447 + if (dma != 0) {
3448 + msdc_dma_off();
3449 + host->dma.used_bd = 0;
3450 + host->dma.used_gpd = 0;
3451 + dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
3452 + }
3453 + host->blksz = 0;
3454 +
3455 +#if 0 // don't stop twice!
3456 + if(host->hw->flags & MSDC_REMOVABLE && data->error) {
3457 + msdc_abort_data(host);
3458 + /* reset in IRQ, stop command has issued. -> No need */
3459 + }
3460 +#endif
3461 +
3462 + N_MSG(OPS, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio"),
3463 + (read ? "read ":"write") ,data->blksz, data->blocks, data->error);
3464 + }
3465 +
3466 +#if 0 /* --- by chhung */
3467 +#if 1
3468 + //if(host->id==1) {
3469 + if(send_type==SND_CMD) {
3470 + if(cmd->opcode == MMC_SEND_STATUS) {
3471 + if((cmd->resp[0] & CARD_READY_FOR_DATA) ||(CARD_CURRENT_STATE(cmd->resp[0]) != 7)){
3472 + N_MSG(OPS,"disable clock, CMD13 IDLE");
3473 + msdc_gate_clock(host->id);
3474 + }
3475 + } else {
3476 + N_MSG(OPS,"disable clock, CMD<%d>", cmd->opcode);
3477 + msdc_gate_clock(host->id);
3478 + }
3479 + } else {
3480 + if(read) {
3481 + N_MSG(OPS,"disable clock!!! Read CMD<%d>",cmd->opcode);
3482 + msdc_gate_clock(host->id);
3483 + }
3484 + }
3485 + //}
3486 +#else
3487 + msdc_gate_clock(host->id);
3488 +#endif
3489 +#endif /* end of --- */
3490 +
3491 + if (mrq->cmd->error) host->error = 0x001;
3492 + if (mrq->data && mrq->data->error) host->error |= 0x010;
3493 + if (mrq->stop && mrq->stop->error) host->error |= 0x100;
3494 +
3495 + //if (host->error) ERR_MSG("host->error<%d>", host->error);
3496 +
3497 + return host->error;
3498 +}
3499 +
3500 +static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
3501 +{
3502 + struct mmc_command cmd;
3503 + struct mmc_request mrq;
3504 + u32 err;
3505 +
3506 + memset(&cmd, 0, sizeof(struct mmc_command));
3507 + cmd.opcode = MMC_APP_CMD;
3508 +#if 0 /* bug: we meet mmc->card is null when ACMD6 */
3509 + cmd.arg = mmc->card->rca << 16;
3510 +#else
3511 + cmd.arg = host->app_cmd_arg;
3512 +#endif
3513 + cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
3514 +
3515 + memset(&mrq, 0, sizeof(struct mmc_request));
3516 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3517 + cmd.data = NULL;
3518 +
3519 + err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);
3520 + return err;
3521 +}
3522 +
3523 +static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
3524 +{
3525 + int result = -1;
3526 + u32 base = host->base;
3527 + u32 rsmpl, cur_rsmpl, orig_rsmpl;
3528 + u32 rrdly, cur_rrdly = 0xffffffff, orig_rrdly;
3529 + u32 skip = 1;
3530 +
3531 + /* ==== don't support 3.0 now ====
3532 + 1: R_SMPL[1]
3533 + 2: PAD_CMD_RESP_RXDLY[26:22]
3534 + ==========================*/
3535 +
3536 + // save the previous tune result
3537 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_RSPL, orig_rsmpl);
3538 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
3539 +
3540 + rrdly = 0;
3541 + do {
3542 + for (rsmpl = 0; rsmpl < 2; rsmpl++) {
3543 + /* Lv1: R_SMPL[1] */
3544 + cur_rsmpl = (orig_rsmpl + rsmpl) % 2;
3545 + if (skip == 1) {
3546 + skip = 0;
3547 + continue;
3548 + }
3549 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl);
3550 +
3551 + if (host->app_cmd) {
3552 + result = msdc_app_cmd(host->mmc, host);
3553 + if (result) {
3554 + ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
3555 + host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
3556 + continue;
3557 + }
3558 + }
3559 + result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.
3560 + ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd->opcode,
3561 + (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
3562 +
3563 + if (result == 0) {
3564 + return 0;
3565 + }
3566 + if (result != (unsigned int)(-EIO)) {
3567 + ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd->opcode, result);
3568 + return result;
3569 + }
3570 +
3571 + /* should be EIO */
3572 + if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */
3573 + msdc_abort_data(host);
3574 + }
3575 + }
3576 +
3577 + /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
3578 + cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
3579 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);
3580 + }while (++rrdly < 32);
3581 +
3582 + return result;
3583 +}
3584 +
3585 +/* Support SD2.0 Only */
3586 +static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
3587 +{
3588 + struct msdc_host *host = mmc_priv(mmc);
3589 + u32 base = host->base;
3590 + u32 ddr=0;
3591 + u32 dcrc=0;
3592 + u32 rxdly, cur_rxdly0, cur_rxdly1;
3593 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3594 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3595 + u32 cur_dat4, cur_dat5, cur_dat6, cur_dat7;
3596 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3597 + u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
3598 + int result = -1;
3599 + u32 skip = 1;
3600 +
3601 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
3602 +
3603 + /* Tune Method 2. */
3604 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3605 +
3606 + rxdly = 0;
3607 + do {
3608 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3609 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3610 + if (skip == 1) {
3611 + skip = 0;
3612 + continue;
3613 + }
3614 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3615 +
3616 + if (host->app_cmd) {
3617 + result = msdc_app_cmd(host->mmc, host);
3618 + if (result) {
3619 + ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host->mrq->cmd->opcode);
3620 + continue;
3621 + }
3622 + }
3623 + result = msdc_do_request(mmc,mrq);
3624 +
3625 + sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
3626 + if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
3627 + ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
3628 + (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
3629 + sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
3630 +
3631 + /* Fix me: result is 0, but dcrc is still exist */
3632 + if (result == 0 && dcrc == 0) {
3633 + goto done;
3634 + } else {
3635 + /* there is a case: command timeout, and data phase not processed */
3636 + if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
3637 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3638 + result, mrq->cmd->error, mrq->data->error);
3639 + goto done;
3640 + }
3641 + }
3642 + }
3643 +
3644 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3645 + cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
3646 +
3647 + /* E1 ECO. YD: Reverse */
3648 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3649 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3650 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3651 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3652 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3653 + orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
3654 + orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
3655 + orig_dat6 = (cur_rxdly1 >> 8) & 0x1F;
3656 + orig_dat7 = (cur_rxdly1 >> 0) & 0x1F;
3657 + } else {
3658 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3659 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3660 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3661 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3662 + orig_dat4 = (cur_rxdly1 >> 0) & 0x1F;
3663 + orig_dat5 = (cur_rxdly1 >> 8) & 0x1F;
3664 + orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
3665 + orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
3666 + }
3667 +
3668 + if (ddr) {
3669 + cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3670 + cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3671 + cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3672 + cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3673 + } else {
3674 + cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
3675 + cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
3676 + cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
3677 + cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
3678 + }
3679 + cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
3680 + cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
3681 + cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
3682 + cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
3683 +
3684 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3685 + cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
3686 +
3687 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3688 + sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
3689 +
3690 + } while (++rxdly < 32);
3691 +
3692 +done:
3693 + return result;
3694 +}
3695 +
3696 +static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
3697 +{
3698 + struct msdc_host *host = mmc_priv(mmc);
3699 + u32 base = host->base;
3700 +
3701 + u32 wrrdly, cur_wrrdly = 0xffffffff, orig_wrrdly;
3702 + u32 dsmpl, cur_dsmpl, orig_dsmpl;
3703 + u32 rxdly, cur_rxdly0;
3704 + u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
3705 + u32 cur_dat0, cur_dat1, cur_dat2, cur_dat3;
3706 + int result = -1;
3707 + u32 skip = 1;
3708 +
3709 + // MSDC_IOCON_DDR50CKD need to check. [Fix me]
3710 +
3711 + sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
3712 + sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl );
3713 +
3714 + /* Tune Method 2. just DAT0 */
3715 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
3716 + cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
3717 +
3718 + /* E1 ECO. YD: Reverse */
3719 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
3720 + orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
3721 + orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
3722 + orig_dat2 = (cur_rxdly0 >> 8) & 0x1F;
3723 + orig_dat3 = (cur_rxdly0 >> 0) & 0x1F;
3724 + } else {
3725 + orig_dat0 = (cur_rxdly0 >> 0) & 0x1F;
3726 + orig_dat1 = (cur_rxdly0 >> 8) & 0x1F;
3727 + orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
3728 + orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
3729 + }
3730 +
3731 + rxdly = 0;
3732 + do {
3733 + wrrdly = 0;
3734 + do {
3735 + for (dsmpl = 0; dsmpl < 2; dsmpl++) {
3736 + cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
3737 + if (skip == 1) {
3738 + skip = 0;
3739 + continue;
3740 + }
3741 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
3742 +
3743 + if (host->app_cmd) {
3744 + result = msdc_app_cmd(host->mmc, host);
3745 + if (result) {
3746 + ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host->mrq->cmd->opcode);
3747 + continue;
3748 + }
3749 + }
3750 + result = msdc_do_request(mmc,mrq);
3751 +
3752 + ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
3753 + result == 0 ? "PASS" : "FAIL",
3754 + cur_dsmpl, cur_wrrdly, cur_rxdly0);
3755 +
3756 + if (result == 0) {
3757 + goto done;
3758 + }
3759 + else {
3760 + /* there is a case: command timeout, and data phase not processed */
3761 + if (mrq->data->error != (unsigned int)(-EIO)) {
3762 + ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
3763 + result, mrq->cmd->error, mrq->data->error);
3764 + goto done;
3765 + }
3766 + }
3767 + }
3768 + cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
3769 + sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);
3770 + } while (++wrrdly < 32);
3771 +
3772 + cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
3773 + cur_dat1 = orig_dat1;
3774 + cur_dat2 = orig_dat2;
3775 + cur_dat3 = orig_dat3;
3776 +
3777 + cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
3778 + sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
3779 + } while (++rxdly < 32);
3780 +
3781 +done:
3782 + return result;
3783 +}
3784 +
3785 +static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
3786 +{
3787 + struct mmc_command cmd;
3788 + struct mmc_request mrq;
3789 + u32 err;
3790 +
3791 + memset(&cmd, 0, sizeof(struct mmc_command));
3792 + cmd.opcode = MMC_SEND_STATUS;
3793 + if (mmc->card) {
3794 + cmd.arg = mmc->card->rca << 16;
3795 + } else {
3796 + ERR_MSG("cmd13 mmc card is null");
3797 + cmd.arg = host->app_cmd_arg;
3798 + }
3799 + cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
3800 +
3801 + memset(&mrq, 0, sizeof(struct mmc_request));
3802 + mrq.cmd = &cmd; cmd.mrq = &mrq;
3803 + cmd.data = NULL;
3804 +
3805 + err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
3806 +
3807 + if (status) {
3808 + *status = cmd.resp[0];
3809 + }
3810 +
3811 + return err;
3812 +}
3813 +
3814 +static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
3815 +{
3816 + u32 err = 0;
3817 + u32 status = 0;
3818 +
3819 + do {
3820 + err = msdc_get_card_status(mmc, host, &status);
3821 + if (err) return err;
3822 + /* need cmd12? */
3823 + ERR_MSG("cmd<13> resp<0x%x>", status);
3824 + } while (R1_CURRENT_STATE(status) == 7);
3825 +
3826 + return err;
3827 +}
3828 +
3829 +/* failed when msdc_do_request */
3830 +static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
3831 +{
3832 + struct msdc_host *host = mmc_priv(mmc);
3833 + struct mmc_command *cmd;
3834 + struct mmc_data *data;
3835 + //u32 base = host->base;
3836 + int ret=0, read;
3837 +
3838 + cmd = mrq->cmd;
3839 + data = mrq->cmd->data;
3840 +
3841 + read = data->flags & MMC_DATA_READ ? 1 : 0;
3842 +
3843 + if (read) {
3844 + if (data->error == (unsigned int)(-EIO)) {
3845 + ret = msdc_tune_bread(mmc,mrq);
3846 + }
3847 + } else {
3848 + ret = msdc_check_busy(mmc, host);
3849 + if (ret){
3850 + ERR_MSG("XXX cmd13 wait program done failed");
3851 + return ret;
3852 + }
3853 + /* CRC and TO */
3854 + /* Fix me: don't care card status? */
3855 + ret = msdc_tune_bwrite(mmc,mrq);
3856 + }
3857 +
3858 + return ret;
3859 +}
3860 +
3861 +/* ops.request */
3862 +static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
3863 +{
3864 + struct msdc_host *host = mmc_priv(mmc);
3865 +
3866 + //=== for sdio profile ===
3867 +#if 0 /* --- by chhung */
3868 + u32 old_H32, old_L32, new_H32, new_L32;
3869 + u32 ticks = 0, opcode = 0, sizes = 0, bRx = 0;
3870 +#endif /* end of --- */
3871 +
3872 + if(host->mrq){
3873 + ERR_MSG("XXX host->mrq<0x%.8x>", (int)host->mrq);
3874 + BUG();
3875 + }
3876 +
3877 + if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
3878 + ERR_MSG("cmd<%d> card<%d> power<%d>", mrq->cmd->opcode, is_card_present(host), host->power_mode);
3879 + mrq->cmd->error = (unsigned int)-ENOMEDIUM;
3880 +
3881 +#if 1
3882 + mrq->done(mrq); // call done directly.
3883 +#else
3884 + mrq->cmd->retries = 0; // please don't retry.
3885 + mmc_request_done(mmc, mrq);
3886 +#endif
3887 +
3888 + return;
3889 + }
3890 +
3891 + /* start to process */
3892 + spin_lock(&host->lock);
3893 +#if 0 /* --- by chhung */
3894 + if (sdio_pro_enable) { //=== for sdio profile ===
3895 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3896 + GPT_GetCounter64(&old_L32, &old_H32);
3897 + }
3898 + }
3899 +#endif /* end of --- */
3900 +
3901 + host->mrq = mrq;
3902 +
3903 + if (msdc_do_request(mmc,mrq)) {
3904 + if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error) {
3905 + //msdc_tune_request(mmc,mrq);
3906 + }
3907 + }
3908 +
3909 + /* ==== when request done, check if app_cmd ==== */
3910 + if (mrq->cmd->opcode == MMC_APP_CMD) {
3911 + host->app_cmd = 1;
3912 + host->app_cmd_arg = mrq->cmd->arg; /* save the RCA */
3913 + } else {
3914 + host->app_cmd = 0;
3915 + //host->app_cmd_arg = 0;
3916 + }
3917 +
3918 + host->mrq = NULL;
3919 +
3920 +#if 0 /* --- by chhung */
3921 + //=== for sdio profile ===
3922 + if (sdio_pro_enable) {
3923 + if (mrq->cmd->opcode == 52 || mrq->cmd->opcode == 53) {
3924 + GPT_GetCounter64(&new_L32, &new_H32);
3925 + ticks = msdc_time_calc(old_L32, old_H32, new_L32, new_H32);
3926 +
3927 + opcode = mrq->cmd->opcode;
3928 + if (mrq->cmd->data) {
3929 + sizes = mrq->cmd->data->blocks * mrq->cmd->data->blksz;
3930 + bRx = mrq->cmd->data->flags & MMC_DATA_READ ? 1 : 0 ;
3931 + } else {
3932 + bRx = mrq->cmd->arg & 0x80000000 ? 1 : 0;
3933 + }
3934 +
3935 + if (!mrq->cmd->error) {
3936 + msdc_performance(opcode, sizes, bRx, ticks);
3937 + }
3938 + }
3939 + }
3940 +#endif /* end of --- */
3941 + spin_unlock(&host->lock);
3942 +
3943 + mmc_request_done(mmc, mrq);
3944 +
3945 + return;
3946 +}
3947 +
3948 +/* called by ops.set_ios */
3949 +static void msdc_set_buswidth(struct msdc_host *host, u32 width)
3950 +{
3951 + u32 base = host->base;
3952 + u32 val = sdr_read32(SDC_CFG);
3953 +
3954 + val &= ~SDC_CFG_BUSWIDTH;
3955 +
3956 + switch (width) {
3957 + default:
3958 + case MMC_BUS_WIDTH_1:
3959 + width = 1;
3960 + val |= (MSDC_BUS_1BITS << 16);
3961 + break;
3962 + case MMC_BUS_WIDTH_4:
3963 + val |= (MSDC_BUS_4BITS << 16);
3964 + break;
3965 + case MMC_BUS_WIDTH_8:
3966 + val |= (MSDC_BUS_8BITS << 16);
3967 + break;
3968 + }
3969 +
3970 + sdr_write32(SDC_CFG, val);
3971 +
3972 + N_MSG(CFG, "Bus Width = %d", width);
3973 +}
3974 +
3975 +/* ops.set_ios */
3976 +static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
3977 +{
3978 + struct msdc_host *host = mmc_priv(mmc);
3979 + struct msdc_hw *hw=host->hw;
3980 + u32 base = host->base;
3981 + u32 ddr = 0;
3982 +
3983 +#ifdef MT6575_SD_DEBUG
3984 + static char *vdd[] = {
3985 + "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
3986 + "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
3987 + "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
3988 + "3.40v", "3.50v", "3.60v"
3989 + };
3990 + static char *power_mode[] = {
3991 + "OFF", "UP", "ON"
3992 + };
3993 + static char *bus_mode[] = {
3994 + "UNKNOWN", "OPENDRAIN", "PUSHPULL"
3995 + };
3996 + static char *timing[] = {
3997 + "LEGACY", "MMC_HS", "SD_HS"
3998 + };
3999 +
4000 + printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
4001 + ios->clock / 1000, bus_mode[ios->bus_mode],
4002 + (ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
4003 + power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);
4004 +#endif
4005 +
4006 + msdc_set_buswidth(host, ios->bus_width);
4007 +
4008 + /* Power control ??? */
4009 + switch (ios->power_mode) {
4010 + case MMC_POWER_OFF:
4011 + case MMC_POWER_UP:
4012 + // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
4013 + break;
4014 + case MMC_POWER_ON:
4015 + host->power_mode = MMC_POWER_ON;
4016 + break;
4017 + default:
4018 + break;
4019 + }
4020 +
4021 + /* Clock control */
4022 + if (host->mclk != ios->clock) {
4023 + if(ios->clock > 25000000) {
4024 + //if (!(host->hw->flags & MSDC_REMOVABLE)) {
4025 + INIT_MSG("SD data latch edge<%d>", hw->data_edge);
4026 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
4027 + sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
4028 + //} /* for tuning debug */
4029 + } else { /* default value */
4030 + sdr_write32(MSDC_IOCON, 0x00000000);
4031 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4032 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4033 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4034 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4035 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4036 + }
4037 + msdc_set_mclk(host, ddr, ios->clock);
4038 + }
4039 +}
4040 +
4041 +/* ops.get_ro */
4042 +static int msdc_ops_get_ro(struct mmc_host *mmc)
4043 +{
4044 + struct msdc_host *host = mmc_priv(mmc);
4045 + u32 base = host->base;
4046 + unsigned long flags;
4047 + int ro = 0;
4048 +
4049 + if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
4050 + spin_lock_irqsave(&host->lock, flags);
4051 + ro = (sdr_read32(MSDC_PS) >> 31);
4052 + spin_unlock_irqrestore(&host->lock, flags);
4053 + }
4054 + return ro;
4055 +}
4056 +
4057 +/* ops.get_cd */
4058 +static int msdc_ops_get_cd(struct mmc_host *mmc)
4059 +{
4060 + struct msdc_host *host = mmc_priv(mmc);
4061 + u32 base = host->base;
4062 + unsigned long flags;
4063 + int present = 1;
4064 +
4065 + /* for sdio, MSDC_REMOVABLE not set, always return 1 */
4066 + if (!(host->hw->flags & MSDC_REMOVABLE)) {
4067 + /* For sdio, read H/W always get<1>, but may timeout some times */
4068 +#if 1
4069 + host->card_inserted = 1;
4070 + return 1;
4071 +#else
4072 + host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0;
4073 + INIT_MSG("sdio ops_get_cd<%d>", host->card_inserted);
4074 + return host->card_inserted;
4075 +#endif
4076 + }
4077 +
4078 + /* MSDC_CD_PIN_EN set for card */
4079 + if (host->hw->flags & MSDC_CD_PIN_EN) {
4080 + spin_lock_irqsave(&host->lock, flags);
4081 +#if 0
4082 + present = host->card_inserted; /* why not read from H/W: Fix me*/
4083 +#else
4084 + present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1;
4085 + host->card_inserted = present;
4086 +#endif
4087 + spin_unlock_irqrestore(&host->lock, flags);
4088 + } else {
4089 + present = 0; /* TODO? Check DAT3 pins for card detection */
4090 + }
4091 +
4092 + INIT_MSG("ops_get_cd return<%d>", present);
4093 + return present;
4094 +}
4095 +
4096 +/* ops.enable_sdio_irq */
4097 +static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
4098 +{
4099 + struct msdc_host *host = mmc_priv(mmc);
4100 + struct msdc_hw *hw = host->hw;
4101 + u32 base = host->base;
4102 + u32 tmp;
4103 +
4104 + if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
4105 + if (enable) {
4106 + hw->enable_sdio_eirq(); /* combo_sdio_enable_eirq */
4107 + } else {
4108 + hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
4109 + }
4110 + } else {
4111 + ERR_MSG("XXX "); /* so never enter here */
4112 + tmp = sdr_read32(SDC_CFG);
4113 + /* FIXME. Need to interrupt gap detection */
4114 + if (enable) {
4115 + tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4116 + } else {
4117 + tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
4118 + }
4119 + sdr_write32(SDC_CFG, tmp);
4120 + }
4121 +}
4122 +
4123 +static struct mmc_host_ops mt_msdc_ops = {
4124 + .request = msdc_ops_request,
4125 + .set_ios = msdc_ops_set_ios,
4126 + .get_ro = msdc_ops_get_ro,
4127 + .get_cd = msdc_ops_get_cd,
4128 + .enable_sdio_irq = msdc_ops_enable_sdio_irq,
4129 +};
4130 +
4131 +/*--------------------------------------------------------------------------*/
4132 +/* interrupt handler */
4133 +/*--------------------------------------------------------------------------*/
4134 +static irqreturn_t msdc_irq(int irq, void *dev_id)
4135 +{
4136 + struct msdc_host *host = (struct msdc_host *)dev_id;
4137 + struct mmc_data *data = host->data;
4138 + struct mmc_command *cmd = host->cmd;
4139 + u32 base = host->base;
4140 +
4141 + u32 cmdsts = MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO | MSDC_INT_CMDRDY |
4142 + MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
4143 + MSDC_INT_ACMD19_DONE;
4144 + u32 datsts = MSDC_INT_DATCRCERR |MSDC_INT_DATTMO;
4145 +
4146 + u32 intsts = sdr_read32(MSDC_INT);
4147 + u32 inten = sdr_read32(MSDC_INTEN); inten &= intsts;
4148 +
4149 + sdr_write32(MSDC_INT, intsts); /* clear interrupts */
4150 + /* MSG will cause fatal error */
4151 +
4152 + /* card change interrupt */
4153 + if (intsts & MSDC_INT_CDSC){
4154 + if (mtk_sw_poll)
4155 + return IRQ_HANDLED;
4156 + IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts);
4157 +#if 0 /* ---/+++ by chhung: fix slot mechanical bounce issue */
4158 + tasklet_hi_schedule(&host->card_tasklet);
4159 +#else
4160 + schedule_delayed_work(&host->card_delaywork, HZ);
4161 +#endif
4162 + /* tuning when plug card ? */
4163 + }
4164 +
4165 + /* sdio interrupt */
4166 + if (intsts & MSDC_INT_SDIOIRQ){
4167 + IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
4168 + //mmc_signal_sdio_irq(host->mmc);
4169 + }
4170 +
4171 + /* transfer complete interrupt */
4172 + if (data != NULL) {
4173 + if (inten & MSDC_INT_XFER_COMPL) {
4174 + data->bytes_xfered = host->dma.xfersz;
4175 + complete(&host->xfer_done);
4176 + }
4177 +
4178 + if (intsts & datsts) {
4179 + /* do basic reset, or stop command will sdc_busy */
4180 + msdc_reset();
4181 + msdc_clr_fifo();
4182 + msdc_clr_int();
4183 + atomic_set(&host->abort, 1); /* For PIO mode exit */
4184 +
4185 + if (intsts & MSDC_INT_DATTMO){
4186 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host->mrq->cmd->opcode);
4187 + data->error = (unsigned int)-ETIMEDOUT;
4188 + }
4189 + else if (intsts & MSDC_INT_DATCRCERR){
4190 + IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
4191 + data->error = (unsigned int)-EIO;
4192 + }
4193 +
4194 + //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
4195 + if (host->dma_xfer) {
4196 + complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
4197 + } /* PIO mode can't do complete, because not init */
4198 + }
4199 + }
4200 +
4201 + /* command interrupts */
4202 + if ((cmd != NULL) && (intsts & cmdsts)) {
4203 + if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) ||
4204 + (intsts & MSDC_INT_ACMD19_DONE)) {
4205 + u32 *rsp = &cmd->resp[0];
4206 +
4207 + switch (host->cmd_rsp) {
4208 + case RESP_NONE:
4209 + break;
4210 + case RESP_R2:
4211 + *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
4212 + *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
4213 + break;
4214 + default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
4215 + if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
4216 + *rsp = sdr_read32(SDC_ACMD_RESP);
4217 + } else {
4218 + *rsp = sdr_read32(SDC_RESP0);
4219 + }
4220 + break;
4221 + }
4222 + } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
4223 + if(intsts & MSDC_INT_ACMDCRCERR){
4224 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR",cmd->opcode);
4225 + }
4226 + else {
4227 + IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR",cmd->opcode);
4228 + }
4229 + cmd->error = (unsigned int)-EIO;
4230 + } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
4231 + if(intsts & MSDC_INT_ACMDTMO){
4232 + IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO",cmd->opcode);
4233 + }
4234 + else {
4235 + IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO",cmd->opcode);
4236 + }
4237 + cmd->error = (unsigned int)-ETIMEDOUT;
4238 + msdc_reset();
4239 + msdc_clr_fifo();
4240 + msdc_clr_int();
4241 + }
4242 + complete(&host->cmd_done);
4243 + }
4244 +
4245 + /* mmc irq interrupts */
4246 + if (intsts & MSDC_INT_MMCIRQ) {
4247 + printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));
4248 + }
4249 +
4250 +#ifdef MT6575_SD_DEBUG
4251 + {
4252 + msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
4253 + N_MSG(INT, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
4254 + intsts,
4255 + int_reg->mmcirq,
4256 + int_reg->cdsc,
4257 + int_reg->atocmdrdy,
4258 + int_reg->atocmdtmo,
4259 + int_reg->atocmdcrc,
4260 + int_reg->atocmd19done);
4261 + N_MSG(INT, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
4262 + intsts,
4263 + int_reg->sdioirq,
4264 + int_reg->cmdrdy,
4265 + int_reg->cmdtmo,
4266 + int_reg->rspcrc,
4267 + int_reg->csta);
4268 + N_MSG(INT, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
4269 + intsts,
4270 + int_reg->xfercomp,
4271 + int_reg->dxferdone,
4272 + int_reg->dattmo,
4273 + int_reg->datcrc,
4274 + int_reg->dmaqempty);
4275 +
4276 + }
4277 +#endif
4278 +
4279 + return IRQ_HANDLED;
4280 +}
4281 +
4282 +/*--------------------------------------------------------------------------*/
4283 +/* platform_driver members */
4284 +/*--------------------------------------------------------------------------*/
4285 +/* called by msdc_drv_probe/remove */
4286 +static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
4287 +{
4288 + struct msdc_hw *hw = host->hw;
4289 + u32 base = host->base;
4290 +
4291 + /* for sdio, not set */
4292 + if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
4293 + /* Pull down card detection pin since it is not avaiable */
4294 + /*
4295 + if (hw->config_gpio_pin)
4296 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4297 + */
4298 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4299 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4300 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4301 + return;
4302 + }
4303 +
4304 + N_MSG(CFG, "CD IRQ Eanable(%d)", enable);
4305 +
4306 + if (enable) {
4307 + if (hw->enable_cd_eirq) { /* not set, never enter */
4308 + hw->enable_cd_eirq();
4309 + } else {
4310 + /* card detection circuit relies on the core power so that the core power
4311 + * shouldn't be turned off. Here adds a reference count to keep
4312 + * the core power alive.
4313 + */
4314 + //msdc_vcore_on(host); //did in msdc_init_hw()
4315 +
4316 + if (hw->config_gpio_pin) /* NULL */
4317 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
4318 +
4319 + sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
4320 + sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
4321 + sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4322 + sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP); /* not in document! Fix me */
4323 + }
4324 + } else {
4325 + if (hw->disable_cd_eirq) {
4326 + hw->disable_cd_eirq();
4327 + } else {
4328 + if (hw->config_gpio_pin) /* NULL */
4329 + hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
4330 +
4331 + sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
4332 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4333 + sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
4334 +
4335 + /* Here decreases a reference count to core power since card
4336 + * detection circuit is shutdown.
4337 + */
4338 + //msdc_vcore_off(host);
4339 + }
4340 + }
4341 +}
4342 +
4343 +/* called by msdc_drv_probe */
4344 +static void msdc_init_hw(struct msdc_host *host)
4345 +{
4346 + u32 base = host->base;
4347 + struct msdc_hw *hw = host->hw;
4348 +
4349 +#ifdef MT6575_SD_DEBUG
4350 + msdc_reg[host->id] = (struct msdc_regs *)host->base;
4351 +#endif
4352 +
4353 + /* Power on */
4354 +#if 0 /* --- by chhung */
4355 + msdc_vcore_on(host);
4356 + msdc_pin_reset(host, MSDC_PIN_PULL_UP);
4357 + msdc_select_clksrc(host, hw->clk_src);
4358 + enable_clock(PERI_MSDC0_PDN + host->id, "SD");
4359 + msdc_vdd_on(host);
4360 +#endif /* end of --- */
4361 + /* Configure to MMC/SD mode */
4362 + sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC);
4363 +
4364 + /* Reset */
4365 + msdc_reset();
4366 + msdc_clr_fifo();
4367 +
4368 + /* Disable card detection */
4369 + sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
4370 +
4371 + /* Disable and clear all interrupts */
4372 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4373 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4374 +
4375 +#if 1
4376 + /* reset tuning parameter */
4377 + sdr_write32(MSDC_PAD_CTL0, 0x00090000);
4378 + sdr_write32(MSDC_PAD_CTL1, 0x000A0000);
4379 + sdr_write32(MSDC_PAD_CTL2, 0x000A0000);
4380 + // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
4381 + sdr_write32(MSDC_PAD_TUNE, 0x84101010); // for MT7620 E2 and afterward
4382 + // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
4383 + sdr_write32(MSDC_DAT_RDDLY0, 0x10101010); // for MT7620 E2 and afterward
4384 + sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
4385 + sdr_write32(MSDC_IOCON, 0x00000000);
4386 +#if 0 // use MT7620 default value: 0x403c004f
4387 + sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
4388 +#endif
4389 +
4390 + if (sdr_read32(MSDC_ECO_VER) >= 4) {
4391 + if (host->id == 1) {
4392 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1);
4393 + sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP, 1);
4394 +
4395 + /* internal clock: latch read data */
4396 + sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);
4397 + }
4398 + }
4399 +#endif
4400 +
4401 + /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
4402 + pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
4403 + set when kernel driver wants to use SDIO bus interrupt */
4404 + /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
4405 + sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
4406 +
4407 + /* disable detect SDIO device interupt function */
4408 + sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
4409 +
4410 + /* eneable SMT for glitch filter */
4411 + sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
4412 + sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
4413 + sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
4414 +
4415 +#if 1
4416 + /* set clk, cmd, dat pad driving */
4417 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
4418 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
4419 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
4420 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
4421 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
4422 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
4423 +#else
4424 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
4425 + sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
4426 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
4427 + sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
4428 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
4429 + sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
4430 +#endif
4431 +
4432 + /* set sampling edge */
4433 +
4434 + /* write crc timeout detection */
4435 + sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
4436 +
4437 + /* Configure to default data timeout */
4438 + sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
4439 +
4440 + msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
4441 +
4442 + N_MSG(FUC, "init hardware done!");
4443 +}
4444 +
4445 +/* called by msdc_drv_remove */
4446 +static void msdc_deinit_hw(struct msdc_host *host)
4447 +{
4448 + u32 base = host->base;
4449 +
4450 + /* Disable and clear all interrupts */
4451 + sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
4452 + sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
4453 +
4454 + /* Disable card detection */
4455 + msdc_enable_cd_irq(host, 0);
4456 + // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
4457 +}
4458 +
4459 +/* init gpd and bd list in msdc_drv_probe */
4460 +static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
4461 +{
4462 + gpd_t *gpd = dma->gpd;
4463 + bd_t *bd = dma->bd;
4464 + bd_t *ptr, *prev;
4465 +
4466 + /* we just support one gpd */
4467 + int bdlen = MAX_BD_PER_GPD;
4468 +
4469 + /* init the 2 gpd */
4470 + memset(gpd, 0, sizeof(gpd_t) * 2);
4471 + //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */
4472 + //gpd->next = (dma->gpd_addr + 1); /* bug */
4473 + gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));
4474 +
4475 + //gpd->intr = 0;
4476 + gpd->bdp = 1; /* hwo, cs, bd pointer */
4477 + //gpd->ptr = (void*)virt_to_phys(bd);
4478 + gpd->ptr = (void *)dma->bd_addr; /* physical address */
4479 +
4480 + memset(bd, 0, sizeof(bd_t) * bdlen);
4481 + ptr = bd + bdlen - 1;
4482 + //ptr->eol = 1; /* 0 or 1 [Fix me]*/
4483 + //ptr->next = 0;
4484 +
4485 + while (ptr != bd) {
4486 + prev = ptr - 1;
4487 + prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
4488 + ptr = prev;
4489 + }
4490 +}
4491 +
4492 +static int msdc_drv_probe(struct platform_device *pdev)
4493 +{
4494 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4495 + __iomem void *base;
4496 + struct mmc_host *mmc;
4497 + struct resource *mem;
4498 + struct msdc_host *host;
4499 + struct msdc_hw *hw;
4500 + int ret, irq;
4501 +
4502 + pdev->dev.platform_data = &msdc0_hw;
4503 +
4504 + /* Allocate MMC host for this device */
4505 + mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
4506 + if (!mmc) return -ENOMEM;
4507 +
4508 + hw = (struct msdc_hw*)pdev->dev.platform_data;
4509 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4510 + irq = platform_get_irq(pdev, 0);
4511 +
4512 + //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
4513 +
4514 + base = devm_ioremap_resource(&pdev->dev, res);
4515 + if (IS_ERR(base))
4516 + return PTR_ERR(base);
4517 +
4518 + /* Set host parameters to mmc */
4519 + mmc->ops = &mt_msdc_ops;
4520 + mmc->f_min = HOST_MIN_MCLK;
4521 + mmc->f_max = HOST_MAX_MCLK;
4522 + mmc->ocr_avail = MSDC_OCR_AVAIL;
4523 +
4524 + /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
4525 + For sdio : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
4526 + if (hw->flags & MSDC_HIGHSPEED) {
4527 + mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
4528 + }
4529 + if (hw->data_pins == 4) { /* current data_pins are all 4*/
4530 + mmc->caps |= MMC_CAP_4_BIT_DATA;
4531 + } else if (hw->data_pins == 8) {
4532 + mmc->caps |= MMC_CAP_8_BIT_DATA;
4533 + }
4534 + if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
4535 + mmc->caps |= MMC_CAP_SDIO_IRQ; /* yes for sdio */
4536 +
4537 + mtk_sw_poll = of_property_read_bool(pdev->dev.of_node, "mediatek,cd-poll");
4538 +
4539 + if (mtk_sw_poll)
4540 + mmc->caps |= MMC_CAP_NEEDS_POLL;
4541 +
4542 + /* MMC core transfer sizes tunable parameters */
4543 +#if LINUX_VERSION_CODE > KERNEL_VERSION(3,10,0)
4544 + mmc->max_segs = MAX_HW_SGMTS;
4545 +#else
4546 + mmc->max_hw_segs = MAX_HW_SGMTS;
4547 + mmc->max_phys_segs = MAX_PHY_SGMTS;
4548 +#endif
4549 + mmc->max_seg_size = MAX_SGMT_SZ;
4550 + mmc->max_blk_size = HOST_MAX_BLKSZ;
4551 + mmc->max_req_size = MAX_REQ_SZ;
4552 + mmc->max_blk_count = mmc->max_req_size;
4553 +
4554 + host = mmc_priv(mmc);
4555 + host->hw = hw;
4556 + host->mmc = mmc;
4557 + host->id = pdev->id;
4558 + host->error = 0;
4559 + host->irq = irq;
4560 + host->base = (unsigned long) base;
4561 + host->mclk = 0; /* mclk: the request clock of mmc sub-system */
4562 + host->hclk = hclks[hw->clk_src]; /* hclk: clock of clock source to msdc controller */
4563 + host->sclk = 0; /* sclk: the really clock after divition */
4564 + host->pm_state = PMSG_RESUME;
4565 + host->suspend = 0;
4566 + host->core_clkon = 0;
4567 + host->card_clkon = 0;
4568 + host->core_power = 0;
4569 + host->power_mode = MMC_POWER_OFF;
4570 +// host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
4571 + host->timeout_ns = 0;
4572 + host->timeout_clks = DEFAULT_DTOC * 65536;
4573 +
4574 + host->mrq = NULL;
4575 + //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
4576 +
4577 + host->dma.used_gpd = 0;
4578 + host->dma.used_bd = 0;
4579 +
4580 + /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
4581 + host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL);
4582 + host->dma.bd = dma_alloc_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), &host->dma.bd_addr, GFP_KERNEL);
4583 + BUG_ON((!host->dma.gpd) || (!host->dma.bd));
4584 + msdc_init_gpd_bd(host, &host->dma);
4585 + /*for emmc*/
4586 + msdc_6575_host[pdev->id] = host;
4587 +
4588 +#if 0
4589 + tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
4590 +#else
4591 + INIT_DELAYED_WORK(&host->card_delaywork, msdc_tasklet_card);
4592 +#endif
4593 + spin_lock_init(&host->lock);
4594 + msdc_init_hw(host);
4595 +
4596 + ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
4597 + if (ret) goto release;
4598 + // mt65xx_irq_unmask(irq); /* --- by chhung */
4599 +
4600 + if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
4601 + if (hw->request_cd_eirq) { /* not set for MT6575 */
4602 + hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
4603 + }
4604 + }
4605 +
4606 + if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
4607 + hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
4608 +
4609 + if (hw->register_pm) {/* yes for sdio */
4610 +#ifdef CONFIG_PM
4611 + hw->register_pm(msdc_pm, (void*)host); /* combo_sdio_register_pm() */
4612 +#endif
4613 + if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
4614 + ERR_MSG("MSDC_SYS_SUSPEND and register_pm both set");
4615 + }
4616 + //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
4617 + }
4618 +
4619 + platform_set_drvdata(pdev, mmc);
4620 +
4621 + ret = mmc_add_host(mmc);
4622 + if (ret) goto free_irq;
4623 +
4624 + /* Config card detection pin and enable interrupts */
4625 + if (hw->flags & MSDC_CD_PIN_EN) { /* set for card */
4626 + msdc_enable_cd_irq(host, 1);
4627 + } else {
4628 + msdc_enable_cd_irq(host, 0);
4629 + }
4630 +
4631 + return 0;
4632 +
4633 +free_irq:
4634 + free_irq(irq, host);
4635 +release:
4636 + platform_set_drvdata(pdev, NULL);
4637 + msdc_deinit_hw(host);
4638 +
4639 +#if 0
4640 + tasklet_kill(&host->card_tasklet);
4641 +#else
4642 + cancel_delayed_work_sync(&host->card_delaywork);
4643 +#endif
4644 +
4645 + if (mem)
4646 + release_mem_region(mem->start, mem->end - mem->start + 1);
4647 +
4648 + mmc_free_host(mmc);
4649 +
4650 + return ret;
4651 +}
4652 +
4653 +/* 4 device share one driver, using "drvdata" to show difference */
4654 +static int msdc_drv_remove(struct platform_device *pdev)
4655 +{
4656 + struct mmc_host *mmc;
4657 + struct msdc_host *host;
4658 + struct resource *mem;
4659 +
4660 + mmc = platform_get_drvdata(pdev);
4661 + BUG_ON(!mmc);
4662 +
4663 + host = mmc_priv(mmc);
4664 + BUG_ON(!host);
4665 +
4666 + ERR_MSG("removed !!!");
4667 +
4668 + platform_set_drvdata(pdev, NULL);
4669 + mmc_remove_host(host->mmc);
4670 + msdc_deinit_hw(host);
4671 +
4672 +#if 0
4673 + tasklet_kill(&host->card_tasklet);
4674 +#else
4675 + cancel_delayed_work_sync(&host->card_delaywork);
4676 +#endif
4677 + free_irq(host->irq, host);
4678 +
4679 + dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
4680 + dma_free_coherent(NULL, MAX_BD_NUM * sizeof(bd_t), host->dma.bd, host->dma.bd_addr);
4681 +
4682 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4683 +
4684 + if (mem)
4685 + release_mem_region(mem->start, mem->end - mem->start + 1);
4686 +
4687 + mmc_free_host(host->mmc);
4688 +
4689 + return 0;
4690 +}
4691 +
4692 +/* Fix me: Power Flow */
4693 +#ifdef CONFIG_PM
4694 +static int msdc_drv_suspend(struct platform_device *pdev, pm_message_t state)
4695 +{
4696 + int ret = 0;
4697 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4698 + struct msdc_host *host = mmc_priv(mmc);
4699 +
4700 + if (mmc && state.event == PM_EVENT_SUSPEND && (host->hw->flags & MSDC_SYS_SUSPEND)) { /* will set for card */
4701 + msdc_pm(state, (void*)host);
4702 + }
4703 +
4704 + return ret;
4705 +}
4706 +
4707 +static int msdc_drv_resume(struct platform_device *pdev)
4708 +{
4709 + int ret = 0;
4710 + struct mmc_host *mmc = platform_get_drvdata(pdev);
4711 + struct msdc_host *host = mmc_priv(mmc);
4712 + struct pm_message state;
4713 +
4714 + state.event = PM_EVENT_RESUME;
4715 + if (mmc && (host->hw->flags & MSDC_SYS_SUSPEND)) {/* will set for card */
4716 + msdc_pm(state, (void*)host);
4717 + }
4718 +
4719 + /* This mean WIFI not controller by PM */
4720 +
4721 + return ret;
4722 +}
4723 +#endif
4724 +
4725 +static const struct of_device_id mt7620_sdhci_match[] = {
4726 + { .compatible = "ralink,mt7620-sdhci" },
4727 + {},
4728 +};
4729 +MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
4730 +
4731 +static struct platform_driver mt_msdc_driver = {
4732 + .probe = msdc_drv_probe,
4733 + .remove = msdc_drv_remove,
4734 +#ifdef CONFIG_PM
4735 + .suspend = msdc_drv_suspend,
4736 + .resume = msdc_drv_resume,
4737 +#endif
4738 + .driver = {
4739 + .name = DRV_NAME,
4740 + .owner = THIS_MODULE,
4741 + .of_match_table = mt7620_sdhci_match,
4742 + },
4743 +};
4744 +
4745 +/*--------------------------------------------------------------------------*/
4746 +/* module init/exit */
4747 +/*--------------------------------------------------------------------------*/
4748 +static int __init mt_msdc_init(void)
4749 +{
4750 + int ret;
4751 +/* +++ by chhung */
4752 + u32 reg;
4753 +
4754 +#if defined (CONFIG_MTD_ANY_RALINK)
4755 + extern int ra_check_flash_type(void);
4756 + if(ra_check_flash_type() == 2) { /* NAND */
4757 + printk("%s: !!!!! SDXC Module Initialize Fail !!!!!", __func__);
4758 + return 0;
4759 + }
4760 +#endif
4761 + printk("MTK MSDC device init.\n");
4762 + mtk_sd_device.dev.platform_data = &msdc0_hw;
4763 +if (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7621AT) {
4764 +//#if defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
4765 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<18);
4766 +//#if defined (CONFIG_RALINK_MT7620)
4767 + if (ralink_soc == MT762X_SOC_MT7620A)
4768 + reg |= 0x1<<18;
4769 +//#endif
4770 +} else {
4771 +//#elif defined (CONFIG_RALINK_MT7628)
4772 + /* TODO: maybe omitted when RAether already toggle AGPIO_CFG */
4773 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c));
4774 + reg |= 0x1e << 16;
4775 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x3c), reg);
4776 +
4777 + reg = sdr_read32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60)) & ~(0x3<<10);
4778 +#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
4779 + reg |= 0x3<<26 | 0x3<<28 | 0x3<<30;
4780 + msdc0_hw.data_pins = 8,
4781 +#endif
4782 +//#endif
4783 +}
4784 + sdr_write32((volatile u32*)(RALINK_SYSCTL_BASE + 0x60), reg);
4785 + //platform_device_register(&mtk_sd_device);
4786 +/* end of +++ */
4787 +
4788 + ret = platform_driver_register(&mt_msdc_driver);
4789 + if (ret) {
4790 + printk(KERN_ERR DRV_NAME ": Can't register driver");
4791 + return ret;
4792 + }
4793 + printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
4794 +
4795 +#if defined (MT6575_SD_DEBUG)
4796 + msdc_debug_proc_init();
4797 +#endif
4798 + return 0;
4799 +}
4800 +
4801 +static void __exit mt_msdc_exit(void)
4802 +{
4803 +// platform_device_unregister(&mtk_sd_device);
4804 + platform_driver_unregister(&mt_msdc_driver);
4805 +}
4806 +
4807 +module_init(mt_msdc_init);
4808 +module_exit(mt_msdc_exit);
4809 +MODULE_LICENSE("GPL");
4810 +MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
4811 +MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
4812 +
4813 +EXPORT_SYMBOL(msdc_6575_host);
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