d9bc48d69b0977b1db6e7c1eaec6f0e839ced560
[openwrt/openwrt.git] / target / linux / ramips / patches-4.14 / 0043-spi-add-mt7621-support.patch
1 From 87a5fcd57c577cd94b5b080deb98885077c13a42 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 09:49:07 +0100
4 Subject: [PATCH 43/53] spi: add mt7621 support
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/spi/Kconfig | 6 +
9 drivers/spi/Makefile | 1 +
10 drivers/spi/spi-mt7621.c | 480 ++++++++++++++++++++++++++++++++++++++++++++++
11 3 files changed, 487 insertions(+)
12 create mode 100644 drivers/spi/spi-mt7621.c
13
14 --- a/drivers/spi/Kconfig
15 +++ b/drivers/spi/Kconfig
16 @@ -569,6 +569,12 @@ config SPI_RT2880
17 help
18 This selects a driver for the Ralink RT288x/RT305x SPI Controller.
19
20 +config SPI_MT7621
21 + tristate "MediaTek MT7621 SPI Controller"
22 + depends on RALINK
23 + help
24 + This selects a driver for the MediaTek MT7621 SPI Controller.
25 +
26 config SPI_S3C24XX
27 tristate "Samsung S3C24XX series SPI"
28 depends on ARCH_S3C24XX
29 --- a/drivers/spi/Makefile
30 +++ b/drivers/spi/Makefile
31 @@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC) += spi-mp
32 obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o
33 obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o
34 obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
35 +obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
36 obj-$(CONFIG_SPI_MXS) += spi-mxs.o
37 obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
38 obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
39 --- /dev/null
40 +++ b/drivers/spi/spi-mt7621.c
41 @@ -0,0 +1,494 @@
42 +/*
43 + * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
44 + *
45 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
46 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
47 + * Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
48 + *
49 + * Some parts are based on spi-orion.c:
50 + * Author: Shadi Ammouri <shadi@marvell.com>
51 + * Copyright (C) 2007-2008 Marvell Ltd.
52 + *
53 + * This program is free software; you can redistribute it and/or modify
54 + * it under the terms of the GNU General Public License version 2 as
55 + * published by the Free Software Foundation.
56 + */
57 +
58 +#include <linux/init.h>
59 +#include <linux/module.h>
60 +#include <linux/clk.h>
61 +#include <linux/err.h>
62 +#include <linux/delay.h>
63 +#include <linux/io.h>
64 +#include <linux/reset.h>
65 +#include <linux/spi/spi.h>
66 +#include <linux/of_device.h>
67 +#include <linux/platform_device.h>
68 +#include <linux/swab.h>
69 +
70 +#include <ralink_regs.h>
71 +
72 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
73 +
74 +#define DRIVER_NAME "spi-mt7621"
75 +/* in usec */
76 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
77 +
78 +/* SPISTAT register bit field */
79 +#define SPISTAT_BUSY BIT(0)
80 +
81 +#define MT7621_SPI_TRANS 0x00
82 +#define SPITRANS_BUSY BIT(16)
83 +
84 +#define MT7621_SPI_OPCODE 0x04
85 +#define MT7621_SPI_DATA0 0x08
86 +#define MT7621_SPI_DATA4 0x18
87 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
88 +#define SPI_CTL_START BIT(8)
89 +
90 +#define MT7621_SPI_POLAR 0x38
91 +#define MT7621_SPI_MASTER 0x28
92 +#define MT7621_SPI_MOREBUF 0x2c
93 +#define MT7621_SPI_SPACE 0x3c
94 +
95 +#define MT7621_CPHA BIT(5)
96 +#define MT7621_CPOL BIT(4)
97 +#define MT7621_LSB_FIRST BIT(3)
98 +
99 +#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
100 +
101 +struct mt7621_spi;
102 +
103 +struct mt7621_spi {
104 + struct spi_master *master;
105 + void __iomem *base;
106 + unsigned int sys_freq;
107 + unsigned int speed;
108 + struct clk *clk;
109 +
110 + struct mt7621_spi_ops *ops;
111 +};
112 +
113 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
114 +{
115 + return spi_master_get_devdata(spi->master);
116 +}
117 +
118 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
119 +{
120 + return ioread32(rs->base + reg);
121 +}
122 +
123 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
124 +{
125 + iowrite32(val, rs->base + reg);
126 +}
127 +
128 +static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
129 +{
130 + u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
131 +
132 + master |= 7 << 29;
133 + master |= 1 << 2;
134 +#ifdef CONFIG_SOC_MT7620
135 + if (duplex)
136 + master |= 1 << 10;
137 + else
138 +#endif
139 + master &= ~(1 << 10);
140 +
141 + mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
142 +}
143 +
144 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
145 +{
146 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
147 + int cs = spi->chip_select;
148 + u32 polar = 0;
149 +
150 + mt7621_spi_reset(rs, cs);
151 + if (enable)
152 + polar = BIT(cs);
153 + mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
154 +}
155 +
156 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
157 +{
158 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
159 + u32 rate;
160 + u32 reg;
161 +
162 + dev_dbg(&spi->dev, "speed:%u\n", speed);
163 +
164 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
165 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
166 +
167 + if (rate > 4097)
168 + return -EINVAL;
169 +
170 + if (rate < 2)
171 + rate = 2;
172 +
173 + reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
174 + reg &= ~(0xfff << 16);
175 + reg |= (rate - 2) << 16;
176 + rs->speed = speed;
177 +
178 + reg &= ~MT7621_LSB_FIRST;
179 + if (spi->mode & SPI_LSB_FIRST)
180 + reg |= MT7621_LSB_FIRST;
181 +
182 + reg &= ~(MT7621_CPHA | MT7621_CPOL);
183 + switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
184 + case SPI_MODE_0:
185 + break;
186 + case SPI_MODE_1:
187 + reg |= MT7621_CPHA;
188 + break;
189 + case SPI_MODE_2:
190 + reg |= MT7621_CPOL;
191 + break;
192 + case SPI_MODE_3:
193 + reg |= MT7621_CPOL | MT7621_CPHA;
194 + break;
195 + }
196 + mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
197 +
198 + return 0;
199 +}
200 +
201 +static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
202 +{
203 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
204 + int i;
205 +
206 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
207 + u32 status;
208 +
209 + status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
210 + if ((status & SPITRANS_BUSY) == 0) {
211 + return 0;
212 + }
213 + cpu_relax();
214 + udelay(1);
215 + }
216 +
217 + return -ETIMEDOUT;
218 +}
219 +
220 +static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
221 + struct spi_message *m)
222 +{
223 + struct mt7621_spi *rs = spi_master_get_devdata(master);
224 + struct spi_device *spi = m->spi;
225 + unsigned int speed = spi->max_speed_hz;
226 + struct spi_transfer *t = NULL;
227 + int status = 0;
228 + int i, len = 0;
229 + int rx_len = 0;
230 + u32 data[9] = { 0 };
231 + u32 val;
232 +
233 + mt7621_spi_wait_till_ready(spi);
234 +
235 + list_for_each_entry(t, &m->transfers, transfer_list) {
236 + const u8 *buf = t->tx_buf;
237 +
238 + if (t->rx_buf)
239 + rx_len += t->len;
240 +
241 + if (!buf)
242 + continue;
243 +
244 + if (t->speed_hz < speed)
245 + speed = t->speed_hz;
246 +
247 + /*
248 + * m25p80 might attempt to write more data than we can handle.
249 + * truncate the message to what we can fit into the registers
250 + */
251 + if (len + t->len > 36)
252 + t->len = 36 - len;
253 +
254 + for (i = 0; i < t->len; i++, len++)
255 + data[len / 4] |= buf[i] << (8 * (len & 3));
256 + }
257 +
258 + if (WARN_ON(rx_len > 32)) {
259 + status = -EIO;
260 + goto msg_done;
261 + }
262 +
263 + if (mt7621_spi_prepare(spi, speed)) {
264 + status = -EIO;
265 + goto msg_done;
266 + }
267 + data[0] = swab32(data[0]);
268 + if (len < 4)
269 + data[0] >>= (4 - len) * 8;
270 +
271 + for (i = 0; i < len; i += 4)
272 + mt7621_spi_write(rs, MT7621_SPI_OPCODE + i, data[i / 4]);
273 +
274 + val = (min_t(int, len, 4) * 8) << 24;
275 + if (len > 4)
276 + val |= (len - 4) * 8;
277 + val |= (rx_len * 8) << 12;
278 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
279 +
280 + mt7621_spi_set_cs(spi, 1);
281 +
282 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
283 + val |= SPI_CTL_START;
284 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
285 +
286 + mt7621_spi_wait_till_ready(spi);
287 +
288 + mt7621_spi_set_cs(spi, 0);
289 +
290 + for (i = 0; i < rx_len; i += 4)
291 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
292 +
293 + m->actual_length = len + rx_len;
294 +
295 + len = 0;
296 + list_for_each_entry(t, &m->transfers, transfer_list) {
297 + u8 *buf = t->rx_buf;
298 +
299 + if (!buf)
300 + continue;
301 +
302 + for (i = 0; i < t->len; i++, len++)
303 + buf[i] = data[len / 4] >> (8 * (len & 3));
304 + }
305 +
306 +msg_done:
307 + m->status = status;
308 + spi_finalize_current_message(master);
309 +
310 + return 0;
311 +}
312 +
313 +#ifdef CONFIG_SOC_MT7620
314 +static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
315 + struct spi_message *m)
316 +{
317 + struct mt7621_spi *rs = spi_master_get_devdata(master);
318 + struct spi_device *spi = m->spi;
319 + unsigned int speed = spi->max_speed_hz;
320 + struct spi_transfer *t = NULL;
321 + int status = 0;
322 + int i, len = 0;
323 + int rx_len = 0;
324 + u32 data[9] = { 0 };
325 + u32 val = 0;
326 +
327 + mt7621_spi_wait_till_ready(spi);
328 +
329 + list_for_each_entry(t, &m->transfers, transfer_list) {
330 + const u8 *buf = t->tx_buf;
331 +
332 + if (t->rx_buf)
333 + rx_len += t->len;
334 +
335 + if (!buf)
336 + continue;
337 +
338 + if (WARN_ON(len + t->len > 16)) {
339 + status = -EIO;
340 + goto msg_done;
341 + }
342 +
343 + for (i = 0; i < t->len; i++, len++)
344 + data[len / 4] |= buf[i] << (8 * (len & 3));
345 + if (speed > t->speed_hz)
346 + speed = t->speed_hz;
347 + }
348 +
349 + if (WARN_ON(rx_len > 16)) {
350 + status = -EIO;
351 + goto msg_done;
352 + }
353 +
354 + if (mt7621_spi_prepare(spi, speed)) {
355 + status = -EIO;
356 + goto msg_done;
357 + }
358 +
359 + for (i = 0; i < len; i += 4)
360 + mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
361 +
362 + val |= len * 8;
363 + val |= (rx_len * 8) << 12;
364 + mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
365 +
366 + mt7621_spi_set_cs(spi, 1);
367 +
368 + val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
369 + val |= SPI_CTL_START;
370 + mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
371 +
372 + mt7621_spi_wait_till_ready(spi);
373 +
374 + mt7621_spi_set_cs(spi, 0);
375 +
376 + for (i = 0; i < rx_len; i += 4)
377 + data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
378 +
379 + m->actual_length = rx_len;
380 +
381 + len = 0;
382 + list_for_each_entry(t, &m->transfers, transfer_list) {
383 + u8 *buf = t->rx_buf;
384 +
385 + if (!buf)
386 + continue;
387 +
388 + for (i = 0; i < t->len; i++, len++)
389 + buf[i] = data[len / 4] >> (8 * (len & 3));
390 + }
391 +
392 +msg_done:
393 + m->status = status;
394 + spi_finalize_current_message(master);
395 +
396 + return 0;
397 +}
398 +#endif
399 +
400 +static int mt7621_spi_transfer_one_message(struct spi_master *master,
401 + struct spi_message *m)
402 +{
403 + struct spi_device *spi = m->spi;
404 +#ifdef CONFIG_SOC_MT7620
405 + int cs = spi->chip_select;
406 +
407 + if (cs)
408 + return mt7621_spi_transfer_full_duplex(master, m);
409 +#endif
410 + return mt7621_spi_transfer_half_duplex(master, m);
411 +}
412 +
413 +static int mt7621_spi_setup(struct spi_device *spi)
414 +{
415 + struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
416 +
417 + if ((spi->max_speed_hz == 0) ||
418 + (spi->max_speed_hz > (rs->sys_freq / 2)))
419 + spi->max_speed_hz = (rs->sys_freq / 2);
420 +
421 + if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
422 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
423 + spi->max_speed_hz);
424 + return -EINVAL;
425 + }
426 +
427 + return 0;
428 +}
429 +
430 +static const struct of_device_id mt7621_spi_match[] = {
431 + { .compatible = "ralink,mt7621-spi" },
432 + {},
433 +};
434 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
435 +
436 +static size_t mt7621_max_transfer_size(struct spi_device *spi)
437 +{
438 + return 32;
439 +}
440 +
441 +static int mt7621_spi_probe(struct platform_device *pdev)
442 +{
443 + const struct of_device_id *match;
444 + struct spi_master *master;
445 + struct mt7621_spi *rs;
446 + void __iomem *base;
447 + struct resource *r;
448 + int status = 0;
449 + struct clk *clk;
450 + struct mt7621_spi_ops *ops;
451 +
452 + match = of_match_device(mt7621_spi_match, &pdev->dev);
453 + if (!match)
454 + return -EINVAL;
455 + ops = (struct mt7621_spi_ops *)match->data;
456 +
457 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
458 + base = devm_ioremap_resource(&pdev->dev, r);
459 + if (IS_ERR(base))
460 + return PTR_ERR(base);
461 +
462 + clk = devm_clk_get(&pdev->dev, NULL);
463 + if (IS_ERR(clk)) {
464 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
465 + status);
466 + return PTR_ERR(clk);
467 + }
468 +
469 + status = clk_prepare_enable(clk);
470 + if (status)
471 + return status;
472 +
473 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
474 + if (master == NULL) {
475 + dev_info(&pdev->dev, "master allocation failed\n");
476 + return -ENOMEM;
477 + }
478 +
479 + master->mode_bits = RT2880_SPI_MODE_BITS;
480 +
481 + master->setup = mt7621_spi_setup;
482 + master->transfer_one_message = mt7621_spi_transfer_one_message;
483 + master->bits_per_word_mask = SPI_BPW_MASK(8);
484 + master->dev.of_node = pdev->dev.of_node;
485 + master->num_chipselect = 2;
486 + master->max_transfer_size = mt7621_max_transfer_size;
487 +
488 + dev_set_drvdata(&pdev->dev, master);
489 +
490 + rs = spi_master_get_devdata(master);
491 + rs->base = base;
492 + rs->clk = clk;
493 + rs->master = master;
494 + rs->sys_freq = clk_get_rate(rs->clk);
495 + rs->ops = ops;
496 + dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
497 +
498 + device_reset(&pdev->dev);
499 +
500 + mt7621_spi_reset(rs, 0);
501 +
502 + return spi_register_master(master);
503 +}
504 +
505 +static int mt7621_spi_remove(struct platform_device *pdev)
506 +{
507 + struct spi_master *master;
508 + struct mt7621_spi *rs;
509 +
510 + master = dev_get_drvdata(&pdev->dev);
511 + rs = spi_master_get_devdata(master);
512 +
513 + clk_disable(rs->clk);
514 + spi_unregister_master(master);
515 +
516 + return 0;
517 +}
518 +
519 +MODULE_ALIAS("platform:" DRIVER_NAME);
520 +
521 +static struct platform_driver mt7621_spi_driver = {
522 + .driver = {
523 + .name = DRIVER_NAME,
524 + .owner = THIS_MODULE,
525 + .of_match_table = mt7621_spi_match,
526 + },
527 + .probe = mt7621_spi_probe,
528 + .remove = mt7621_spi_remove,
529 +};
530 +
531 +module_platform_driver(mt7621_spi_driver);
532 +
533 +MODULE_DESCRIPTION("MT7621 SPI driver");
534 +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
535 +MODULE_LICENSE("GPL");